Method, device, chip and terminal for wireless communication

Abstract

The present application provides a method, device, chip and terminal for wireless communication. The method includes: determining the target number of coding blocks contained in a transmission block to be decoded, determining the number of decoding iterations according to the target number of coding blocks and the target corresponding relationship, the target corresponding relationship including the corresponding relationship between the target number of decoding iterations and the target number of coding blocks, and in the process of decoding the transmission block, in response to the current number of decoding iterations being greater than or equal to the number of iterations, outputting the decoding result of the transmission block. By dynamically determining the number of decoding iterations, the decoding performance and system resource utilization efficiency can be improved.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a method, device, chip and terminal for wireless communication. Background Art

[0002] In communication systems using iterative decoders, the number of decoder iterations has a significant impact on decoding performance and system resource utilization. Conventional iterative decoders usually use a fixed number of iterations, but under different communication scenarios and data conditions, the fixed number of iterations may not be able to meet both performance and efficiency requirements. Summary of the invention

[0003] In view of this, the purpose of the present application is to propose a method, device, chip and terminal for wireless communication to solve or partially solve the above-mentioned problems.

[0004] Based on the above purpose, in a first aspect, the present application provides a method for wireless communication, including:

[0005] Determining a target number of coded blocks contained in a transport block to be decoded;

[0006] Determining the number of decoding iterations according to the target number of coding blocks and the target corresponding relationship, wherein the target corresponding relationship includes a corresponding relationship between the target number of decoding iterations and the target number of coding blocks;

[0007] In a process of decoding the transport block, in response to a current number of decoding iterations being greater than or equal to the number of iterations, a decoding result of the transport block is output.

[0008] In a second aspect of the present application, a device for wireless communication is provided, including:

[0009] A first determination module is configured to determine a target number of coding blocks of coding blocks included in a transport block to be decoded;

[0010] A second determination module is configured to determine the number of decoding iterations according to the target number of coding blocks and a target corresponding relationship, wherein the target corresponding relationship includes a corresponding relationship between the target number of decoding iterations and the target number of coding blocks;

[0011] The output module is configured to output a decoding result of the transport block in response to a current number of decoding iterations being greater than or equal to the number of iterations during decoding of the transport block.

[0012] In a third aspect of the present application, a chip is provided, comprising a programmable logic circuit and / or program instructions, which is used to implement the method described in the first aspect when the chip is running.

[0013] In a fourth aspect of the present application, a terminal is provided, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the method described in the first aspect is implemented.

[0014] As can be seen from the above, the present application provides a method, device, chip and terminal for wireless communication. The method includes: determining the target number of coding blocks contained in the transmission block to be decoded, determining the number of decoding iterations according to the target number of coding blocks and the target correspondence, the target correspondence includes the correspondence between the target number of decoding iterations and the target number of coding blocks, and in the process of decoding the transmission block, in response to the current number of decoding iterations being greater than or equal to the number of iterations, outputting the decoding result of the transmission block. By dynamically determining the number of decoding iterations, the decoding performance and system resource utilization efficiency can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the present application or related technologies, the drawings required for use in the embodiments or related technical descriptions are briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0016] Figure 1A A schematic diagram of an exemplary terminal according to an embodiment of the present application is shown.

[0017] Figure 1B A schematic diagram of an exemplary decoding iteration process according to an embodiment of the present application is shown.

[0018] Figure 2 A schematic diagram of an exemplary decoding process and a modular unit composition using adaptive selection of the number of iterations according to an embodiment of the present application is shown.

[0019] Figure 3 A schematic flow chart of an exemplary method for wireless communication according to an embodiment of the present application is shown.

[0020] Figure 4 A schematic diagram of an exemplary device for wireless communication according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0021] In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0022] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present application should be the usual meanings understood by people with ordinary skills in the field to which the present application belongs. The "first", "second" and similar words used in the embodiments of the present application do not represent any order, quantity or importance, but are only used to distinguish different components. "Including" or "comprising" and similar words mean that the elements or objects appearing in front of the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0023] In communication systems using iterative decoders, the number of decoder iterations has a significant impact on decoding performance and system resource utilization. Conventional iterative decoders usually use a fixed number of iterations, but under different communication scenarios and data conditions, the fixed number of iterations may not be able to meet both performance and efficiency requirements.

[0024] Communication systems are developing rapidly, and the requirements for data transmission accuracy and efficiency are constantly increasing. Iterative decoding algorithms such as Turbo Codes (Turbo Codes) and Low-Density Parity-Check Codes (LDPC Codes) are widely used in modern communication systems as an efficient channel coding method. Iterative decoders improve decoding performance through iterative decoding, but the traditional fixed number of iterations is difficult to adapt to complex and changing communication environments.

[0025] The basic principle of Turbo decoder is to approach the optimal decoding result through iteration between soft input soft output (SISO) decoders. In each iteration, the decoder calculates based on the received channel information and the output of the previous iteration, gradually improving the decoding accuracy. However, different factors such as data block size and channel conditions will result in different optimal number of iterations required.

[0026] The basic principle of LDPC decoding is to decode LDPC codes through message passing algorithms, such as Belief Propagation (BP) or Min-Sum Algorithm (MSA). This process usually includes multiple iterations of the received soft information. In each iteration, the decoder updates the state of the node based on the received signal and the message passed between the check node and the variable node. Through these iterations, the decoder gradually optimizes the channel information and coding constraints to approach the optimal decoding result. Since LDPC codes have a sparse parity check matrix, the computational complexity of each iteration is low, allowing it to maintain good performance in the case of larger code lengths. However, the convergence speed of decoding is affected by many factors, such as code length, channel noise, and the decoding algorithm used. Different scenarios may require different numbers of iterations to achieve ideal decoding performance.

[0027] The existing technical solutions usually use a given maximum number of iterations as the peak number of iterations of the iterative decoder. The following takes the Turbo decoder of the 4th Generation mobile communication technology (4G) Long Term Evolution (LTE) system as an example to introduce the technical solution. The communication system using the LDPC decoder, which is also an iterative decoder, is similar to the system using the Turbo decoder, and will not be repeated here.

[0028] At present, when designing a turbo decoder, a fixed maximum number of iterations is usually pre-set based on the throughput requirements of the hardware design and the estimation of some typical scenarios. For example, the commonly used default maximum number of iterations is 16, where the number of iterations is defined as one iteration for each SISO component decoder to run once, i.e., half a round of iterations. Since each turbo decoder has two SISO component decodings to process, 16 iterations are equivalent to 8 full rounds of iterations.

[0029] Figure 1A A schematic diagram of an exemplary terminal 100 according to an embodiment of the present application is shown, and the terminal 100 may include: a processor 1010, a memory 1020, an input / output interface 1030, a communication interface 1040, and a bus 1050. The processor 1010, the memory 1020, the input / output interface 1030, and the communication interface 1040 are connected to each other in communication within the device through the bus 1050.

[0030] The processor 1010 can be implemented by a general-purpose CPU (Central Processing Unit), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this specification.

[0031] The memory 1020 may be implemented in the form of ROM (Read Only Memory), RAM (Random Access Memory), static storage device, dynamic storage device, etc. The memory 1020 may store an operating system and other application programs. When the technical solutions provided in the embodiments of this specification are implemented by software or firmware, the relevant program codes are stored in the memory 1020 and are called and executed by the processor 1010.

[0032] The input / output interface 1030 is used to connect the input / output module to realize information input and output. The input / output module can be configured in the device as a component (not shown in the figure), or it can be externally connected to the device to provide corresponding functions. The input device may include a keyboard, a mouse, a touch screen, a microphone, various sensors, etc., and the output device may include a display, a speaker, a vibrator, an indicator light, etc.

[0033] The communication interface 1040 is used to connect a communication module (not shown) to realize communication interaction between the device and other devices. The communication module can realize communication through wired means (such as USB, network cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.).

[0034] The bus 1050 includes a path that transmits information between the various components of the device (eg, the processor 1010 , the memory 1020 , the input / output interface 1030 , and the communication interface 1040 ).

[0035] It should be noted that, although the above device only shows the processor 1010, the memory 1020, the input / output interface 1030, the communication interface 1040 and the bus 1050, in the specific implementation process, the device may also include other components necessary for normal operation. In addition, it can be understood by those skilled in the art that the above device may also only include the components necessary for implementing the embodiments of the present specification, and does not necessarily include all the components shown in the figure.

[0036] Figure 1B A schematic diagram of an exemplary decoding iteration process according to an embodiment of the present application is shown.

[0037] The Turbo decoder has two component decoders (SISO#0 component decoder and SISO#1 component decoder). Figure 1B As shown, the decoding process is that after receiving the soft bit (step 101), the Turbo decoder inputs it to the SISO#0 component decoder for decoding (step 102). After the decoding is completed, the output hard bit is judged in advance (step 103). If the ET judgment condition is met, the entire decoding is completed (step 104) and the iteration loop is jumped out; if the ET judgment condition is not met, it is determined whether the current number of iterations is less than the maximum number of iterations (step 105); if the current number of iterations is less than the maximum number of iterations, the next iteration is continued, and the SISO#1 component decoder is decoded (step 106), and the same ET judgment is performed on the output of the SISO#1 component decoder (step 107); if the ET judgment condition is not met, it is determined whether the current number of iterations is less than the maximum number of iterations (step 108); if the current number of iterations is less than the maximum number of iterations, it returns to step 102, continues to perform the SISO#0 component decoder decoding and enters the next round of iteration, and so on. If each round of iteration of the SISO#0 component decoder and the SISO#1 component decoder does not meet the ET judgment condition, when the current iteration number reaches the maximum iteration number, the iteration is stopped and the decoding ends.

[0038] The ET decision here includes the cyclic redundancy check (CRC) check decision and various early stopping algorithm decisions. For example, the decision condition can set the threshold condition of the ET algorithm. In this way, although the decoding error occurs, the iteration is terminated when the threshold condition of the set ET algorithm is reached. It is not repeated here.

[0039] It can be seen that the existing iterative decoder adopts a fixed number of iterations, which cannot be adjusted dynamically according to the actual communication scenario and data conditions, resulting in waste of system resources or insufficient decoding performance. The fixed number of iterations lacks flexibility and adaptability, and does not consider the system load and resource allocation, resulting in low scheduling efficiency and limited performance. In the case of poor channel link quality and high bit error, the fixed maximum number of iterations cannot fully utilize the error correction capability of the iterative decoder. In addition, the fixed number of iterations easily causes the decoder to perform too many iterations when it is not necessary, which increases the waste of system resources (such as computing time, energy consumption, etc.) and reduces the overall efficiency of the system.

[0040] In order to at least solve the above problems, the present application provides a method, device, chip and terminal for wireless communication. The method includes: determining the target number of coding blocks contained in the transmission block to be decoded, determining the number of decoding iterations according to the target number of coding blocks and the target corresponding relationship, the target corresponding relationship includes the corresponding relationship between the target number of decoding iterations and the target number of coding blocks, and in the process of decoding the transmission block, in response to the current number of decoding iterations being greater than or equal to the number of iterations, outputting the decoding result of the transmission block. By dynamically determining the number of decoding iterations, the decoding performance and system resource utilization efficiency can be improved.

[0041] Figure 2 A schematic diagram of an exemplary decoding process and a modular unit composition using adaptive selection of the number of iterations according to an embodiment of the present application is shown.

[0042] like Figure 2 As shown, the maximum dynamic iteration number calculation unit (Max Iter Num Cal unit) before entering the decoder will be called once in each time slot, that is, the processing cycle is 1ms. In some embodiments, the Max Iter Num Cal unit is mainly divided into a transport block size calculation module (Transport Block Size Calculation, TBS Cal), a coding block segmentation module (CB segmentation), and a maximum iteration number selection module (Max Iter Num Selection).

[0043] In the transport block size calculation module, in some embodiments, the size of the transport block can be determined according to the TBS calculation method specified in section 7.1.7.2 of the 3rd Generation Partnership Project (3GPP) 36213 protocol, for example, by looking up the table based on the resource block (RB) data allocated to the current transport block (TB) and the input modulation and coding scheme (MCS) sequence number, which is not repeated here.

[0044] A transport block is a basic unit for data transmission in wireless communication systems. A coding block is an intermediate unit of a transport block in the physical layer coding process. In order to improve coding efficiency and reduce decoding complexity, a transport block is usually divided into multiple coding blocks.

[0045] In the coding block segmentation module, in some embodiments, the target number of coding blocks included in the transport block to be decoded can be determined. The number of coding blocks (CB) can be calculated according to the algorithm for coding block segmentation in section 5.1.2 of the 3GPP 36212 protocol, which will not be described in detail here.

[0046] The selection of the maximum number of iterations needs to be made according to the hardware capabilities. Usually used in low-power LTE terminals, the clock frequency of the Turbo decoder is usually high, and the clock frequency may be between tens of MHz and hundreds of MHz. The following takes 491.52MHz as the clock frequency of the Turbo decoder as an example to illustrate the selection of the maximum number of iterations. In some embodiments, the maximum number of iterations can be dynamically selected according to the number of CBs, and the target number of iterations for decoding (for example, the maximum number of iterations) can be determined according to the target number of coding blocks and the target correspondence. The target correspondence may include a correspondence between the target number of iterations for decoding and the target number of coding blocks, where the target number of iterations may be the maximum number of iterations. The correspondence between the maximum number of iterations (nIter) and the target number of coding blocks (nCB) is shown in Table 1.

[0047] Table 1: Correspondence between the maximum number of iterations and the number of target coding blocks.

[0048]

[0049] After the target number of iterations is determined, during the decoding process of the transport block, when the current number of decoding iterations is greater than or equal to the target number of iterations, the decoding result of the transport block can be output. In this way, by dynamically and adaptively determining the target number of iterations instead of a fixed number of iterations, the decoding performance and system resource utilization efficiency can be improved.

[0050] The following is an explanation of the principle of dynamic selection of the maximum number of iterations. It can be calculated by the following formula:

[0051]

[0052] in, is the clock frequency of 1 time slot; is the duty cycle; is the decoder processing time for each CB; It is the number of all CBs in the current time slot. The time slot is the basic time unit for data transmission.

[0053] For different transmission scenarios, it is necessary to consider the processing power of the hardware and determine the target correspondence through different calculation methods. In some embodiments, for the scenario of transmitting one transmission block in one time slot (for example, a single TB scenario), the target correspondence can be determined based on the number of coding blocks of the coding blocks contained in one transmission block (for example, the second number of coding blocks). For the scenario of transmitting multiple transmission blocks in one time slot (for example, a multi-TB scenario), the target correspondence can be determined based on the number of coding blocks of the coding blocks contained in multiple transmission blocks (for example, the third number of coding blocks). In this way, by considering different transmission scenarios and selecting different calculation methods for the maximum number of iterations, it is possible to avoid the number of iterations being too large and exceeding the processing power of the hardware.

[0054] For the calculation of the maximum number of iterations in a single TB scenario, the principle is explained by taking 491.52 MHz as the clock frequency of the Turbo decoder as an example.

[0055] In some embodiments, a first clock frequency of a decoder and a first duty cycle of a processor may be determined. At the same time, a first processing time required for decoding a coding block may be determined. A first number of decoding iterations may be determined based on the first clock frequency, the first duty cycle, the first processing time, and the second number of coding blocks, and a target corresponding relationship may be determined based on the first number of iterations and the first number of coding blocks.

[0056] The hardware used to implement the functions of the decoder can be an application-specific integrated circuit (ASIC). Assuming that the first duty cycle of the application-specific integrated circuit is 0.9, the Turbo decoder performs parallel processing with a maximum of 4 parallel blocks. For example, the Radix-4 algorithm can be used to implement parallel processing of decoding. In some embodiments, decoding can be performed based on a sliding window algorithm. The main idea of ​​the sliding window is to divide the entire block of data into multiple sub-windows of fixed length and execute the decoding algorithm separately, and then combine the decoding results. Only the state measurement of the length of a sub-window needs to be stored each time, which can greatly save storage space. Assume that the length of each sliding window (Sliding Window, SW) in the embodiment of the present application is 64 bits, 2 bits of data are decoded each time, and 32 times of processing are performed to complete a sliding window calculation.

[0057] Taking the LTE single TB scenario as an example, according to the 3GPP 36213 protocol, the maximum TBS value is 75376 bits. According to the algorithm for coding block segmentation in Section 5.1.2 of the 3GPP36212 protocol, it is divided into 13 coding blocks, and the maximum coding block length (CB Size) is 6144 bits. The processing time of the Turbo decoder for one time slot needs to meet the following formula:

[0058]

[0059]

[0060] That is, the processing time of the Turbo decoder called by all coding blocks in each time slot must not exceed the maximum processing capacity of the ASIC hardware processing.

[0061] In the above formula, Indicates the iteration number (for example, the first iteration number); Hz is the first clock frequency of the Turbo decoder designed for ASIC hardware; is the first duty cycle of the ASIC hardware; is the first processing time required to process a coding block, where bit is the maximum length of a coding block in LTE. represents two SISO component decoders, is the parallelism of the Turbo decoder (the parallel processing of the Turbo decoder refers to the decoder segmenting the input data. Taking the maximum code block length of LTE as 6144 bits, 4 parallel decoding means that 4 segments of data, each with a length of 1536 bits, are decoded in parallel at the same time). times is the number of times the Radix-4 algorithm is used to decode the first sliding window of each length of 64 bits; +1 represents the time taken by the interleaver between decoders and the time reserved for the transmission of the metrics of the previous and next items; The second coding block number representing the coding blocks included in a transport block transmitted in one time slot.

[0062] In some embodiments, the first clock frequency may be multiplied by the first duty cycle (eg, ), obtain a first value; determine a first processing number of decoding each of the first sliding windows (for example, ); according to the product of the first processing time, the first processing number and the first number of coding blocks (for example, ), obtain the second value; according to the ratio of the first value to the second value (for example, ), determine a first number of iterations, the first number of iterations being less than or equal to the ratio of the first value to the second value (for example, ).

[0063] Assuming that the maximum number of coding blocks transmitted in a time slot in a single TB scenario is 13, the following corresponding relationship between the first iteration number and the first coding block number can be obtained based on the above calculation method.

[0064] Table 2: Correspondence between the number of first iterations and the number of first coding blocks.

[0065]

[0066] Normally, the parameter register of the Turbo decoder output to the ASIC hardware design is configured with 5 bits, that is, the maximum number of iterations is 31 times to meet the decoding requirements, that is, after exceeding 31 times, Turbo decoding can be performed with 31 iterations.

[0067] Therefore, in some embodiments, for all single TB scenarios, ie, the number of second coding blocks ≤ 13, the Turbo decoder of each coding block may adopt a maximum number of 31 iterations.

[0068] For scenarios with more than 13 CBs in one time slot, i.e., multi-TB scenarios, the processing capacity of the hardware may be exceeded, so calculations for more scenarios need to be considered.

[0069] In some embodiments, a second clock frequency of the decoder and a second duty cycle of the processor may be determined, a second processing time required for decoding one coding block and a third processing time required for decoding multiple coding blocks may be determined, the number of common transmission blocks in the multiple transmission blocks may be determined, and a second number of decoding iterations may be determined based on the second clock frequency, the second duty cycle, the second processing time, the third processing time, the number of common transmission blocks, and the second number of coding blocks. A target correspondence relationship may be determined based on the second number of iterations and the second number of coding blocks.

[0070] In LTE, the maximum number of coding blocks in a time slot may exceed 13 in a multi-TB scenario.

[0071] In the LTE system, a time slot may carry multiple PDSCH (physical channel for downlink data transmission) data streams at the same time. Taking the conventional specification with a maximum carrying capacity of 4 PDSCHs (2 unicast TBs and 2 common TBs) as an example, the maximum number of coding blocks that can be carried is 2×12+2=26 coding blocks. PDSCH (Physical Downlink Shared Channel) is a physical channel in the LTE system, used to carry data from the downlink transport channel (DSCH), and is the downlink channel that mainly carries user data.

[0072] This is because, for the LTE system with a maximum bandwidth of 20MHz, dual unicast TB belongs to the dual codeword scenario. At this time, a maximum of 96 resource blocks can be configured. According to the provisions of the 3GPP 36213 protocol, the MCS index value is set to a maximum value of 28. At this time, looking up Table 7.1.7.2.1-1 can only get the maximum transport block size of 71112 bits. According to the algorithm for code block segmentation in Chapter 5.1.2 of 3GPP36212, it can only be divided into 12 coding blocks, each with a length of 5952 bits.

[0073] The public transport block only supports the maximum Quadrature Phase Shift Keying (QPSK) modulation. In the 100 resource blocks of 20MHz, at most 4 resource blocks are allocated to the public transport block. According to Table 7.1.7.2.1-1 of the 3GPP36213 protocol, the maximum possible public transport block size is 616 bits, which is less than 6144 bits. Therefore, the public transport block belongs to a single TB.

[0074] Therefore, the calculation method for the maximum number of iterations (for example, the second iteration number) in the above multi-TB maximum extreme scenario is:

[0075]

[0076] in, Indicates the iteration number (for example, the second iteration number); Hz is the second clock frequency of the Turbo decoder designed for ASIC hardware; is the second duty cycle of the ASIC hardware; The second processing time required to process one coding block, where bit is the maximum length of a coding block in a multi-TB scenario in LTE. represents two SISO component decoders, is the parallelism of the Turbo decoder (the parallel processing of the Turbo decoder refers to the decoder segmenting the input data. Taking the maximum coding block length of LTE as 5952 bits, 4 parallel decoding means that 4 segments of data, each with a length of 1488 bits, are decoded in parallel at the same time). The second is the number of times the Radix-4 algorithm is used to decode each second sliding window of 64 bits in length; +1 represents the time taken by the interleaver between decoders and the time reserved for the transmission of the previous and next terms; A third number of coding blocks representing coding blocks included in a plurality of transport blocks transmitted in one time slot; Indicates the number of common transport blocks in a plurality of transport blocks; represents the third processing time required to decode multiple coding blocks; 1 represents 1 parallel block and 2 represents two SISO component decoders.

[0077] In some embodiments, the second clock frequency may be multiplied by the second duty cycle (eg, ), obtain a third value; determine the second processing times for decoding each second sliding window (for example, ); according to the second processing time, the second processing number and the product of the number of common transport blocks and the second number of coding blocks (for example, ), obtain a fourth value; according to the product of the third processing time, the number of common transport blocks and the second number of coding blocks (for example, ), and obtain the fifth value; according to the sum of the fourth value and the fifth value (for example, ), obtain the sixth value; according to the ratio of the third value and the sixth value (for example, ), determine a second iteration number, the second iteration number is less than or equal to the ratio of the third value to the sixth value (for example, ).

[0078] The calculation of the maximum number of iterations corresponding to different numbers of coding blocks is derived based on the maximum coding block length of LTE specified in the 3GPP 36212 protocol:

[0079]

[0080] Based on the derived correspondence between the maximum number of iterations and the number of coding blocks, Table 3 can be obtained:

[0081] Table 3: Correspondence between the maximum number of iterations and the number of coding blocks.

[0082]

[0083] Among them, nCB can take a maximum value of 26 according to the most extreme case possible in 3GPP, and nIter=22 at this time; when nCB=17, nIter is calculated to be 32. According to the general design, all nCB≤17 can use 31 iterations. Therefore, in some embodiments, the correspondence between the maximum number of iterations and the target number of coding blocks shown in Table 1 can be used as an implementation plan for dynamically selecting the number of iterations according to the number of coding blocks. In some embodiments, the maximum number of iterations can be dynamically allocated to the decoder called in each time slot, so that the maximum number of iterations can be allocated without exceeding the hardware processing capacity, so as to increase the probability of successful decoding and improve decoding performance.

[0084] After executing the maximum dynamic iteration number calculation unit, if Figure 2 As shown, it will enter the Turbo Decoder unit. The Turbo Decoder will process each coding block once, and all coding blocks will use the same maximum number of iterations for decoding operations.

[0085] After adopting the dynamically allocated maximum number of iterations, the Turbo decoder (for example, the SISO#0 component decoder and the SISO#1 component decoder) will perform decoding according to normal iterations. If ET enable (including CRC check judgment) takes effect, the iteration will be stopped and the decoding will be terminated.

[0086] The embodiments of the present application are applicable to all iterative decoder communication systems including Turbo decoders, LDPC (Low Density Parity Check Code) decoders, etc., including but not limited to the third generation mobile communication technology (3G), 4G communication standards, satellite communications, digital broadcasting and other communication systems using Turbo coding technology, the fifth generation mobile communication technology (5G) communication standards, WIFI (Wireless Fidelity), WiMAX (Worldwide Interoperability for Microwave Access), satellite navigation systems, satellite broadcasting systems, optical communication systems, sensor networks, mobile multimedia broadcasting and other communication systems using iterative LDPC decoding schemes.

[0087] The embodiments of this application only focus on the dynamic iteration algorithm of the Turbo decoder in 4G LTE, and do not limit the scope of protection of this application. For different hardware processing capabilities and different decoder solutions, the final simplified lookup table can be derived according to the formula in this solution, and the maximum number of iterations can be adaptively selected.

[0088] For example, for different hardware processing capabilities, the numerator in the following formula can be adjusted and , which can be determined based on the design specifications of the system.

[0089] In the case where different transport blocks in a time slot have different numbers of coding blocks, each transport block contains a different number of coding blocks. The processing time required to decode all coding blocks of each transport block in the above formula can be accumulated as the denominator for calculation.

[0090] Different decoder schemes, such as Turbo decoder and LDPC decoder, can calculate the denominator processTime of the above formula according to the specific actual processing time, and then calculate the final number of iterations.

[0091] Different decoding algorithms for the same decoding, such as Turbo decoders using different parallel segmentation and windowing modes, can all be calculated by referring to the above algorithm formula to obtain different processTimes, and then calculate the final number of iterations.

[0092] If there is a Hybrid Automatic Retransmission Request (HARQ) retransmission, the MCS obtained when parsing the retransmitted Downlink Control Information (DCI) may be smaller than the initial transmission, resulting in a smaller calculated transport block size and number of coding blocks, which in turn leads to a larger number of iterations calculated by table lookup.

[0093] However, according to the HARQ scheduling criteria, the retransmission is calculated using the initial transmission block size. Therefore, it is possible that the actual number of iterations used for the retransmission is too high and exceeds the hardware bottleneck, causing the hardware to crash. Therefore, the most effective and safe approach is to use the same maximum number of iterations for the retransmission as the initial transmission, the same as the transmission block size.

[0094] Figure 3 FIG. 3 is a flow chart of an exemplary method 300 for wireless communication according to an embodiment of the present application. The method 300 may be executed by the terminal 100, such as Figure 3 As shown, method 300 may include the following steps.

[0095] In step 302, a target number of coding blocks included in a transport block to be decoded is determined.

[0096] In step 304, the number of decoding iterations is determined according to the target number of coding blocks and the target corresponding relationship, wherein the target corresponding relationship includes a corresponding relationship between the target number of decoding iterations and the target number of coding blocks.

[0097] In some embodiments, the target number of coding blocks includes a first number of coding blocks and a second number of coding blocks, and the method further includes: in response to transmitting one of the transmission blocks in a time slot, determining the target correspondence relationship based on the first number of coding blocks of the coding blocks contained in one of the transmission blocks; in response to transmitting multiple of the transmission blocks in a time slot, determining the target correspondence relationship based on the second number of coding blocks of the coding blocks contained in multiple of the transmission blocks.

[0098] In some embodiments, the target number of iterations includes a first number of iterations, and in response to transmitting one of the transmission blocks in a time slot, determining the target correspondence based on the first number of coding blocks of the coding blocks included in one of the transmission blocks further includes: determining a first clock frequency of the decoder and a first duty cycle of the processor; determining a first processing time required to decode one of the coding blocks; determining the first number of iterations of decoding based on the first clock frequency, the first duty cycle, the first processing time and the second number of coding blocks; determining the target correspondence based on the first number of iterations and the first number of coding blocks.

[0099] In some embodiments, the target number of iterations includes a second number of iterations, and in response to transmitting a plurality of the transmission blocks within a time slot, determining the target correspondence based on the second number of coding blocks of the coding blocks included in the plurality of the transmission blocks further includes: determining a second clock frequency of the decoder and a second duty cycle of the processor; determining a second processing time required for decoding one coding block and a third processing time required for decoding a plurality of coding blocks; determining the number of common transmission blocks in the plurality of transmission blocks; determining the second number of iterations of decoding based on the second clock frequency, the second duty cycle, the second processing time, the third processing time, the number of common transmission blocks and the second number of coding blocks; and determining the target correspondence based on the second number of iterations and the second number of coding blocks.

[0100] In some embodiments, the transmission block is decoded in units of a first sliding window, and determining the first number of decoding iterations based on the first clock frequency, the first duty cycle, the first processing time, and the second number of coding blocks further includes: obtaining a first value based on the product of the first clock frequency and the first duty cycle; determining the first number of decoding processing times for each of the first sliding windows; obtaining a second value based on the product of the first processing time, the first number of processing times, and the first number of coding blocks; determining the first number of iterations based on the ratio of the first number to the second number, the first number of iterations being less than or equal to the ratio of the first number to the second number.

[0101] In some embodiments, the transmission block is decoded in units of a second sliding window, and determining the second number of decoding iterations according to the second clock frequency, the second duty cycle, the second processing time, the third processing time, the number of common transmission blocks and the third number of coding blocks further includes: obtaining a third value according to the product of the second clock frequency and the second duty cycle; determining the second processing number of decoding each second sliding window; obtaining a fourth value according to the second processing time, the second processing number and the product of the number of common transmission blocks and the second number of coding blocks; obtaining a fifth value according to the product of the third processing time, the number of common transmission blocks and the second number of coding blocks; obtaining a sixth value according to the sum of the fourth value and the fifth value; determining the second number of iterations according to the ratio of the third value to the sixth value, the second number of iterations being less than or equal to the ratio of the third value to the sixth value.

[0102] In step 306, during decoding of the transport block, in response to a current number of decoding iterations being greater than or equal to the number of iterations, a decoding result of the transport block is output.

[0103] In some embodiments, in the process of decoding the transmission block, in response to the current number of decoding iterations being greater than or equal to the number of iterations, outputting the decoding result of the transmission block further includes: in the process of decoding each of the coding blocks included in the transmission block, in response to the current number of decoding iterations being greater than or equal to the number of iterations, outputting the decoding result.

[0104] By using the method of the embodiment of the present application, the decoding performance can be improved: under the premise of fully utilizing the maximum processing capacity of the hardware, by dynamically selecting the number of iterations, the most appropriate number of iterations can be selected under different channel conditions and data block sizes, thereby improving the accuracy of decoding and reducing the bit error rate; resource utilization can also be optimized: the decoder externally adaptively selects the maximum number of iterations as much as possible, and the decoder internally adopts various ET (including CRC check) schemes at the same time, avoiding excessive iterations in unnecessary situations, reducing the waste of system resources (such as computing time, energy consumption, etc.), and improving the overall efficiency of the system; adaptability can also be enhanced: it can better adapt to complex and changeable communication environments, adjust the number of iterations in real time according to actual conditions, and ensure the stability of communication quality.

[0105] It should be noted that the method of the embodiment of the present application can be performed by a single device, such as a computer or server. The method of this embodiment can also be applied to a distributed scenario and completed by multiple devices cooperating with each other. In the case of such a distributed scenario, one of the multiple devices can only perform one or more steps in the method of the embodiment of the present application, and the multiple devices will interact with each other to complete the described method.

[0106] It should be noted that the above describes some embodiments of the present application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the above embodiments and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0107] Based on the same technical concept, corresponding to any of the above-mentioned embodiment methods, the present application also provides a device for wireless communication.

[0108] refer to Figure 4 , the device for wireless communication comprises:

[0109] The first determination module 401 is configured to determine a target number of coding blocks of coding blocks included in a transport block to be decoded.

[0110] The second determination module 402 is configured to determine the number of decoding iterations according to the target number of coding blocks and the target corresponding relationship, wherein the target corresponding relationship includes the corresponding relationship between the target number of decoding iterations and the target number of coding blocks.

[0111] The second determination module 402 is further configured to, in response to transmitting one of the transmission blocks in a time slot, determine the target correspondence according to the first number of coding blocks of the coding blocks contained in one of the transmission blocks; in response to transmitting multiple of the transmission blocks in a time slot, determine the target correspondence according to the second number of coding blocks of the coding blocks contained in multiple of the transmission blocks.

[0112] The second determination module 402 is further configured to determine a first clock frequency of the decoder and a first duty cycle of the processor; determine a first processing time required to decode one of the coding blocks; determine the first number of decoding iterations based on the first clock frequency, the first duty cycle, the first processing time and the second number of coding blocks; determine the target correspondence based on the first number of iterations and the first number of coding blocks.

[0113] The second determination module 402 is also configured to determine the second clock frequency of the decoder and the second duty cycle of the processor; determine the second processing time required for decoding one of the coding blocks and the third processing time required for decoding multiple coding blocks; determine the number of common transmission blocks in the multiple transmission blocks; determine the second number of decoding iterations based on the second clock frequency, the second duty cycle, the second processing time, the third processing time, the number of common transmission blocks and the second number of coding blocks; determine the target correspondence based on the second number of iterations and the second number of coding blocks.

[0114] The second determination module 402 is further configured to obtain a first value based on the product of the first clock frequency and the first duty cycle; determine a first processing number of decoding each of the first sliding windows; obtain a second value based on the product of the first processing time, the first processing number and the first number of coding blocks; determine the first number of iterations based on the ratio of the first number to the second number, the first number of iterations being less than or equal to the ratio of the first number to the second number.

[0115] The second determination module 402 is further configured to obtain a third value based on the product of the second clock frequency and the second duty cycle; determine the second processing times for decoding each of the second sliding windows; obtain a fourth value based on the product of the second processing time, the second processing times, the number of common transmission blocks, and the second number of coding blocks; obtain a fifth value based on the product of the third processing time, the number of common transmission blocks, and the second number of coding blocks; obtain a sixth value based on the sum of the fourth value and the fifth value; determine the second number of iterations based on the ratio of the third value to the sixth value, the second number of iterations being less than or equal to the ratio of the third value to the sixth value.

[0116] The output module 403 is configured to output a decoding result of the transport block in response to a current number of decoding iterations being greater than or equal to the number of iterations during decoding of the transport block.

[0117] The output module 403 is further configured to output the decoding result in response to the current number of decoding iterations being greater than or equal to the number of iterations during the decoding of each of the coding blocks included in the transmission block.

[0118] For the convenience of description, the above device is described in terms of functions divided into various modules. Of course, when implementing the present application, the functions of each module can be implemented in the same or multiple software and / or hardware.

[0119] The device of the above embodiment is used to implement the corresponding method 300 in any of the above embodiments, and has the beneficial effects of the corresponding method embodiment, which will not be described in detail here.

[0120] The embodiment of the present application further provides a chip, which includes a programmable logic circuit and / or program instructions, and is used to implement method 300 when the chip is running.

[0121] A person skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present application (including the claims) is limited to these examples. In line with the concept of the present application, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of the different aspects of the embodiments of the present application as described above, which are not provided in detail for the sake of simplicity.

[0122] In addition, to simplify the description and discussion, and in order not to make the embodiments of the present application difficult to understand, the well-known power / ground connections to the integrated circuit (IC) chip and other components may or may not be shown in the provided drawings. In addition, the device may be shown in the form of a block diagram to avoid making the embodiments of the present application difficult to understand, and this also takes into account the fact that the details of the implementation of these block diagram devices are highly dependent on the platform on which the embodiments of the present application are to be implemented (that is, these details should be fully within the scope of understanding of those skilled in the art). Where specific details (e.g., circuits) are set forth to describe exemplary embodiments of the present application, it is obvious to those skilled in the art that the embodiments of the present application can be implemented without these specific details or with changes in these specific details. Therefore, these descriptions should be considered illustrative rather than restrictive.

[0123] Although the present application has been described in conjunction with specific embodiments of the present application, many alternatives, modifications and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may use the discussed embodiments.

[0124] The embodiments of the present application are intended to cover all such substitutions, modifications and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present application should be included in the scope of protection of the present application.

Claims

1. A method for wireless communication, comprising: Determining a target number of coded blocks contained in a transport block to be decoded; The target number of coding blocks includes the first number of coding blocks; Determining the number of decoding iterations according to the target number of coding blocks and the target corresponding relationship, wherein the target corresponding relationship includes a corresponding relationship between the target number of decoding iterations and the target number of coding blocks; In a process of decoding the transport block, in response to a current number of iterations of decoding being greater than or equal to the number of iterations, outputting a decoding result of the transport block; The method further includes: in response to transmitting one of the transport blocks in one time slot, determining the target correspondence according to the first number of the coding blocks of the coding blocks included in one of the transport blocks: determining a first clock frequency of the decoder and a first duty cycle of the processor; Determining a first processing time required to decode one of the coded blocks; Determining a first number of decoding iterations according to the first clock frequency, the first duty cycle, the first processing time, and the first number of coding blocks; Determining the target corresponding relationship according to the first number of iterations and the first number of coding blocks; decoding the transmission block in units of a first sliding window; Determining the first number of decoding iterations based on the first clock frequency, the first duty cycle, the first processing time, and the first number of coding blocks further includes: obtaining a first value based on the product of the first clock frequency and the first duty cycle; determining the first number of decoding processing times for each of the first sliding windows; obtaining a second value based on the product of the first processing time, the first number of processing times, and the first number of coding blocks; determining the first number of iterations based on the ratio of the first number to the second number, the first number of iterations being less than or equal to the ratio of the first number to the second number.

2. The method of claim 1, wherein: The target number of coding blocks also includes a second number of coding blocks, and the method further includes: In response to transmitting a plurality of the transport blocks in a time slot, the target corresponding relationship is determined according to the number of the second coding blocks of the coding blocks included in the plurality of the transport blocks.

3. The method of claim 2, wherein: The target number of iterations includes a second number of iterations, and in response to transmitting a plurality of the transport blocks in a time slot, determining the target corresponding relationship according to the second number of coding blocks of the coding blocks included in the plurality of the transport blocks further includes: determining a second clock frequency of the decoder and a second duty cycle of the processor; Determining a second processing time required to decode one of the coding blocks and a third processing time required to decode a plurality of the coding blocks; Determining the number of common transport blocks in the plurality of transport blocks; the transport blocks are decoded in units of a second sliding window; Determine the second number of decoding iterations according to the second clock frequency, the second duty cycle, the second processing time, the third processing time, the number of common transmission blocks, and the second number of coding blocks: obtain a third value according to the product of the second clock frequency and the second duty cycle; determine the second number of decoding processing for each second sliding window; obtain a fourth value according to the second processing time, the second number of processing times, the product of the number of common transmission blocks and the second number of coding blocks; obtain a fifth value according to the product of the third processing time, the number of common transmission blocks, and the second number of coding blocks; obtain a sixth value according to the sum of the fourth value and the fifth value; determine the second number of iterations according to the ratio of the third value to the sixth value, the second number of iterations being less than or equal to the ratio of the third value to the sixth value; The target corresponding relationship is determined according to the second number of iterations and the second number of coding blocks.

4. The method of claim 1, wherein: In the process of decoding the transport block, in response to the current number of decoding iterations being greater than or equal to the number of iterations, outputting the decoding result of the transport block further comprises: In a process of decoding each of the coding blocks included in the transmission block, in response to the current number of decoding iterations being greater than or equal to the number of iterations, the decoding result is output.

5. An apparatus for wireless communication, comprising: A first determination module is configured to determine a target number of coding blocks of coding blocks included in a transport block to be decoded; The target number of coding blocks includes the first number of coding blocks; A second determination module is configured to determine the number of decoding iterations according to the target number of coding blocks and a target corresponding relationship, wherein the target corresponding relationship includes a corresponding relationship between the target number of decoding iterations and the target number of coding blocks; an output module, configured to output a decoding result of the transport block in response to a current number of decoding iterations being greater than or equal to the number of iterations during decoding of the transport block; The apparatus further includes: a response module configured to, in response to transmitting one of the transmission blocks in one time slot, determine the target correspondence relationship according to the first number of the coding blocks of the coding blocks included in one of the transmission blocks: A first determining unit is configured to determine a first clock frequency of the decoder and a first duty cycle of the processor; A second determining unit is configured to determine a first processing time required for decoding one of the coding blocks; a third determining unit, configured to determine a first number of decoding iterations according to the first clock frequency, the first duty cycle, the first processing time, and the first number of coding blocks; A fourth determining unit is configured to determine the target corresponding relationship according to the first number of iterations and the first number of coding blocks; the transport block is decoded in units of a first sliding window; The third determination unit is further configured to: obtain a first value based on the product of the first clock frequency and the first duty cycle; determine a first processing number of decoding each of the first sliding windows; obtain a second value based on the product of the first processing time, the first processing number and the first number of coding blocks; determine the first number of iterations based on the ratio of the first number to the second number, the first number of iterations being less than or equal to the ratio of the first number to the second number.

6. A chip, comprising a programmable logic circuit and / or program instructions, which is used to implement the method according to any one of claims 1 to 4 when the chip is running.

7. A terminal comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the program, the method according to any one of claims 1 to 4 is implemented.

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