A method for manufacturing a circuit board with double-sided gold-plated pad area difference

Abstract

The application discloses a circuit board manufacturing method with double-sided gold-plated pad area difference, which comprises the following steps: arranging a plurality of unit boards according to a mutual alternation arrangement mode of front surfaces and back surfaces to form a spliced board data; an edge area of the spliced board data is a process edge; a large pad pattern and a small pad pattern are manufactured on a copper layer of the circuit board according to the spliced board data, including etching a plate edge, forming a non-copper frame, etching a part of the process edge, forming an etching window pattern, and then performing electroplating and post-process processing to form a required circuit board; the arrangement mode of the unit boards is ingeniously adjusted to form a mode of first manufacturing the spliced board data and then uniformly electroplating, so that all the pad patterns are simultaneously electroplated on the plurality of unit boards, the production efficiency is greatly improved, the high consistency of products between different batches is ensured, and the comprehensive problems of uneven current density distribution, long process, complex process and high cost in traditional electroplating are effectively solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of circuit board manufacturing, in particular to a circuit board manufacturing method with double-sided gold-plated pad area difference. BACKGROUND

[0002] For some circuit boards with plug-in contact or press contact, gold plating treatment needs to be performed on the pad pattern of the circuit board to improve the wear resistance and reliability of the pad.

[0003] However, when the two pad patterns of the circuit board have a large area difference (2:1 to 8:1), the electric field lines of the two sides are not uniform, the electric field lines of the large area pad to be plated are relatively sparse, and other problems exist, so that the plating process of the small area pad to be plated is more "intense", the formed gold plating is thicker, and the appearance visually shows a whitening phenomenon, the plating process of the large area pad to be plated is more "weak", the formed gold plating is thinner, resulting in a large difference in the thickness of the gold plating of the two pad patterns, and affecting the reliability of the circuit board application.

[0004] The existing manufacturing method is a surface processing method: first, the first surface is protected by pasting an anti-gold dry film, the second surface is gold-plated, and then the same operation is performed on the other surface.

[0005] However, the process of this manufacturing method is long, the process is complex, and the cost is high, resulting in more waste and waste liquid.

[0006] Therefore, in order to solve the above-mentioned problems, a circuit board manufacturing method with double-sided gold-plated pad area difference is needed. SUMMARY

[0007] The present application aims to solve the comprehensive problems of the prior art, such as long process, complex process, and high cost, for gold plating of pad patterns with large area difference on both sides, and proposes a circuit board manufacturing method with double-sided gold-plated pad area difference. The circuit board is processed using a spliced board structure formed by splicing a plurality of unit boards, the front surface of the unit board is designed with a large pad pattern, the back surface is designed with a small pad pattern, the area ratio of the large pad pattern to the small pad pattern is 2:1 to 8:1, and the manufacturing method comprises the following steps:

[0008] S10: Splice a plurality of unit boards according to the arrangement mode that the front surface and the back surface are alternated with each other to form a spliced board data;

[0009] The edge area of the spliced board data is a process edge, the area where the unit boards are distributed is a pattern area, and the pattern area is surrounded by the process edge;

[0010] S20: processing the circuit board according to the panelization data to form a copper layer circuit board, wherein the copper layer circuit board is entirely covered with a copper layer, and making a circuit pattern on the copper layer to form an outer layer circuit board;

[0011] The circuit pattern includes the large pad pattern and the small pad pattern;

[0012] The circuit pattern making includes etching the board edge to form a copper-free frame, and etching off part of the process edge to form an etched window pattern;

[0013] S30: performing electro-gold plating on the outer layer circuit board, and then performing post-processing to form the circuit board with the double-sided gold-plated pad area difference.

[0014] Furthermore, the panelized material is formed by arranging several of the unit panels according to the front side to form a first unit module, arranging several of the unit panels according to the back side to form a second unit module, and panelizing the first unit modules and the second unit modules in an alternating arrangement to form the panelized material.

[0015] Furthermore, the circuit pattern includes the large pad pattern lead and the small pad pattern lead; the width of the small pad pattern lead is smaller than that of the large pad pattern lead.

[0016] Furthermore, the width of the small pad pattern lead is 1 / 2 to 1 / 3 of the width of the large pad pattern lead.

[0017] Furthermore, the width of the small pad pattern lead is 25 μm to 75 μm, preferably 50 μm.

[0018] Furthermore, the width of the copper-free frame is 1 mm to 5 mm.

[0019] Furthermore, the etched window pattern is located on the non-clamping edge of the electroplating gold processing.

[0020] Furthermore, the width of the etched window pattern is 5 mm to 20 mm.

[0021] Furthermore, the circuit board is a multi-layer circuit board, the stacking structure of the multi-layer circuit board is a symmetrical structure, and the hole pattern structure is a symmetrical structure.

[0022] Furthermore, forming the outer layer circuit board includes making an inner layer circuit pattern of the multi-layer circuit board, including etching a board edge and etching off a portion of the process edge.

[0023] The technical scheme of the present application forms the mode of first making the panel data and then uniformly electroplating by adjusting the arrangement mode of the unit panel, so that the large pad pattern and the small pad pattern are alternately and uniformly distributed on the same surface, the simultaneous electroplating of multiple unit panels is completed under relatively similar conditions, the production efficiency is greatly improved, the high consistency of products between different batches is ensured, and the problem of uneven current density distribution in the traditional electroplating process is effectively solved; by the etching process, the copper-free frame and the etched window pattern are formed, the copper on the first surface of the unit panel and the copper on the second surface are not connected to each other, the surrounding copper pattern is not formed on the edge of the panel, the electroplating of the large pad pattern and the small pad pattern is shielded, the problems of unstable current and uneven electroplating caused by the connection of the circuits on the two surfaces are effectively avoided; the overall process is formed in cooperation with the front and rear to realize the manufacturing of the double-sided gold-plated pad area difference circuit board with high quality and consistency, and the problems of long process, complex process and high cost in the manufacturing method of the prior art are improved, and a large amount of waste materials and waste liquid are generated. BRIEF DESCRIPTION OF DRAWINGS

[0024] In order to more clearly illustrate the technical scheme in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor on the basis of the drawings shown.

[0025] Figure 1 It is a process flow diagram of the embodiment of the present application.

[0026] Figure 2 It is a front view schematic diagram of the panel data of the embodiment of the present application.

[0027] Figure 3 It is a back view schematic diagram of the panel data of the embodiment of the present application.

[0028] Figure 4 It is a partial enlarged plan view schematic diagram of Figure 3 .

[0029] Figure 5 It is a plan view schematic diagram of the panel data of another embodiment.

[0030] Figure 6 It is a plan view schematic diagram of the large pad pattern of an embodiment.

[0031] Figure 7 It is a plan view schematic diagram of the small pad pattern of an embodiment.

[0032] Explanation of reference numerals:

[0033]

[0034] The objectives, functional features and advantages of the present application will be further described with reference to the embodiments in conjunction with the accompanying drawings. DETAILED DESCRIPTION

[0035] The technical solutions in the embodiments of the present application will be apparently and completely described with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without any creative work fall within the protection scope of the present application.

[0036] It should be noted that all the directionality indications (such as up, down, left, right, front, back, inside, outside, etc.) in the embodiments of the present application are only used to explain the relative position relationship, movement condition, etc. between the components in a certain specific posture (as shown in the drawings). If the specific posture changes, the directionality indications also change accordingly.

[0037] In addition, the descriptions such as “first”, “second” and the like in the present application are only for the purpose of description, and cannot be understood as indicating or implying the relative importance of the indicated technical features or implicitly indicating the number of the indicated technical features. Therefore, the features limited by “first”, “second” can explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of “plurality” is at least two, such as two, three, etc., unless otherwise specifically limited.

[0038] In addition, the technical solutions of each embodiment of the present application can be combined with each other, but it must be based on the fact that a person skilled in the art can realize it. When the combination of technical solutions appears contradictory or unachievable, it should be considered that the combination of technical solutions does not exist and is not within the protection scope of the present application.

[0039] Please refer to Figure 1 , Figure 1 for the process flowchart of the embodiment of the present application.

[0040] The circuit board of the embodiment of the present application is processed by using the spliced board structure formed by splicing unit boards in the processing process. The front surface of the unit board is designed with a large pad pattern 1010, and the back surface is designed with a small pad pattern 1020. The area ratio of the large pad pattern 1010 to the small pad pattern 1020 is 2:1 to 8:1.

[0041] The manufacturing method includes using each step process in Figure 1 The following will make further step-by-step description of each step process in Figure 1 .

[0042] Please refer toFigure 2 、 Figure 3 、 Figure 4 , Figure 2 is a schematic diagram of the front side of the panel material of an embodiment of the present application; Figure 3 is a schematic diagram of the back side of the panel material of an embodiment of the present application; Figure 4 is a partial enlarged plan view of Figure 3 .

[0043] S10: a plurality of unit panels are arranged in an alternating manner of front side and back side to form a panel material 10; the edge area of the panel material 10 is a process edge, and the area where the unit panels are distributed is a pattern area, which is surrounded by the process edge.

[0044] By arranging the unit panels in an alternating manner of front side and back side to form a large panel material 10, in the entire panel, the large pad patterns 1010 and the small pad patterns 1020 are staggered, which helps to make the electric field lines more evenly distributed between the various pads, thereby reducing the problem of uneven current density caused by area difference. That is, by this arrangement, each large pad pattern 1010 and small pad pattern 1020 is in a relatively balanced electric field environment, regardless of its size, a relatively consistent current density can be obtained, and thus a more uniform plating thickness is achieved.

[0045] Please refer to Figure 5 , Figure 5 is a plan view of the panel material of another embodiment.

[0046] In another embodiment, the panel material 10 is formed by arranging a plurality of unit panels in a front side arrangement to form a first unit module, arranging a plurality of unit panels in a back side arrangement to form a second unit module, and arranging the first unit module and the second unit in an alternating manner to form the panel material 10.

[0047] By using the above method of first making the panel material 10 and then uniformly electroplating, the large pad patterns 1010 and the small pad patterns 1020 of the plurality of unit panels are alternately and uniformly distributed on the same side, and are formed to receive electroplating under relatively the same conditions, so that simultaneous electroplating of the plurality of unit panels can be completed in one operation, greatly improving the production efficiency, and at the same time, ensuring the high consistency of products between different batches, which is conducive to large-scale production and ensures the quality of electroplating.

[0048] Please refer to Figure 6 and Figure 7 , Figure 6 is a plan view of the large pad pattern of an embodiment; Figure 7 is a plan view of the small pad pattern of an embodiment.

[0049] S20: processing the circuit board according to the panel data 10 to form a copper layer circuit board, the copper layer circuit board is covered by copper layer as a whole, and a circuit pattern 100 is made on the copper layer to form an outer layer circuit board, the circuit pattern 100 includes a large pad pattern 1010 and a small pad pattern 1020, the making of the circuit pattern 100 includes etching the board edge to form a copper-free frame 1030, and etching the partial process edge to form an etching window pattern 1040.

[0050] Further, the circuit pattern 100 includes a large pad pattern lead 1010A and a small pad pattern lead 1020A, and the width of the small pad pattern lead 1020A is smaller than that of the large pad pattern lead 1010A. By designing the small pad pattern lead 1020A to be narrower than the large pad pattern lead 1010A, that is, when the lead length is the same and the width is reduced, the resistance will increase, which will naturally tend to choose the large pad path with smaller resistance, that is, the large pad pattern lead 1010A, which can balance the current distribution between the two to some extent, so that the electroplating surface of the entire circuit board is more uniform and smooth.

[0051] Optionally, the width of the small pad pattern lead 1020A is 1 / 2 to 1 / 3 of the width of the large pad pattern lead 1010A.

[0052] Optionally, the width of the small pad pattern lead 1020A is 1 / 2 to 1 / 3 of the width of the large pad pattern lead 1010A.

[0053] Generally, the pads at the edge position are more susceptible to changes in the electric field than the pads at the center position, which can cause the plating layer in the edge area to be too thick or too thin.

[0054] To solve this problem and ensure that the current can flow more effectively to the large pad pattern 1010 and the small pad pattern 1020 to be electroplated, the process edge in the present embodiment forms a copper-free frame 1030 and an etching window pattern 1040 by etching, that is, the copper on the first surface and the copper on the second surface of the unit board are not connected to each other, effectively avoiding the problem of unstable current caused by the connection of the two surfaces and the problem of uneven electroplating; and the copper-free frame 1030 prevents the formation of a closed copper pattern on the edge of the board, preventing the edge of the board from absorbing too much electric field line and shielding the electroplating of the large pad pattern 1010 and the small pad pattern 1020, so that the current of the electroplating chuck is connected to the large pad pattern 1010 and the small pad pattern 1020 to be plated only through the conductive lead, effectively reducing the influence of the edge effect on the large pad pattern 1010 and the small pad pattern 1020.

[0055] Further, in order to avoid the plating clamp from clamping the conductive area and failing to form the plating effect, the width of the copper-free frame 1030 is limited to the range of 1mm to 5mm.

[0056] Further, the etching window pattern 1040 is located on the non-clamping side of the electroplating gold processing, preventing the vertical side from forming more adsorption of the electric field lines, effectively avoiding the current shunt phenomenon caused by the clamp contact, so that the current can flow more concentratedly through the to-be-plated area, thereby improving the consistency and quality of the plating layer.

[0057] Optionally, the width of the etching window pattern 1040 is 5mm to 20mm. By reasonably setting the width of the etching window pattern 1040, the problem of uneven plating layer thickness caused by the area difference between the large pad pattern 1010 and the small pad pattern 1020 can be largely eliminated, ensuring a high-quality flat plating layer.

[0058] Optionally, the circuit board is a multi-layer circuit board, and the stack structure of the multi-layer circuit board is a symmetrical structure. That is, the copper layers and other materials in the internal layers of the circuit board are arranged symmetrically up and down according to a certain rule. Such a structure design can ensure that the current path length on each layer is equal or similar, so that the current density is more uniformly distributed on the entire circuit board, which is conducive to the deposition of metal ions during electroplating, thereby forming a uniform plating layer. Moreover, the hole pattern structure of the multi-layer circuit board is a symmetrical structure. Here, the "hole" refers to a via hole used to connect the conductive lines between different layers. By arranging the positions, sizes and distributions of these holes symmetrically, a relatively stable current environment can be provided during electroplating, avoiding the problem of local over-thick or over-thin plating layer caused by current congestion.

[0059] Further, the multi-layer circuit board can be designed with a through hole. To form an outer layer circuit board, when etching the inner layer circuit pattern of the multi-layer circuit board, the plate edge is etched and the part of the process edge is etched. This has the same effect as etching the process edge of the outer layer circuit pattern, preventing the existence of a through hole on the plate edge and forming an inner layer through hole, which affects the electroplating effect.

[0060] S30: electroplating gold processing is performed on the outer layer circuit board, and then a rear process is performed to form a circuit board with a double-sided gold-plated pad area difference.

[0061] The treated outer layer circuit board is placed in an electroplating solution containing gold ions, and an electric current is applied under appropriate voltage conditions to make the gold ions deposit onto the surfaces of the large pad pattern 1010 and the small pad pattern 1020 to form a plating layer.

[0062] After electroplating is completed, a series of post-processing operations such as cleaning and drying need to be performed, and finally the quality of the plating layer is detected by an instrument to determine whether it meets the requirements, and then the rear process is continued for final forming.

[0063] The above merely describes the preferred embodiments of the present application, and is not intended to limit the patent scope of the present application. Any equivalent structural changes made according to the content of the present application specification and drawings, or direct / indirect application in other related technical fields, are included in the patent protection scope of the present application.

Claims

1. A method for manufacturing a circuit board having a difference in gold-plated pad area on both sides, the circuit board being processed using a split board structure formed by splicing unit boards, a large pad pattern being designed on the front side of the unit boards, and a small pad pattern being designed on the back side of the unit boards, the area ratio of the large pad pattern to the small pad pattern being 2:1 to 8:1, characterized in that, The manufacturing method comprises the following steps: S10: a plurality of unit boards are arranged according to the arrangement mode of the front surface and the back surface alternately, to form a plate arrangement; in the plate arrangement, the large pad pattern and the small pad pattern are distributed alternately; The edge area of the plate arrangement is a process edge, and the area where the unit boards are distributed is a pattern area, which is surrounded by the process edge; S20: the circuit board is processed according to the plate arrangement, to form a copper layer circuit board, which is covered by a copper layer as a whole, and a circuit pattern is made on the copper layer, to form an outer layer circuit board; The circuit pattern comprises the large pad pattern and the small pad pattern; The manufacturing of the circuit pattern comprises etching the plate edge, forming a non-copper frame, and etching part of the process edge to form an etching window pattern; The circuit pattern comprises a large pad pattern lead and a small pad pattern lead; the width of the small pad pattern lead is smaller than that of the large pad pattern lead; S30: the outer layer circuit board is processed by electroplating gold, and then processed by a subsequent process, to form the circuit board with the double-sided gold-plated pad area difference.

2. The method of claim 1, wherein the circuit board is formed by a subtractive process. The plate arrangement is formed by arranging a plurality of unit boards according to the front surface to form a first unit module, arranging a plurality of unit boards according to the back surface to form a second unit module, and arranging the first unit module and the second unit module alternately to form the plate arrangement.

3. The method of claim 1, wherein the method further comprises: forming a solder mask on the first and second surfaces of the circuit board; and removing the solder mask from the first surface of the circuit board to expose the first surface of the circuit board. The width of the small pad pattern lead is 1 / 2 to 1 / 3 of the width of the large pad pattern lead.

4. The method of claim 1 or 2, wherein the circuit board is formed by a subtractive process. The width of the small pad pattern lead is 25 μm to 75 μm.

5. The method of claim 1, wherein the circuit board is formed by a subtractive process. The width of the non-copper frame is 1 mm to 5 mm.

6. The method for manufacturing a circuit board with double-sided gold-plated pad area difference according to claim 1, wherein: The etching window pattern is located on the non-clamping edge of the electroplating gold process.

7. A method for manufacturing a circuit board with double-sided gold-plated pad area difference according to claim 1 or 6, characterized in that: The width of the etching window pattern is 5 mm to 20 mm.

8. The method for manufacturing a circuit board with double-sided gold-plated pad area difference according to claim 1, wherein: The circuit board is a multi-layer circuit board, the stack structure of the multi-layer circuit board is a symmetrical structure, and the hole pattern structure is a symmetrical structure.

9. The method of claim 8, wherein the circuit board is formed by a subtractive process. The outer layer circuit board is formed by manufacturing the inner layer circuit pattern of the multi-layer circuit board, which comprises etching the plate edge and etching part of the process edge.

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