A semiconductor device and a method for manufacturing the same

Abstract

The present application discloses a semiconductor device and a manufacturing method thereof, relating to the field of semiconductor technology. The semiconductor device includes: a semiconductor layer; a first gate structure, a second gate structure, and a third gate structure, located on the semiconductor layer; a doped region, located in the semiconductor layer; a first dielectric layer and a second dielectric layer, the first dielectric layer is at least located on the sidewalls of the first gate structure, and the second dielectric layer is at least located on the third gate structure; and a sidewall contact layer and an electrode layer, the sidewall contact layer is located on the first dielectric layer, and the electrode layer is located on the second dielectric layer; wherein, the electrode layer, the second dielectric layer, and the third gate structure form a capacitor structure, and the electrode layer is led out through the third gate structure as a control electrode; the first dielectric layer and the second dielectric layer are formed simultaneously, and the sidewall contact layer and the electrode layer are formed simultaneously.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and particularly to a semiconductor device and a manufacturing method thereof. Background Art

[0002] An OTP (One Time Programmable) device is a storage device, which is relative to multiple programming (MTP). Its programming process is an irreversible activity, and it is suitable for application scenarios where the program remains unchanged. It has been widely used because of its low cost.

[0003] The existing OTP devices have the problem that the initial current is too high to be removed. The too high initial current of the OTP device will cause the problem that the non-coding bytes (bits) adjacent to the coding bytes (bits) are passively coded during the programming of the OTP device, which will further lead to coding chaos and incorrect stored information.

[0004] Currently, the method to solve the problem of too high initial current in OTP devices includes ultraviolet (UV) erasure, but its effect of erasing the initial current is not obvious. Summary of the Invention

[0005] In view of the above problems, the purpose of the present application is to provide a semiconductor device and a manufacturing method thereof, in which an electrode layer is formed on the third gate structure, and the electrode layer is led out through the control electrode of the third gate structure to realize limited erasure and writing of the OTP structure.

[0006] According to an aspect of the present invention, there is provided a semiconductor device, including: a semiconductor layer; a first gate structure, a second gate structure, and a third gate structure located on the semiconductor layer; a doped region located in the semiconductor layer; a first dielectric layer and a second dielectric layer, the first dielectric layer is at least located on the sidewalls of the first gate structure, and the second dielectric layer is at least located on the third gate structure; and a sidewall contact layer and an electrode layer, the sidewall contact layer is located on the first dielectric layer, and the electrode layer is located on the second dielectric layer; wherein, the electrode layer, the second dielectric layer, and the third gate structure form a capacitive structure, and the electrode layer is led out through the control electrode of the third gate structure; the first dielectric layer and the second dielectric layer are formed simultaneously, and the sidewall contact layer and the electrode layer are formed simultaneously.

[0007] Optionally, the semiconductor layer, the second gate structure, and the doped regions on both sides of the second gate structure form a select transistor of the OTP structure; the semiconductor layer, the third gate structure, and the doped regions on both sides of the third gate structure form a floating-gate transistor of the OTP structure, and the source region of the floating-gate transistor is connected to the drain region of the select transistor; before programming the OTP structure, a positive voltage is applied to the control electrode of the third gate structure to clear the initial charges in the floating gate.

[0008] Optionally, the semiconductor layer, the second gate structure, and the doped regions on both sides of the second gate structure form a select transistor of the OTP structure; the semiconductor layer, the third gate structure, and the doped regions on both sides of the third gate structure form a floating-gate transistor of the OTP structure, and the source region of the floating-gate transistor is connected to the drain region of the select transistor; after programming the OTP structure, a negative voltage is applied to the control electrode of the third gate structure to retain the electrons in the floating gate.

[0009] Optionally, the semiconductor layer, the second gate structure, and the doped regions on both sides of the second gate structure form a select transistor of the OTP structure; the semiconductor layer, the third gate structure, and the doped regions on both sides of the third gate structure form a floating-gate transistor of the OTP structure, and the source region of the floating-gate transistor is connected to the drain region of the select transistor; a positive voltage is applied to the control electrode of the third gate structure to clear the electrons in the floating gate.

[0010] Optionally, the second dielectric layer covers the third gate structure and the semiconductor layer between the third gate structure and the second gate structure, and extends to at least a portion of the second gate structure; the control electrode of the third gate structure is in contact with the electrode layer between the third gate structure and the second gate structure.

[0011] Optionally, the first dielectric layer includes a stack of a silicon oxynitride layer and a silicon oxide layer; the second dielectric layer includes a stack of a silicon oxynitride layer and a silicon oxide layer.

[0012] According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, including: forming a first gate structure, a second gate structure, and a third gate structure on a semiconductor layer; forming doped regions in the semiconductor layer; forming a first dielectric layer at least on the sidewalls of the first gate structure, and forming a second dielectric layer at least on the third gate structure, the first dielectric layer and the second dielectric layer being formed simultaneously; forming a sidewall contact layer on the first dielectric layer, and forming an electrode layer on the second dielectric layer, the sidewall contact layer and the electrode layer being formed simultaneously; wherein, the electrode layer, the second dielectric layer, and the third gate structure form a capacitor structure, and the electrode layer is led out via the control electrode of the third gate structure.

[0013] Optionally, the steps of forming the first dielectric layer, the second dielectric layer, the sidewall contact layer, and the electrode layer include: forming a dielectric layer on the semiconductor layer and on the first gate structure, the second gate structure, and the third gate structure, the dielectric layer conformally covering the semiconductor layer and the first gate structure, the second gate structure, and the third gate structure; forming a polysilicon layer on the dielectric layer; forming a patterned mask layer on the polysilicon layer; etching the polysilicon layer and the dielectric layer via the patterned mask layer to form a first dielectric layer, a polysilicon layer on the first dielectric layer, a second dielectric layer, and a polysilicon layer on the second dielectric layer, wherein the first dielectric layer covers at least the sidewall of the first gate structure, and the second dielectric layer covers at least the third gate structure; alloying the polysilicon layer on the first dielectric layer and the polysilicon layer on the second dielectric layer to form a sidewall contact layer on the first dielectric layer and an electrode layer on the second dielectric layer.

[0014] Optionally, the second dielectric layer covers the third gate structure and the semiconductor layer between the third gate structure and the second gate structure, and extends to at least a portion of the second gate structure; the third gate structure control electrode is in contact with the electrode layer between the third gate structure and the second gate structure.

[0015] Optionally, the first dielectric layer includes a stack of a silicon oxynitride layer and a silicon oxide layer; the second dielectric layer includes a stack of a silicon oxynitride layer and a silicon oxide layer.

[0016] The unexpected technical effect of this application is:

[0017] According to the semiconductor device and its manufacturing method of the embodiment of the present invention, the electrode layer on the second dielectric layer and the third gate structure (floating gate) form upper and lower electrode plates, the electrode layer on the second dielectric layer, the second dielectric layer, and the third gate structure (floating gate) form a capacitive structure, and the upper electrode plate (electrode layer) of the capacitive structure is led out via the third gate structure control electrode.

[0018] Before OTP structure encoding, a positive voltage is applied to the third gate structure control electrode. At this time, a downward electric field is formed in the capacitive structure formed by the electrode layer, the second dielectric layer, and the third gate structure (floating gate), and the electrons in the third gate structure (floating gate) move upward, and the electrons break through the barrier of the third gate structure (floating gate) / second dielectric layer (especially SiON) and are lost in large quantities, achieving the effect of clearing the charges in the third gate structure (floating gate).

[0019] After the OTP structure encoding is completed, due to the high-k property of the second dielectric layer (especially the SiON dielectric layer), it is difficult for electrons in the third gate structure (floating gate) to break through the second dielectric layer, especially the potential barrier of the dielectric layer (SiON). Further, after the OTP structure encoding is completed, a negative voltage can be applied to the control electrode of the third gate structure. An upward electric field is formed in the capacitor structure formed by the electrode layer on the second dielectric layer, the second dielectric layer, and the third gate structure (floating gate), suppressing the loss of electrons in the third gate structure (floating gate) and further enhancing the reliability of the data retention ability of the OTP structure.

[0020] In this embodiment, since an electrode layer is provided above the third gate structure (floating gate) and a control electrode of the third gate structure connected to the electrode layer above the third gate structure (floating gate) is provided, the OTP structure can achieve limited erasure and writing, and further greatly improves the error tolerance rate of the OTP structure. Specifically, when the OTP structure encoding is incorrect, a positive voltage is applied to the control electrode of the third gate structure. At this time, a downward electric field is formed in the capacitor structure formed by the electrode layer, the second dielectric layer, and the third gate structure (floating gate). The electrons introduced by programming in the third gate structure (floating gate) move upward, and the electrons break through the potential barrier of the third gate structure (floating gate) / second dielectric layer (especially the SiON dielectric layer) and flow out, realizing the function of electron erasure, and further enabling the OTP structure to achieve limited repeated programming.

[0021] Further, the electrode layer covers the top and sidewalls of the third gate structure (floating gate), that is, the electrode layer completely covers the third gate structure (floating gate), enabling the control electrode of the third gate structure to erase the charge in the third gate structure (floating gate) and retain the stored charge by applying a relatively small voltage.

[0022] Further, the electrode layer on the top of the third gate structure (floating gate) extends above the semiconductor layer between the second gate structure (select gate) and the third gate structure (floating gate), and above the second gate structure (select gate). The control electrode of the third gate structure can be provided between the second gate structure (select gate) and the third gate structure (floating gate). On the one hand, the setting of the control electrode of the third gate structure will not affect the extraction of other electrodes (such as the select gate electrode, the second source electrode, and the second drain electrode), and the overall area and overall structure of the electrode structure of the OTP structure will not be affected. On the other hand, the control electrode of the third gate structure is provided between the second gate structure (select gate) and the third gate structure (floating gate), enabling the bottom of the control electrode of the third gate structure to be connected to the planar electrode layer, which is more conducive to the etching of the control electrode of the third gate structure.

[0023] Further, the second dielectric layer is located on the third gate structure (floating gate) and extends to the semiconductor layer between the second gate structure (select gate) and the third gate structure (floating gate), preventing the formation of silicide in the semiconductor layer between the second gate structure (select gate) and the third gate structure (floating gate), which may affect the conduction of the channel between the second gate structure (select gate) and the third gate structure (floating gate), and effectively avoiding the formation of a path for electron leakage in the third gate structure (floating gate) caused by the formation of silicide in the semiconductor layer between the second gate structure (select gate) and the third gate structure (floating gate), further preventing the loss of the stored charge in the third gate structure (floating gate).

[0024] In this embodiment, while forming the first dielectric layer on the sidewall of the first gate structure in the LDMOS structure, the second dielectric layer on the third gate structure in the OTP structure is formed, realizing the process compatibility between the LDMOS structure and the OTP structure. Compared with forming the first dielectric layer and the second dielectric layer separately, this embodiment saves at least one photolithography step.

[0025] Further, in order to achieve the process compatibility between the LDMOS structure and the OTP structure and save photolithography steps, a parasitic polysilicon layer is introduced above the third gate structure in the OTP structure. In this embodiment, the parasitic polysilicon layer is retained and converted into an electrode layer. A capacitor is formed between this electrode layer and the floating gate, and it is led out via the control electrode of the third gate structure. By applying different voltages to the control electrode of the third gate structure, the initial charge in the floating gate can be erased, and functions such as limited erasing and writing that the traditional OTP structure does not have, stronger data storage ability, and longer storage time can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Through the following description of the embodiments of the present application with reference to the drawings, the above and other objects, features, and advantages of the present application will become clearer. In the drawings:

[0027] Figure 1a A cross-sectional schematic diagram of a traditional OTP structure is shown;

[0028] Figure 1b A circuit schematic diagram of a traditional OTP structure is shown;

[0029] Figure 2a A schematic cross-sectional view of a semiconductor device according to an embodiment of the present application is shown;

[0030] Figure 2b A schematic cross-sectional view of the LDMOS structure according to an embodiment of the present application is shown;

[0031] Figure 2c A schematic cross-sectional view of the OTP structure according to an embodiment of the present application is shown;

[0032] Figure 2dShows a schematic top view of the OTP structure according to an embodiment of the present application;

[0033] Figures 3a to 3i Shows cross-sectional views of various stages in the manufacturing process of a semiconductor device according to an embodiment of the present application, where:

[0034] Figure 3a Shows a schematic structural diagram of forming a first gate structure to a third gate structure on a semiconductor layer and forming a doped region in the semiconductor layer;

[0035] Figure 3b Shows a schematic structural diagram of forming a dielectric layer and a polysilicon layer;

[0036] Figure 3c Shows a schematic structural diagram of forming a first mask layer on the polysilicon layer and patterning the first mask layer using a lithography process;

[0037] Figure 3d Shows a schematic structural diagram of etching the polysilicon layer and the dielectric layer through the patterned first mask layer;

[0038] Figure 3e Shows a schematic structural diagram of forming a contact layer;

[0039] Figure 3f Shows a schematic structural diagram of forming an etch stop layer and an interlayer dielectric layer;

[0040] Figure 3g Shows a schematic structural diagram of forming a second mask layer on the interlayer dielectric layer and patterning the second mask layer using a lithography process;

[0041] Figure 3h Shows a schematic structural diagram of etching the interlayer dielectric layer through the patterned second mask layer;

[0042] Figure 3i Shows a schematic structural diagram of forming an electrode structure. Detailed implementation manners

[0043] The present application will be described in more detail below with reference to the accompanying drawings. In each of the drawings, the same elements are denoted by like reference numerals. For clarity, the various parts in the drawings are not drawn to scale. In addition, some well-known parts may not be shown.

[0044] The present application can be presented in various forms, and some examples will be described below.

[0045] Figure 1a Shows a schematic cross-sectional view of a conventional OTP structure, Figure 1b Shows a circuit schematic diagram of a conventional OTP structure. As Figure 1a and Figure 1bAs shown in the figure, the OTP structure includes a first semiconductor layer 110, a first doping region 120 located in the first semiconductor layer 110, and a select gate 130a and a floating gate 130b located on the first semiconductor layer 110. Among them, the first semiconductor layer 110, the select gate 130a, and the first doping regions 120 on both sides of the select gate 130a form a select transistor, and the first doping regions 120 on both sides of the select gate 130a respectively form the source region and the drain region of the select transistor. The first semiconductor layer 110, the floating gate 130b, and the first doping regions 120 on both sides of the floating gate 130b form a floating gate transistor, and the first doping regions 120 on both sides of the floating gate 130b form the source region and the drain region of the floating gate transistor.

[0046] The select gate 130a of the select transistor is connected to the word line SG via the first electrode 151, the source region of the select transistor is connected to the source line SL via the second electrode 152, the drain region of the select transistor is connected to the source region of the floating gate transistor, the floating gate 130b of the floating gate transistor covers the dielectric layer 140, and the drain region of the floating gate transistor is connected to the bit line BL via the third electrode 152.

[0047] Among them, during the manufacturing process of the OTP structure, charges are introduced into the floating gate 130b. Currently, the method of ultraviolet (UV) erasure is used to remove the charges in the floating gate 130b. Among them, the step of ultraviolet (UV) erasure is performed before the formation of the dielectric layer 140. During the subsequent deposition of the dielectric layer 140 and the process of etching the dielectric layer 140 using photolithography and etching processes, charges are introduced into the floating gate 130b to varying degrees, so the step of ultraviolet (UV) erasure needs to be performed again before the formation of the first electrode 151 to the third electrode 152. However, the dielectric layer 140 is usually a nitride layer (such as SiN), and ultraviolet light cannot penetrate the dielectric layer 140 to reach the floating gate 130b, and thus the charges in the floating gate 130b cannot be effectively cleared.

[0048] Furthermore, because the traditional OTP structure cannot be operated and changed a second time after one-time programming, its initial coding fault tolerance ability is poor. After the batch products are burned and encoded once, if there are errors, there is no chance of correction, which will lead to unnecessary product scrapping due to small software problems such as programming errors.

[0049] Furthermore, the traditional OTP structure has a certain service life. After encoding, due to the limitation of its data retention ability, data storage will be lost after a certain period of time, resulting in the inability to obtain the data information related to the OTP structure normally after a certain period of time.

[0050] Figure 2a The schematic cross-sectional view of the semiconductor device according to the embodiment of the present application is shown; Figure 2b The schematic cross-sectional view of the LDMOS structure according to the embodiment of the present application is shown; Figure 2cShows a schematic cross-sectional view of the OTP structure according to an embodiment of the present application; Figure 2d Shows a schematic top view of the OTP structure according to an embodiment of the present application. As Figures 2a to 2d shown, the semiconductor device includes an LDMOS structure and an OTP structure.

[0051] Specifically, the semiconductor device includes a second semiconductor layer 210, a second doped region 220 located in the second semiconductor layer 210, and a first gate structure 231, a second gate structure 232, and a third gate structure 233 located on the second semiconductor layer 210. The second semiconductor layer 210 can be composed of any one of a doped semiconductor substrate, a doped well region, and a doped epitaxial semiconductor layer.

[0052] The second semiconductor layer 210, the first gate structure 231, and the second doped regions 220 on both sides of the first gate structure 231 constitute the LDMOS structure, and the second doped regions 220 on both sides of the first gate structure 231 respectively constitute the source region and the drain region of the LDMOS structure.

[0053] The second semiconductor layer 210, the second gate structure 232, and the second doped regions 220 on both sides of the second gate structure 232 constitute the select transistor of the OTP structure, and the second doped regions 220 on both sides of the second gate structure 232 constitute the source region and the drain region of the select transistor. The second semiconductor layer 210, the third gate structure 233, and the second doped regions 220 on both sides of the third gate structure 233 constitute the floating gate transistor of the OTP structure, and the second doped regions 220 on both sides of the third gate structure 233 constitute the source region and the drain region of the floating gate transistor. Further, the drain region of the select transistor is connected to the source region of the floating gate transistor.

[0054] The first gate structure 231 includes a gate dielectric layer 230a, a gate conductor 230b located on the gate dielectric layer 230a, and sidewalls 230c located on both sides of the gate conductor 230b. The sidewalls 230c include an oxide layer and / or a nitride layer. The structures of the second gate structure 232 and the third gate structure 233 are the same as those of the first gate structure 231, and are not described herein again in this embodiment.

[0055] The semiconductor device includes a first dielectric layer 241 and a second dielectric layer 242. The first dielectric layer 241 is at least located on one sidewall of the first gate structure 231. In this embodiment, the first dielectric layer 241 covers one sidewall of the first gate structure 231 and extends to the top of the first gate structure 231, and the first dielectric layer 241 exposes at least a partial surface of the top of the first gate structure 231. The second dielectric layer 242 is at least located on the third gate structure 233. In this embodiment, the second dielectric layer 242 is located on the third gate structure 233, on the second semiconductor layer 210 between the third gate structure 233 and the second gate structure 232, and extends to the second gate structure 232. Specifically, the second dielectric layer 242 covers the top and sidewalls of the third gate structure 233, the surface of the second semiconductor layer 210 between the third gate structure 233 and the second gate structure 232, the sidewall of the second gate structure 232 adjacent to the third gate structure 233, and a partial surface of the top of the second gate structure 232.

[0056] The first dielectric layer 241 and the second dielectric layer 242 include one or more dielectric layers. In this embodiment, the first dielectric layer 241 and the second dielectric layer 242 include a stacked bottom dielectric layer 240a and a top dielectric layer 240b. The bottom dielectric layer 240a is, for example, a nitride layer (such as a SiON layer), and the top dielectric layer 240b is, for example, an oxide layer (such as a SiO2 layer).

[0057] The semiconductor device includes contact layers, specifically including a sidewall contact layer 250a, an electrode layer 250b, a gate contact layer 250c, and a doped region contact layer 250d. The sidewall contact layer 250a is located on the first dielectric layer 241, the electrode layer 250b is located on the second dielectric layer 242, the gate contact layer 250c is located on the tops of the first gate structure 231 and the second gate structure 232, and the doped region contact layer 250d is located on the top of the second doped region 220.

[0058] The semiconductor device includes an etch stop layer 260, an interlayer dielectric layer 270, and an electrode structure. The etch stop layer 260 conformally covers the exposed surface of the second semiconductor layer 210, the surface of the sidewall contact layer 250a on the first dielectric layer 241, the surface of the electrode layer 250b on the second dielectric layer 242, and the exposed surfaces of the first gate structure 231 and the second gate structure 232. The interlayer dielectric layer 270 is located on the etch stop layer 260 and covers the surface of the etch stop layer 260.

[0059] The electrode structure includes a first gate electrode 281, a first source electrode 282, and a first drain electrode 283. The first gate electrode 281 reaches the top of the first gate structure 231 and contacts the gate contact layer 250c on the top of the first gate structure 231. The first source electrode 282 and the first drain electrode 283 respectively reach the second doped regions 220 on both sides of the first gate structure 231 and contact the doped region contact layer 250d on the top of the second doped regions 220. In this embodiment, the electrode structure further includes a sidewall electrode 284 reaching the sidewall of the first gate structure 231, and the sidewall electrode 284 contacts the sidewall contact layer 250a on the sidewall.

[0060] The electrode structure includes a select gate electrode 285, a second source electrode 286, and a second drain electrode 287. The select gate electrode 285 reaches the top of the second gate structure (select gate) 232 and contacts the gate contact layer 250c of the second gate structure (select gate) 232. The second source electrode 286 reaches the second doped region 220 on the side of the second gate structure (select gate) 232 away from the third gate structure (floating gate) 233 and contacts the doped region contact layer 250d on the top of the second doped region 220. The second drain electrode 287 reaches the surface of the second doped region 220 on the side of the third gate structure (floating gate) 233 away from the second gate structure (select gate) 232 and contacts the doped region contact layer 250d on the top of the second doped region 220.

[0061] Furthermore, the electrode structure further includes a third gate structure control electrode 288, and the third gate structure control electrode 288 contacts the electrode layer 250b. Among them, since the electrode layer 250b is located above the top and sidewall of the third gate structure (floating gate) 233 and extends above the second semiconductor layer 210 between the second gate structure (select gate) 232 and the third gate structure (floating gate) 233, the third gate structure control electrode 288 can be disposed at any one of the top of the third gate structure (floating gate) 233, the sidewall of the third gate structure (floating gate) 233, and between the second gate structure (select gate) 232 and the third gate structure (floating gate) 233.

[0062] In this embodiment, the control electrode 288 of the third gate structure is disposed between the second gate structure (select gate) 232 and the third gate structure (floating gate) 233. When the control electrode 288 of the third gate structure is located on the top and sidewalls of the third gate structure (floating gate) 233, during the process of forming the contact hole for the control electrode 288 of the third gate structure, over-etching is likely to occur, causing the contact hole of the control electrode 288 of the third gate structure to extend into the second dielectric layer 242, and even penetrate through the second dielectric layer 242 and extend to the top or sidewall of the third gate structure (floating gate), further causing the control electrode 288 of the third gate structure to contact the third gate structure (floating gate), introducing an unnecessary leakage risk. In this embodiment, the control electrode 288 of the third gate structure is disposed between the second gate structure (select gate) 232 and the third gate structure (floating gate) to avoid short-circuiting between the control electrode 288 of the third gate structure and the third gate structure (floating gate), increasing the reliability of the device and not affecting the layout of other electrodes.

[0063] Among them, the electrode layer 250b on the second dielectric layer 242 and the third gate structure (floating gate) 233 form upper and lower electrode plates, and the electrode layer 250b on the second dielectric layer 242, the second dielectric layer 242, and the third gate structure (floating gate) 233 form a capacitive structure, and the upper electrode plate (electrode layer 250b) of the capacitive structure is led out via the control electrode 288 of the third gate structure.

[0064] Before the OTP structure is encoded, a first voltage is applied to the control electrode 288 of the third gate structure. The first voltage is, for example, a positive voltage. At this time, a downward electric field is formed in the capacitive structure formed by the electrode layer 250b, the second dielectric layer 242, and the third gate structure (floating gate) 233. The electrons in the third gate structure (floating gate) 233 move upward, and the electrons break through the barrier of the third gate structure (floating gate) / second dielectric layer 242 (especially the SiON layer) and are lost in large quantities, achieving the effect of clearing the charges in the third gate structure (floating gate).

[0065] After the OTP structure is encoded, due to the high-k property of the second dielectric layer 242 (especially the dielectric layer SiON), it is difficult for the electrons in the third gate structure (floating gate) 233 to break through the second dielectric layer 242, especially the barrier of the bottom dielectric layer 240a (SiON). Further, after the OTP structure is encoded, a second voltage can be applied to the control electrode 288 of the third gate structure. The second voltage is, for example, a negative voltage. An upward electric field is formed in the capacitive structure formed by the electrode layer 250b, the dielectric stack 240, and the third gate structure (floating gate) to inhibit the loss of electrons in the third gate structure (floating gate), further improving the reliability of the data retention ability of the OTP structure.

[0066] Due to the one-time programming characteristic of the traditional OTP structure, its error tolerance rate is extremely low. Usually, once the encoding is incorrect, secondary encoding cannot be achieved. In this embodiment, since the electrode layer 250b is provided above the third gate structure (floating gate) 233 and the third gate structure control electrode 288 connected to the electrode layer 250b above the third gate structure (floating gate) 233 is provided, the OTP structure can achieve limited erasure and writing, further greatly improving the error tolerance rate of the OTP structure. Specifically, when the OTP structure encoding is incorrect, the third voltage is applied to the third gate structure control electrode 288. The third voltage is, for example, a positive voltage. At this time, a downward electric field is formed in the capacitor structure formed by the electrode layer 250b, the second dielectric layer 242, and the third gate structure (floating gate) 233. The electrons introduced by programming in the third gate structure (floating gate) 233 move upward, and the electrons break through the barrier of the third gate structure (floating gate) 233 / the second dielectric layer 242 (especially the dielectric layer SiON) and flow out, realizing the function of electron erasure, and further enabling the OTP structure to achieve limited repeated programming.

[0067] Furthermore, the electrode layer 250b covers the top and sidewalls of the third gate structure (floating gate) 233, that is, the electrode layer 250b completely covers the third gate structure (floating gate) 233, so that a relatively small voltage applied to the third gate structure control electrode 288 can achieve the erasure of the charge in the third gate structure (floating gate) 233 and the retention of the stored charge.

[0068] Furthermore, the electrode layer 250b on the top of the third gate structure (floating gate) 233 extends above the second semiconductor layer 210 between the second gate structure (selective gate) 232 and the third gate structure (floating gate) 233, and above the second gate structure (selective gate) 232. The third gate structure control electrode 288 is arranged between the second gate structure (selective gate) 232 and the third gate structure (floating gate) 233. On the one hand, the arrangement of the third gate structure control electrode 288 does not affect the extraction of other electrodes (such as the selective gate electrode 285, the second source electrode 286, and the second drain electrode 287), and the overall area and overall structure of the electrode structure of the OTP structure will not be affected. On the other hand, the third gate structure control electrode 288 is arranged between the second gate structure (selective gate) 232 and the third gate structure (floating gate) 233, so that the bottom of the third gate structure control electrode 288 is connected to the planar electrode layer 250b, which is more conducive to the etching of the third gate structure control electrode 288.

[0069] Further, the second dielectric layer is located on the third gate structure (floating gate) 233 and extends onto the second semiconductor layer 210 between the second gate structure (select gate) 232 and the third gate structure (floating gate) 233, preventing the second semiconductor layer 210 between the second gate structure (select gate) 232 and the third gate structure (floating gate) 233 from forming silicide, which may affect the conduction of the channel between the second gate structure (select gate) 232 and the third gate structure (floating gate) 233. Also, it can effectively prevent the second semiconductor layer 210 between the second gate structure (select gate) 232 and the third gate structure (floating gate) 233 from forming silicide, which may introduce a path for electron leakage in the third gate structure (floating gate) 233, further avoiding the loss of the stored charge in the third gate structure (floating gate).

[0070] Figures 3a to 3i The cross-sectional views of various stages in the preparation process of the semiconductor device according to the embodiments of the present application are shown.

[0071] As Figure 3a shown, a first gate structure 231, a second gate structure 232, and a third gate structure 233 are formed on the second semiconductor layer 210, and a second doping region 220 is formed in the second semiconductor layer 210.

[0072] The second semiconductor layer 210 can be composed of any one of a doped semiconductor substrate, a doped well region, and a doped epitaxial semiconductor layer. The second semiconductor layer 210, the first gate structure 231, and the second doping regions 220 on both sides of the first gate structure 231 form an LDMOS structure, and the second doping regions 220 on both sides of the first gate structure 231 respectively form the source region and the drain region of the LDMOS structure.

[0073] The second semiconductor layer 210, the second gate structure 232, and the second doping regions 220 on both sides of the second gate structure 232 form a select transistor of the OTP structure, and the second doping regions 220 on both sides of the second gate structure 232 form the source region and the drain region of the select transistor. The second semiconductor layer 210, the third gate structure 233, and the second doping regions 220 on both sides of the third gate structure 233 form a floating gate transistor of the OTP structure, and the second doping regions 220 on both sides of the third gate structure 233 form the source region and the drain region of the floating gate transistor.

[0074] The first gate structure 231 includes a gate dielectric layer 230a, a gate conductor 230b located on the gate dielectric layer 230a, and sidewalls 230c located on both sides of the gate conductor 230b. The sidewalls 230c include an oxide layer and / or a nitride layer. The structures of the second gate structure 232 and the third gate structure 233 are the same as that of the first gate structure 231, and thus will not be elaborated herein.

[0075] As Figure 3bAs shown, a dielectric stack 240 and a polysilicon layer 2501 are sequentially formed on the second semiconductor layer 210, the first gate structure 231, the second gate structure 232, and the third gate structure 233. The dielectric stack 240 conformally covers the surfaces of the second semiconductor layer 210, the first gate structure 231, the second gate structure 232, and the third gate structure 233, and the polysilicon layer 2501 conformally covers the surface of the dielectric stack 240. In this embodiment, the dielectric stack 240 includes a stacked bottom dielectric layer 240a and top dielectric layer 240b. The bottom dielectric layer 240a is, for example, a nitride layer (such as a SiON layer), and the top dielectric layer 240b is, for example, an oxide layer (such as a SiO2 layer).

[0076] As Figure 3c shown, a first mask layer PR1 is formed on the polysilicon layer 2501, and the first mask layer PR1 is patterned using a lithography process.

[0077] As Figure 3d shown, the polysilicon layer 2501 and the dielectric stack 240 are etched through the patterned first mask layer PR1 to form a first dielectric layer 241, the polysilicon layer 2501 on the first dielectric layer 241, a second dielectric layer 242, and the polysilicon layer 2501 on the second dielectric layer 242.

[0078] Among them, the first dielectric layer 241 covers at least the sidewall on one side of the first gate structure 231. In this embodiment, the first dielectric layer 241 covers at least a part of the surface of the top of the first gate structure 231 and the sidewall on one side of the first gate structure 231, and at least a part of the surface of the top of the first gate structure 231 and the sidewall on the other side of the first gate structure 231 are exposed. The second dielectric layer 242 covers at least the third gate structure 233. In this embodiment, the second dielectric layer 242 covers the third gate structure 233 (including the top and sidewalls of the third gate structure 233) and the surface of the second semiconductor layer 210 between the second gate structure 232 and the third gate structure 233, and extends to at least a part of the surface of the second gate structure 232, for example, extends to the sidewall on the side of the second gate structure 232 close to the third gate structure 233, and at least a part of the surface of the top of the second gate structure 232. At least a part of the surface of the top of the second gate structure 232 and the sidewall on the side of the second gate structure 232 away from the third gate structure 233 are exposed.

[0079] Among them, Figure 3c and Figure 3dIn the steps shown, the same mask is used to etch the dielectric stack 240 and the polysilicon layer 2501, and at least a first dielectric layer 241 is formed on the sidewalls of the first gate structure 231 of the LDMOS structure, and at least a second dielectric layer 242 is formed on the third gate structure of the OTP structure. That is, the first dielectric layer 241 and the second dielectric layer 242 are formed simultaneously, and compared with separately forming the first dielectric layer 241 in the LDMOS structure and the second dielectric layer 242 in the OTP structure, one mask is omitted in this embodiment. However, it should be found that, compared with Figure 1a the embodiment shown, in this embodiment, in order to be compatible with the polysilicon layer 2501 on the first dielectric layer 241 in the LDMOS structure, a polysilicon layer 2501 is also parasitically formed on the second dielectric layer 242 in the OTP structure.

[0080] As Figure 3e shown, a contact layer is formed.

[0081] A metal layer is formed on the surface of the exposed second doped region 220, the exposed surface at the top of the first gate structure 231, the exposed surface at the top of the second gate structure 232, and the surface of the polysilicon layer 2501 above the first dielectric layer 241 and the second dielectric layer 242. The metal layer is, for example, a nickel (Ni) layer, a platinum (Pt) layer, a cobalt (Co) layer, a nickel-platinum alloy layer, a nickel-cobalt alloy layer, a platinum-cobalt alloy layer, a nickel-platinum-cobalt ternary alloy layer, etc. Then, for example, through an annealing process, the metal layer reacts with the exposed silicon surface to form a sidewall contact layer 250a on the first dielectric layer 241, an electrode layer 250b on the second dielectric layer 242, a gate contact layer 250c on the exposed surface at the top of the first gate structure 231 and the exposed surface at the top of the second gate structure 232, and a doped region contact layer 250d on the surface of the second doped region 220.

[0082] In this step, the polysilicon layer 2501 on the first dielectric layer 241 forms a sidewall contact layer 250a to facilitate the extraction of the sidewall electrode formed subsequently; at the same time, the polysilicon layer 2501 parasitically formed on the second dielectric layer 242 forms an electrode layer 250b. The electrode layer 250b and the third gate structure (floating gate) 233 form upper and lower electrode plates, and the electrode layer 250b on the second dielectric layer 242, the second dielectric layer 242, and the third gate structure (floating gate) 233 form a capacitor structure.

[0083] As Figure 3f shown, an etch stop layer 260 and an interlayer dielectric layer 270 are formed.

[0084] Among them, for example, an etch stop layer 260 and an interlayer dielectric layer 270 are formed by a deposition process. The etch stop layer 260 conformally covers the surfaces of the sidewall contact layer 250a, the electrode layer 250b, the gate contact layer 250c, the doped region contact layer 250d, and the exposed surfaces of the first gate structure 231 and the second gate structure 232. The interlayer dielectric layer 270 covers the surface of the etch stop layer 260. Then, for example, a CMP process is used to planarize the interlayer dielectric layer 270 so that the interlayer dielectric layer 270 has a flat surface. The etch stop layer 260 is, for example, a silicon nitride layer (SiN) and / or a silicon oxide layer (SiO2 layer). The interlayer dielectric layer 270 is, for example, a silicon oxide layer (SiO2 layer).

[0085] As Figure 3g shown, a second mask layer PR2 is formed on the interlayer dielectric layer 270, and the second mask layer PR2 is patterned by a photolithography process.

[0086] As Figure 3h shown, the interlayer dielectric layer 270 and the etch stop layer 260 are etched through the patterned second mask layer PR2 to form vias penetrating the interlayer dielectric layer 270 and the etch stop layer 260.

[0087] As Figure 3i shown, an electrode structure is formed.

[0088] In this step, for example, a conductive layer is formed by a deposition process. The conductive layer covers the surface of the interlayer dielectric layer 270 and fills the vias in the interlayer dielectric layer 270. Then, for example, a CMP process is used to planarize the conductive layer so that the conductive layer has a flat surface. Then, the conductive layer is etched by a photolithography and etching process to form an electrode structure.

[0089] The electrode structure includes a first gate electrode 281, a first source electrode 282, and a first drain electrode 283. The first gate electrode 281 reaches the top of the first gate structure 231 and contacts the gate contact layer 250c at the top of the first gate structure 231. The first source electrode 282 and the first drain electrode 283 respectively reach the surface of the second doped region 220 and contact the doped region contact layer 250d at the top of the second doped region 220. In this embodiment, the electrode structure further includes a sidewall electrode 284 reaching the sidewall of the first gate structure 231, and the sidewall electrode 284 contacts the sidewall contact layer 250a on the sidewall.

[0090] The electrode structure includes a select gate electrode 285, a second source electrode 286, and a second drain electrode 287. The select gate electrode 285 reaches the top of the second gate structure (select gate) 232 and contacts the gate contact layer 250c of the second gate structure (select gate) 232. The second source electrode 286 and the second drain electrode 287 respectively reach the surface of the second doped region 220 and contact the doped region contact layer 250d on the top of the second doped region 220.

[0091] Furthermore, the electrode structure further includes a third gate structure control electrode 288, and the third gate structure control electrode 288 contacts any one of the electrode layers 250b on the top of the third gate structure (floating gate) 233, the electrode layer 250b on the sidewall of the third gate structure (floating gate) 233, the second gate structure (select gate) 232, and the electrode layer 250b between the third gate structure (floating gate) 233 and the second gate structure (select gate) 232. In this embodiment, the third gate structure control electrode 288 contacts the electrode layer 250b between the second gate structure (select gate) 232 and the third gate structure (floating gate) 233.

[0092] The unexpected technical effect of this application is:

[0093] According to the semiconductor device and its manufacturing method of the embodiment of the present invention, the electrode layer on the second dielectric layer and the third gate structure (floating gate) form upper and lower electrode plates, the electrode layer on the second dielectric layer, the second dielectric layer, and the third gate structure (floating gate) form a capacitor structure, and the upper electrode plate (electrode layer) of the capacitor structure is led out through the third gate structure control electrode.

[0094] Before the OTP structure encoding, a positive voltage is applied to the third gate structure control electrode. At this time, a downward electric field is formed in the capacitor structure formed by the electrode layer, the second dielectric layer, and the third gate structure (floating gate), and the electrons in the third gate structure (floating gate) move upward. The electrons break through the barrier of the third gate structure (floating gate) / second dielectric layer (especially SiON) and are lost in large quantities, achieving the effect of clearing the charges in the third gate structure (floating gate).

[0095] After the OTP structure encoding is completed, due to the high-k property of the second dielectric layer (especially the dielectric layer SiON), it is difficult for the electrons in the third gate structure (floating gate) to break through the second dielectric layer, especially the barrier of the dielectric layer (SiON). Furthermore, after the OTP structure encoding is completed, a negative voltage can be applied to the third gate structure control electrode, and an upward electric field is formed in the capacitor structure formed by the electrode layer on the second dielectric layer, the second dielectric layer, and the third gate structure (floating gate), suppressing the loss of electrons in the third gate structure (floating gate) and further improving the reliability of the data retention ability in the OTP structure.

[0096] In this embodiment, since an electrode layer is provided above the third gate structure (floating gate) and a third gate structure control electrode connected to the electrode layer above the third gate structure (floating gate) is provided, the OTP structure can achieve a limited number of erasures and writes, further greatly improving the error tolerance of the OTP structure. Specifically, when the OTP structure is encoded incorrectly, a positive voltage is applied to the third gate structure control electrode. At this time, a downward electric field is formed in the capacitive structure formed by the electrode layer, the second dielectric layer, and the third gate structure (floating gate). The electrons introduced by programming in the third gate structure (floating gate) move upward, and the electrons break through the barrier of the third gate structure (floating gate) / second dielectric layer (especially the dielectric layer SiON) and flow out, realizing the function of electron erasure, and further enabling the OTP structure to achieve a limited number of repeated programming.

[0097] Furthermore, the electrode layer covers the top and sidewalls of the third gate structure (floating gate), that is, the electrode layer completely covers the third gate structure (floating gate), so that a relatively small voltage applied to the third gate structure control electrode can achieve the erasure of the charge in the third gate structure (floating gate) and the retention of the stored charge.

[0098] Furthermore, the electrode layer on the top of the third gate structure (floating gate) extends above the semiconductor layer between the second gate structure (select gate) and the third gate structure (floating gate), and above the second gate structure (select gate). The third gate structure control electrode can be arranged between the second gate structure (select gate) and the third gate structure (floating gate). On the one hand, the arrangement of the third gate structure control electrode does not affect the extraction of other electrodes (such as the select gate electrode, the second source electrode, and the second drain electrode), and the overall area and overall structure of the electrode structure of the OTP structure will not be affected. On the other hand, the third gate structure control electrode is arranged between the second gate structure (select gate) and the third gate structure (floating gate), so that the bottom of the third gate structure control electrode is connected to the planar electrode layer, which is more conducive to the etching of the third gate structure control electrode.

[0099] Furthermore, the second dielectric layer is located on the third gate structure (floating gate) and extends onto the semiconductor layer between the second gate structure (select gate) and the third gate structure (floating gate), avoiding the formation of silicide in the semiconductor layer between the second gate structure (select gate) and the third gate structure (floating gate), which affects the conduction of the channel between the second gate structure (select gate) and the third gate structure (floating gate), and can effectively avoid the formation of a path for electron leakage in the third gate structure (floating gate) caused by the formation of silicide in the semiconductor layer between the second gate structure (select gate) and the third gate structure (floating gate), further avoiding the loss of the stored charge in the third gate structure (floating gate).

[0100] In this embodiment, while forming the first dielectric layer on the sidewall of the first gate structure in the LDMOS structure, the second dielectric layer on the third gate structure in the OTP structure is formed, realizing the process compatibility between the LDMOS structure and the OTP structure. Compared with forming the first dielectric layer and the second dielectric layer separately, at least one photolithography step is saved in this embodiment.

[0101] Furthermore, in order to realize the process compatibility between the LDMOS structure and the OTP structure and save the photolithography steps, a parasitic polysilicon layer is introduced above the third gate structure in the OTP structure. In this embodiment, the parasitic polysilicon layer is retained and converted into an electrode layer. A capacitor is formed between this electrode layer and the floating gate, and it is led out via the control electrode of the third gate structure. By providing different voltages to the control electrode of the third gate structure, the initial charges in the floating gate are erased, and functions such as limited erasing and writing that the traditional OTP structure does not have, stronger data storage ability, and longer storage time are realized.

[0102] As described above in the embodiments according to the present application, these embodiments do not describe all the details in detail, nor limit the application to only the specific embodiments described. Obviously, many modifications and variations can be made according to the above description. These embodiments are selected and specifically described in this specification to better explain the principle and practical application of the present application, so that those skilled in the art can make good use of the present application and its modifications based on the present application. The present application is only limited by the claims and their full scope and equivalents.

Claims

1. A semiconductor device, characterized in that, Comprising: A semiconductor layer; A first gate structure, a second gate structure, and a third gate structure, located on the semiconductor layer; A doped region, located in the semiconductor layer, and the semiconductor layer, the second gate structure, and the doped regions on both sides of the second gate structure form a select transistor of the OTP structure, and the semiconductor layer, the third gate structure, and the doped regions on both sides of the third gate structure form a floating-gate transistor of the OTP structure; A first dielectric layer and a second dielectric layer, the first dielectric layer is at least located on the sidewalls of the first gate structure, and the second dielectric layer is at least located on the third gate structure; And A sidewall contact layer and an electrode layer, the sidewall contact layer is located on the first dielectric layer, and the electrode layer is located on the second dielectric layer; Wherein, the electrode layer, the second dielectric layer, and the third gate structure form a capacitor structure, and the electrode layer is led out through the control electrode of the third gate structure; the first dielectric layer and the second dielectric layer are formed simultaneously, and the sidewall contact layer and the electrode layer are formed simultaneously.

2. The semiconductor device according to claim 1, wherein The source region of the floating-gate transistor is connected to the drain region of the select transistor; Before programming the OTP structure, a positive voltage is applied to the control electrode of the third gate structure to clear the initial charges in the floating gate.

3. The semiconductor device according to claim 1, wherein, The source region of the floating-gate transistor is connected to the drain region of the select transistor; After programming the OTP structure, a negative voltage is applied to the control electrode of the third gate structure to retain the electrons in the floating gate.

4. The semiconductor device according to claim 1, characterized in that, The source region of the floating-gate transistor is connected to the drain region of the select transistor; A positive voltage is applied to the control electrode of the third gate structure to clear the electrons in the floating gate.

5. The semiconductor device according to claim 1, wherein The second dielectric layer covers the third gate structure and the semiconductor layer between the third gate structure and the second gate structure, and extends to at least a part of the second gate structure; The control electrode of the third gate structure is in contact with the electrode layer between the third gate structure and the second gate structure.

6. The semiconductor device according to claim 1, wherein The first dielectric layer includes a stack of silicon oxynitride layer and silicon oxide layer; the second dielectric layer includes a stack of silicon oxynitride layer and silicon oxide layer.

7. A method for manufacturing a semiconductor device, characterized in that, Comprising: Forming a first gate structure, a second gate structure, and a third gate structure on the semiconductor layer; Forming a doped region in the semiconductor layer, and the semiconductor layer, the second gate structure, and the doped regions on both sides of the second gate structure form a select transistor of the OTP structure; the semiconductor layer, the third gate structure, and the doped regions on both sides of the third gate structure form a floating-gate transistor of the OTP structure; Forming a first dielectric layer at least on the sidewalls of the first gate structure, and forming a second dielectric layer at least on the third gate structure, and the first dielectric layer and the second dielectric layer are formed simultaneously; Forming a sidewall contact layer on the first dielectric layer, and forming an electrode layer on the second dielectric layer, and the sidewall contact layer and the electrode layer are formed simultaneously; Wherein, the electrode layer, the second dielectric layer, and the third gate structure form a capacitor structure, and the electrode layer is led out through the control electrode of the third gate structure.

8. The method according to claim 7, wherein The steps of forming the first dielectric layer, the second dielectric layer, the sidewall contact layer, and the electrode layer include: A dielectric layer is formed on the semiconductor layer and on the first gate structure, the second gate structure, and the third gate structure, and the dielectric layer conformally covers the semiconductor layer and the first gate structure, the second gate structure, and the third gate structure; A polysilicon layer is formed on the dielectric layer; A patterned mask layer is formed on the polysilicon layer; The polysilicon layer and the dielectric layer are etched via the patterned mask layer to form a first dielectric layer, a polysilicon layer on the first dielectric layer, a second dielectric layer, and a polysilicon layer on the second dielectric layer, wherein the first dielectric layer at least covers the sidewall of the first gate structure, and the second dielectric layer at least covers the third gate structure; The polysilicon layer on the first dielectric layer and the polysilicon layer on the second dielectric layer are alloyed to form a sidewall contact layer on the first dielectric layer and an electrode layer on the second dielectric layer.

9. The method according to claim 7, wherein The second dielectric layer covers the third gate structure and the semiconductor layer between the third gate structure and the second gate structure, and extends to at least a portion of the second gate structure; The control electrode of the third gate structure is in contact with the electrode layer between the third gate structure and the second gate structure.

10. The method according to claim 7, wherein The first dielectric layer includes a stack of a silicon oxynitride layer and a silicon oxide layer; the second dielectric layer includes a stack of a silicon oxynitride layer and a silicon oxide layer.

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