Capacitor including capacitor dielectric layer having sloped sidewalls

Abstract

The present disclosure relates to a capacitor including a capacitor dielectric layer having sloped sidewalls. In an example, an integrated circuit (IC) includes a semiconductor substrate (302), a capacitor, an interconnect dielectric layer (602), and a metal via (704). The capacitor is over the semiconductor substrate (302) and has a capacitor stack including a first conductive layer (314), a capacitor dielectric layer (316), and a second conductive layer (318). The first conductive layer (314) is over the semiconductor substrate (302). The capacitor dielectric layer (316) is over the first conductive layer (314) and has a dielectric sloped sidewall surface (506). The second conductive layer (318) is over the capacitor dielectric layer (316). The interconnect dielectric layer (602) is over the second conductive layer (318). The metal via (704) passes through the interconnect dielectric layer (602) and the dielectric sloped sidewall surface (506) to the first conductive layer (314).

Description

Technical Field

[0001] The present disclosure relates generally to integrated circuits and, more particularly, to a capacitor including a capacitor dielectric layer having sloped sidewalls. Background Art

[0002] Capacitors have a wide range of applications, such as use in combination with other components in integrated circuits. Capacitors used to implement large capacitance occupy a large area on the die. This increases the die area and / or may require each die to be larger, thereby reducing the number of dies that can be manufactured from a single wafer. Summary of the invention

[0003] This summary is provided to introduce a brief selection of the disclosed concepts in a simplified form, which will be further described in the following detailed description including the provided figures. Various disclosed devices and methods can be advantageously applied in the context of semiconductor processing, where capacitors can be manufactured in integrated circuits (ICs). Some examples described herein can be applied to patterning capacitor stacks of capacitors in ICs. Although it is contemplated that such examples avoid multiple lithography and etching processes, no specific results are required unless explicitly recited in a particular claim.

[0004] The example described herein is an integrated circuit (IC). The IC includes a semiconductor substrate, a capacitor, an interconnect dielectric layer, and a metal via. The semiconductor substrate has a top surface. The capacitor is above the semiconductor substrate. The capacitor has a capacitor stack, the capacitor stack including a first capacitor conductive layer, a capacitor dielectric layer, and a second capacitor conductive layer. The first capacitor conductive layer is above the semiconductor substrate. The capacitor dielectric layer is above the first capacitor conductive layer. The capacitor dielectric layer has a dielectric inclined sidewall surface. The second capacitor conductive layer is above the capacitor dielectric layer. The interconnect dielectric layer is above the second capacitor conductive layer. The metal via passes through the dielectric inclined sidewall surfaces of the interconnect dielectric layer and the capacitor dielectric layer to reach the first capacitor conductive layer.

[0005] Another example described herein is a method of manufacturing an IC. A capacitor is formed over a semiconductor substrate having a top surface. The capacitor has a capacitor conductive-dielectric stack, the capacitor conductive-dielectric stack including a first conductive layer, a capacitor dielectric layer, and a second conductive layer. The capacitor dielectric layer is over the first conductive layer. The second conductive layer is over the capacitor dielectric layer. Forming the capacitor includes: etching the second conductive layer and the capacitor dielectric layer, thereby forming an inclined dielectric sidewall of the capacitor dielectric layer; forming an interconnect dielectric layer over the first conductive layer, the capacitor dielectric layer, and the second conductive layer; and forming a metal via through the interconnect dielectric layer and the inclined dielectric sidewall to the first conductive layer.

[0006] Another example described herein is a method for semiconductor processing. A capacitor stack is formed above a top surface of a semiconductor substrate. The capacitor stack includes a first conductive layer, a dielectric layer, and a second conductive layer. The first conductive layer is above the semiconductor substrate. The dielectric layer is above the first conductive layer. The second conductive layer is above the dielectric layer. A photoresist layer is patterned above the capacitor stack using grayscale lithography, thereby forming a patterned photoresist layer above the second conductive layer. The patterned photoresist layer has an inclined sidewall that forms an angle of less than 60° relative to the top surface. The capacitor stack is etched using the patterned photoresist layer as a mask. Etching includes forming a plasma with a gas mixture including chlorine (Cl2) gas, boron chloride (BCl3) gas, argon (Ar) gas, and nitrogen (N2) gas, a source power, and a bias power. The bias power is at least one-tenth of the source power.

[0007] The foregoing summary of the invention has been quite extensively summarized various features of examples of the present disclosure so that the following detailed description may be better understood. Additional features and advantages of such examples will be described below. The described examples may be readily used as a basis for modifying or designing other examples within the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to understand the above features in detail, reference is made to the following detailed description in conjunction with the accompanying drawings.

[0009] Figure 1 is a schematic diagram of a semiconductor processing tool for semiconductor processing according to some examples.

[0010] Figure 2 is a flow chart of a method of manufacturing an integrated circuit (IC) including a capacitor according to some examples.

[0011] Figure 3 , 4 , 5A, 6, and 7A are cross-sectional views of ICs during corresponding fabrication stages according to some examples.

[0012] Figure 5B and 7B According to some examples, Figure 5A and 7A Layout diagram of the IC.

[0013] Figure 8 is a cross-sectional view of an IC according to some examples.

[0014] Fig. 9 is a scanning electron microscope (SEM) image of a formed capacitor structure according to some examples.

[0015] Fig.10is a block diagram of a processor-based system according to some examples.

[0016] The drawings and accompanying detailed description are provided for understanding the features of the various examples and do not limit the scope of the appended claims. The examples illustrated in the drawings and described in the accompanying detailed description can be easily used as a basis for modifying or designing other examples within the scope of the appended claims. Where possible, the same reference numerals may be used to refer to the same elements that are common among the drawings. The drawings are drawn to clearly illustrate the relevant elements or features and are not necessarily drawn to scale. DETAILED DESCRIPTION

[0017] Various features are described below with reference to the drawings. The illustrated examples may not have all aspects or advantages shown. An aspect or advantage described in conjunction with a particular example is not necessarily limited to that example and may be practiced in any other example, even if not so illustrated or not explicitly described. In addition, the methods described herein may be described in a particular order of operations, but other methods according to other examples may be implemented with various other orders of more or fewer operations (e.g., including different serial or parallel executions of various operations).

[0018] The present disclosure relates to a capacitor, comprising a capacitor stack having a capacitor dielectric layer, the capacitor dielectric layer having a shallow inclined sidewall between conductive layers, at least one conductive layer having a steep inclined sidewall. In some examples, the capacitor is above a semiconductor substrate. The capacitor comprises a capacitor stack, the capacitor stack comprising a capacitor dielectric layer and an upper capacitor conductive layer above the capacitor dielectric layer. The capacitor stack further comprises a lower capacitor conductive layer. The lower capacitor conductive layer may have a conductive composition identical or similar to that of the upper capacitor conductive layer, or may be an interconnect metallization layer that additionally provides signal routing between components of an integrated circuit (IC), the capacitor being a part of the integrated circuit. The capacitor dielectric layer has a shallow inclined dielectric sidewall surface, and the upper conductive layer has a steep inclined sidewall. The interconnect dielectric layer is above the capacitor stack, included above the upper capacitor conductive layer. The metal vias that fall on the lower capacitor conductive layer pass through the interconnect dielectric layer and through the inclined sidewall surface of the capacitor dielectric layer. In some examples, etching is used to pattern the capacitor stack to form a capacitor. The photoresist layer may be patterned using grayscale lithography and may be used as a mask during etching. In some examples, etching the capacitor stack uses a gas mixture including chlorine (Cl2) gas, boron chloride (BCl3) gas, argon (Ar) gas, and nitrogen (N2) gas, and the etching can balance physical etching and chemical etching, so that the etching rate of the capacitor conductive layer is greater than the etching rate of the capacitor dielectric layer. Other examples include semiconductor processing tools configured to perform such etching. Some examples can achieve patterning of the capacitor stack in a single etch, so that metal vias reaching the intermediate capacitor conductive layer can be formed, and multiple photolithography processes and multiple etching processes used to pattern the capacitor stack can be avoided. Other benefits or advantages can be achieved through various examples.

[0019] Figure 1 FIG. 1 is a schematic diagram of a semiconductor processing tool 100 for semiconductor processing according to some examples. Figure 1 1 and 2 to clearly illustrate various aspects described herein. In this example, the semiconductor processing tool 100 is shown as an inductively coupled plasma (ICP) processing tool. In other examples, the semiconductor processing tool 100 can be configured as a capacitively coupled plasma (CCP) processing tool, an electron cyclotron resonance (ECR) processing tool, or another processing tool. In some examples, the semiconductor processing tool 100 is a semiconductor etching tool. In some examples, the semiconductor processing tool 100 can be a tool for other semiconductor processing.

[0020] The semiconductor processing tool 100 includes an upper chamber formed by an upper chamber housing 102 and a lower chamber formed by a lower chamber housing 104. The upper chamber housing 102 includes a dome 106. The upper chamber housing 102 has an interior volume 108 defined by an inner wall of the upper chamber housing 102 and the dome 106. Gases and plasma are formed in the interior volume 108 for semiconductor processing.

[0021] The semiconductor processing tool 100 includes a substrate support 110. The substrate support 110 is disposed on and supported by a pedestal 112. The substrate support 110 has a support surface 114 configured to support a semiconductor substrate 116 during semiconductor processing. During semiconductor processing, the semiconductor substrate 116 is disposed on the support surface 114 of the substrate support 110.

[0022] The pedestal 112 is configured to move the substrate support 110 from the lower chamber (formed by the lower chamber housing 104) to the upper chamber (formed by the upper chamber housing 102), and vice versa. In the lowered position of the pedestal 112, the substrate support 110 is in the lower chamber, and the semiconductor substrate 116 can be transferred to or from the substrate support 110 through a slit valve 118 in the wall of the lower chamber housing 104 (e.g., by a robotic arm). The load lock or transfer chamber can engage the semiconductor processing tool 100 at the slit valve 118 so that during the transfer of the semiconductor substrate 116, the volume of the semiconductor processing tool 100 can be maintained at a low or reduced pressure (e.g., maintained under vacuum). In the upper position of the pedestal 112, the semiconductor substrate 116 is in the upper chamber housing 102 and exposed to the interior volume 108 in the upper chamber housing 102. In this position, the support surface 114 of the substrate support 110 may be coplanar with or higher than the lower interior surface of the upper chamber housing 102 , and the substrate support 110 may be at least partially disposed in the lower chamber housing 104 .

[0023] The substrate support 110 includes an electrostatic chuck (ESC) 120 and a base plate 122. In the illustrated configuration, the ESC 120 is disposed above and on the base plate 122. The base plate 122 is disposed above and on the pedestal 112.

[0024] The ESC 120 includes a clamping electrode 124 and a biasing electrode 126 disposed in and / or coated by a dielectric material. The clamping electrode 124 is electrically coupled to a power source, such as a direct current (DC) power source (not shown), and is configured to clamp the semiconductor substrate 116 to the substrate support 110, for example, by electrostatic force. The biasing electrode 126 is electrically coupled to a power source 128, and is configured to provide bias power in a semiconductor process. The power source 128 may be configured to generate alternating current (AC) power and supply it to the biasing electrode 126, such as at a radio frequency (e.g., a frequency of 13.56 MHz or 60 MHz) or another frequency. The power source 128 may supply AC power having any voltage or ampere signal waveform, such as a triangular waveform, a square waveform, a sine waveform, a pulse waveform, etc. The power source 128 may include other components not shown, such as an impedance matching network.

[0025] The conductive coil 130 is disposed on the upper chamber housing 102 and laterally surrounds the dome 106. The conductive coil 130 is disposed in a coil housing 132 on the upper chamber housing 102. The conductive coil 130 is electrically coupled to a power supply 134 and is configured to generate plasma in a semiconductor process. The power supply 134 may be configured to generate AC power and current and supply it to the conductive coil 130, such as at a radio frequency (e.g., a frequency of 13.56 MHz or 60 MHz) or another frequency. The power supply 134 may supply AC power with any voltage or ampere signal waveform, such as a triangular waveform, a square waveform, a sine waveform, a pulse waveform, etc. The power supply 134 may include other components not shown, such as an impedance matching network.

[0026] The upper chamber housing 102 has a gas inlet 140 fluidly coupled to a gas manifold 142, and the upper chamber housing 102 has a gas outlet 144 fluidly coupled to an exhaust system 146. During semiconductor processing, gas flows from the gas manifold 142 through the gas inlet 140 to the interior volume 108. The interior volume 108 is vertically disposed between the conductive coil 130 surrounding the dome 106 and the substrate support 110, and is typically where plasma is generated (using gas flowing into the interior volume 108) during semiconductor processing. During semiconductor processing, a semiconductor substrate 116 disposed on a supporting surface 114 of the substrate support 110 is exposed to the plasma in the interior volume 108. Then, the gas may flow through the gas outlet 144 to the exhaust system 146 to be exhausted from the interior volume 108 of the chamber.

[0027] The gas manifold 142 is fluidly coupled to the mass flow controllers 160, 162, 164, 166, respectively, and the mass flow controllers 160, 162, 164, 166 are fluidly coupled to the gas tanks 170, 172, 174, 176, respectively. The mass flow controllers 160 to 166 are configured to be selectively opened and closed. When in the open position, the mass flow controllers 160 to 166 allow the gas from the corresponding gas tank 170 to 176 to flow through the corresponding mass flow controller 160 to 166 to the gas manifold 142. When in the closed position, the mass flow controllers 160 to 166 prevent the gas from the corresponding gas tank 170 to 176 from flowing therethrough. The gas manifold 142 can pass the gas flowing from the mass flow controllers 160 to 166 to the upper chamber (e.g., through the gas inlet 140), and / or can mix and pass the gas flowing from multiple mass flow controllers 160 to 166 to the upper chamber. As depicted, in some examples, gas tank 170 contains chlorine (Cl2) gas; gas tank 172 contains boron trichloride (BCl3) gas; gas tank 174 contains nitrogen (N2) gas; and gas tank 176 contains argon (Ar) gas. In some examples, gas tanks 170-176 may contain highly pressurized liquid forms that evaporate into gaseous forms when the pressure is reduced.

[0028] The semiconductor processing tool 100 includes a controller 180. The controller 180 may be or include any processor-based system, which may be or include a hardened processor architecture, a soft processor (e.g., implemented on a programmable fabric of a field programmable gate array (FPGA)), or a combination thereof. For example, the controller 180 may be or include a computer, a server, a programmable logic controller (PLC), etc., or a combination thereof. The controller 180 may control the operation of the semiconductor processing tool 100 and may be programmed to implement the operation of the semiconductor processing tool 100 as described herein. In addition, the controller 180 is communicatively coupled to the pedestal 112, the power supplies 128, 134, and the mass flow controllers 160-166 to control the operation of those components.

[0029] Although not shown, the semiconductor processing tool 100 may include a thermal control component that can control, for example, the processing temperature of the internal volume 108 and / or can control the temperature of the semiconductor substrate 116. For example, the substrate support 110 may include a heater and a fluid channel. The heater may include one or more resistive heating elements disposed in a dielectric thermally conductive material. An electric current may flow through the one or more resistive heating elements, which may generate thermal energy that is conducted to the semiconductor substrate 116. The fluid channel may be disposed in the dielectric material and / or coated by the dielectric material. The fluid channel may be configured to flow a fluid (e.g., a liquid or a gas) therethrough to remove and dissipate thermal energy from the semiconductor substrate 116. The fluid channel may be referred to as a cooler. The sidewalls of the upper chamber housing 102 and the sidewalls of the lower chamber housing 104 may also include fluid channels configured to remove and dissipate thermal energy from the internal volume 108 and / or the semiconductor substrate 116. The coil housing 132 may also include fluid channels configured to remove and dissipate thermal energy from the conductive coil 130. The controller 180 may be communicatively coupled to the thermal control assembly and thereby control the temperature of the semiconductor substrate 116 and / or the interior volume 108 during semiconductor processing.

[0030] Figure 2 FIG. 2 is a flow chart of a method 200 of manufacturing an integrated circuit (IC) including a capacitor according to some examples. Figure 3 , 4 , 5A, 6 and 7A are described in the context of Figure 2 Method 200, Figure 3 , 4 , 5A, 6, and 7A are cross-sectional views of example ICs during corresponding fabrication stages according to some examples. Figure 5B and 7B is the layout diagram of the example IC and corresponds to Figure 5A and 7A . Figure 3 , 4 , 5A, 5B, 6, 7A and 7B are shown with xyz axis references to facilitate orientation of the drawings and aspects thereof. Figure 5B and 7B The sight directions in Figure 5A and 7A The view shown in the cross-sectional view.

[0031] Also refer to Figure 2 Box 202 and Figure 3, a capacitor stack is formed over the top surface of semiconductor substrate 302. Semiconductor substrate 302 may be or include a bulk wafer, a semiconductor on insulator (SOI) substrate, etc. Semiconductor substrate 302 may be or include any semiconductor material, and may include a bulk material (e.g., bulk silicon) and / or one or more epitaxial layers of semiconductor material. One or more active devices (e.g., transistor 304) are formed in, on, and / or over the top surface of semiconductor substrate 302. A pre-metal dielectric (PMD) 306 is over semiconductor substrate 302. PMD 306 may include a conformal dielectric layer (e.g., an etch stop layer) over (e.g., possibly over) the top surface of semiconductor substrate 302 and the active devices (e.g., transistor 304), and may include a dielectric layer over the conformal dielectric layer. In some examples, the conformal dielectric layer may be or include silicon nitride, silicon oxynitride, etc., or a combination thereof, and the dielectric layer may be or include silicon oxide, phosphosilicate glass (PSG), etc., or a combination thereof. One or more dielectric layers may be above PMD 306. As depicted, an interconnect dielectric layer 308 (e.g., an interlayer dielectric (ILD), an intermetallic dielectric (IMD), etc.) is above PMD 306. Interconnect dielectric layer 308 may be or include a dielectric layer such as PMD 306. Conductive layer 310 is above or on interconnect dielectric layer 308. In some examples, conductive layer 310 is "in" interconnect dielectric layer 308 because a top surface of conductive layer 310 is coplanar with a top surface of interconnect dielectric layer 308. In some other examples, conductive layer 310 is on PMD 306. Conductive layer 310 may be a conductive (e.g., metal) line or plate, such as in a metallization layer, and may be part of an interconnect metallization layer that includes routing between components at the same level above semiconductor substrate 302, or may be a supplemental conductive layer that is not typically used for interconnects. In some examples, conductive layer 310 is or includes aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), alloys thereof, combinations of layers thereof, and the like.

[0032] The capacitor stack includes a first capacitor dielectric layer 312, a lower capacitor conductive layer 314, a second capacitor dielectric layer 316, and an upper capacitor conductive layer 318. The first capacitor dielectric layer 312 is formed over or on conductive layer 310. The lower capacitor conductive layer 314 is formed over or on the first capacitor dielectric layer 312. The second capacitor dielectric layer 316 is formed over or on the lower capacitor conductive layer 314. And the upper capacitor conductive layer 318 is formed over or on the second capacitor dielectric layer 316. Additional one or more capacitor dielectric layers and one or more capacitor conductive layers may be formed to continue Figure 3. As described subsequently, in examples including a conductive layer 310, this layer may be considered part of the capacitor stack because the conductive layer 310 forms a plate of the formed capacitor; however, in some examples as in the illustrated example, the conductive layer is not patterned with the other layers of the capacitor stack. The capacitor dielectric layers 312, 316 may be formed as respective blanket layers deposited by any suitable deposition process, such as chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), atomic layer deposition (ALD), etc. The capacitor conductive layers 314, 318 may be formed as respective blanket layers deposited by any suitable deposition process, such as CVD, physical vapor deposition (PVD), etc.

[0033] In some examples, each of the capacitor dielectric layers 312, 316 includes or is silicon dioxide (SiO2), silicon nitride (SiN), hafnium dioxide (HfO2), or another dielectric material. In some examples, each of the capacitor conductive layers 314, 318 includes or is titanium nitride (TiN) or another conductive material (e.g., a metal or metal-containing material). In some examples, the thickness of each of the capacitor dielectric layers 312, 316 is in the range of 10nm to 200nm, such as about 110nm. In some examples, the thickness of each of the capacitor conductive layers 314, 318 is in the range of 20nm to 500nm, such as about 100nm. Other thicknesses may be implemented.

[0034] Also refer to Figure 2 Box 204 and Figure 4 , a patterned photoresist 402 is formed over the capacitor stack using grayscale lithography. The patterned photoresist 402 has a sloped sidewall 404 formed using grayscale lithography. The photoresist 402 is deposited (e.g., by spin coating) on ​​or over the upper capacitor conductive layer 318 and is patterned using grayscale lithography to form sloped sidewalls 404, etc. in the photoresist 402. Any suitable grayscale lithography technique may be implemented. For example, i-line grayscale lithography may be implemented. In other examples, KrF grayscale technology may be implemented. In other examples, maskless digital grayscale lithography may be implemented. In some examples, the sloped sidewall 404 may have an angle α of less than 60°, and more particularly in the range of 10° to 30°, for example, about 16°, relative to the top surface of the upper capacitor conductive layer 318 and / or the bottom surface of the photoresist 402. P .

[0035] At block 206, the semiconductor substrate 302 is transferred to a chamber of a semiconductor processing tool. Figure 1As an example, the semiconductor processing tool 100 of FIG. 1 may transfer the semiconductor substrate 302 onto the support surface 114 of the substrate support 110 using, for example, a transfer chamber or load lock that is external to the lower chamber housing 104 and engages the lower chamber housing 104 at a slit valve 118 so that the internal volume in the semiconductor processing tool 100 and the semiconductor substrate 302 is not exposed to the atmospheric ambient environment during the transfer. With the pedestal 112 in the lower position, the semiconductor substrate 302 is transferred from the transfer chamber or load lock through the slit valve 118 and onto the support surface 114 of the substrate support 110. The pedestal 112 is then raised so that the substrate support 110 is at least partially within the upper chamber housing 102 and the semiconductor substrate 302 is exposed to the internal volume 108.

[0036] Also refer to Figure 2 Box 208 and Figure 5A , an etch is performed on the semiconductor substrate 302 in the chamber. Once exposed, the etch simultaneously etches or consumes the photoresist 402, the upper capacitor conductive layer 318, the second capacitor dielectric layer 316, the lower capacitor conductive layer 314, and the first capacitor dielectric layer 312. The etch is anisotropic and removes the upper capacitor conductive layer 318 and the lower capacitor conductive layer 314 at a greater rate than the second capacitor dielectric layer 316 and the first capacitor dielectric layer 312. The patterned photoresist 402 is used as a mask in the etch. A balanced etch recipe is implemented to transfer the sloped sidewall to the capacitor stack. The balanced etch recipe balances the chemical etching component and the physical etching component so that at least three different materials (e.g., the photoresist 402, the capacitor dielectric layers 312, 316, and the capacitor conductive layers 314, 318) are etched simultaneously to transfer the sloped sidewall to the capacitor dielectric layers 312, 316, and the capacitor conductive layers 314, 318. The etching may remove the conductive layer 310 at a slower rate than the first capacitor dielectric layer 312 , such that an insignificant amount of the conductive layer 310 is removed while removing the first capacitor dielectric layer 312 over the conductive layer 310 .

[0037] After etching, the first capacitor dielectric layer 312 has a sloped sidewall 502. The first capacitor dielectric layer 312 has a bottom angle where the sloped sidewall 502 meets the top surface of the conductive layer 310, and has a top angle where the sloped sidewall 502 meets the bottom surface of the lower capacitor conductive layer 314. The lower capacitor conductive layer 314 has a sloped sidewall 504. The lower capacitor conductive layer 314 has a bottom angle where the sloped sidewall 504 meets the top surface of the first capacitor dielectric layer 312, and has a top angle where the sloped sidewall 504 meets the bottom surface of the second capacitor dielectric layer 316. The second capacitor dielectric layer 316 has a sloped sidewall 506. The second capacitor dielectric layer 316 has a bottom angle where the sloped sidewall 506 meets the top surface of the lower capacitor conductive layer 314, and has a top angle where the sloped sidewall 506 meets the bottom surface of the upper capacitor conductive layer 318. The upper capacitor conductive layer 318 has a sloped sidewall 508. The upper capacitor dielectric layer 318 has a bottom angle where the sloped sidewall 508 meets the top surface of the second capacitor conductive layer 316, and has a top angle where the sloped sidewall 508 meets the bottom surface of the photoresist 402.

[0038] like Figure 5A As shown in the plane of the cross section of FIG. 1 , the inclined sidewall 502 forms an angle α with the top surface of the conductive layer 310 and / or the bottom surface of the first capacitor dielectric layer 312. D1 The inclined sidewall 504 forms an angle α with the top surface of the first capacitor dielectric layer 312 and / or the bottom surface of the lower capacitor conductive layer 314. C1 The inclined sidewall 506 forms an angle α with the top surface of the lower capacitor conductive layer 314 and / or the bottom surface of the second capacitor dielectric layer 316. D2 The sloped sidewall 508 forms an angle α with the top surface of the second capacitor dielectric layer 316 and / or the bottom surface of the upper capacitor conductive layer 318. C2 The respective top and bottom surfaces of the capacitor conductive layers 314, 318 and the capacitor dielectric layers 312, 316 may be parallel to each other and to the top surface of the semiconductor substrate 302. In such a case, the angle α D1 , α C1 , α D2 , α C2 , α P May be relative to the top surface of the semiconductor substrate 302 .

[0039] According to some examples, the angle α of the sloped sidewalls 502 , 506 of the capacitor dielectric layers 312 , 316 is D1 , α D2 One or both of the angles α and α of the inclined sidewalls 504 and 508 of the capacitor conductive layers 314 and 318 are smaller than the angles α of the inclined sidewalls 504 and 508 of the capacitor conductive layers 314 and 318. C1 , αC2 In addition, it has been observed in some examples that as the photoresist 402 is consumed during etching and the sloped sidewall 404 is laterally reduced, the more laterally distal angle (the sloped sidewall 404 away from the photoresist 402) of the same or similar material becomes greater than the more laterally proximal angle. Thus, in some examples, the angle α of the sloped sidewall 502 of the first capacitor dielectric layer 312 is D1 is greater than the angle α of the inclined sidewall 506 of the second capacitor dielectric layer 316 D2 Similarly, in some examples, the angle α of the inclined sidewall 504 of the lower capacitor conductive layer 314 is C1 is greater than the angle α of the inclined sidewall 508 of the upper capacitor conductive layer 318 C2 In some examples, the angle α of the sloped sidewalls 502 , 506 of the capacitor dielectric layers 312 , 316 is D1 , α D2 One or both of them are less than 10°, and the angle α of the inclined sidewalls 504 and 508 of the capacitor conductive layers 314 and 318 is C1 , α C2 The angle α of the inclined side walls 502, 504, 506, 508 is greater than 10°. D1 , α C1 , α D2 , α C2 The angles α of the inclined side walls 502, 504, 506, 508 may be different from each other. D1 , α C1 , α D2 , α C2 The angle α of the inclined sidewall 404 of the photoresist 402 may be P 60°, for example, at an angle α with the inclined side wall 404 P The difference ranges from 2° to 60°.

[0040] refer to Figure 5A The cross-sectional view and Figure 5B , the inclined sidewall 502 of the first capacitor dielectric layer 312 extends a lateral distance L from the top surface of the conductive layer 310 to the bottom surface of the lower capacitor conductive layer 314. D1 The sloped sidewalls 504 of the lower capacitor conductive layer 314 extend a lateral distance L from the top surface of the first capacitor dielectric layer 312 to the bottom surface of the second capacitor dielectric layer 316. C1 The sloped sidewall 506 of the second capacitor dielectric layer 316 extends a lateral distance L from the top surface of the lower capacitor conductive layer 314 to the bottom surface of the upper capacitor conductive layer 318. D2The sloped sidewall 508 of the upper capacitor conductive layer 318 extends a lateral distance L from the top surface of the second capacitor dielectric layer 316 to the bottom surface of the photoresist 402. C2 As shown, the lateral distance L of the inclined sidewalls 502, 504, 506, 508 is D1 , L C1 , L D2 , L C2 Aligned laterally (eg, along the x-direction).

[0041] According to some examples, the lateral distance L between the sloped sidewalls 502 , 506 of the capacitor dielectric layers 312 , 316 is D1 , L D2 One or both of them are greater than the lateral distance L of the inclined sidewalls 504, 508 of the capacitor conductive layers 314, 318. C1 , L C2 Each of, for example, at least twice. The lateral distance L of the inclined side walls 502, 504, 506, 508 D1 , L C1 , L D2 , L C2 In some examples, L D1 =L C1 and / or L C1 =L C2 .

[0042] According to some examples, etching may be performed using ICP-RIE, which may be performed using Figure 1The etching is performed by flowing a gas mixture into a chamber, such as into an interior volume 108 of an upper chamber housing 102. In some examples, the gas mixture includes chlorine (Cl2) gas, boron trichloride (BCl3) gas, argon (Ar) gas, and nitrogen (N2) gas. In such examples, the chlorine (Cl2) gas may flow at a flow rate in a range of 5 standard cubic centimeters (sccm) to 150 sccm; the boron trichloride (BCl3) gas may flow at a flow rate in a range of 5 sccm to 70 sccm; the argon (Ar) gas may flow at a flow rate in a range of 5 sccm to 150 sccm; and the nitrogen (N2) gas may flow at a flow rate in a range of 5 sccm to 150 sccm. The gas flow rates may vary depending on the size of the semiconductor substrate being processed (e.g., 200 mm wafers, 300 mm wafers, etc.). The pressure of the etch (e.g., in the interior volume 108 of the upper chamber housing 102) can be maintained at less than 50 mtorr (6.7 Pascal (Pa)), such as in the range of 6 mtorr (0.8 Pa) to 50 mtorr (6.7 Pa), and more particularly less than 15 mtorr (about 2 Pa), such as in the range of 6 mtorr (0.8 Pa) to 15 mtorr (about 2 Pa). The etch can be performed with a source power applied to the plasma activation system (e.g., the conductive coil 130) in the range of 0.5 kilowatts (kW) to 2 kW and a bias power applied to the bias electrode (e.g., the bias electrode 126) in the range of 50 watts (W) to 250 W. The sidewalls of the chamber (e.g., the sidewalls of the upper chamber housing 102) can be maintained at a temperature in the range of 60° C. to 100° C. The substrate support (eg, substrate support 110, and more particularly, ESC 120) may be maintained at a temperature in the range of 20°C to 60°C.

[0043] In a specific example, etching is performed on a capacitor stack including the materials indicated in Table 1 below and using the process parameters indicated in Table 1. The process parameters of the etching may be substantially ("about") the values ​​indicated in Table 1, such as within 5% of the corresponding indicated values ​​for flow rate, within 5% of the corresponding indicated values ​​for power, within 5% of the corresponding indicated values ​​for pressure, and within 5% of the corresponding indicated values ​​for temperature in degrees Celsius.

[0044]

[0045] According to some examples, during etching, the etching rate of the capacitor conductive layers 314, 318 is equal to or greater than the etching rate of the capacitor dielectric layers 312, 316. In some examples, the etching has a higher etching selectivity for the capacitor conductive layers 314, 318 relative to the capacitor dielectric layers 312, 316. The ratio of the etching rate of the capacitor conductive layers 314, 318 to the etching rate of the capacitor dielectric layers 312, 316 may be in the range of 1:1 to 10:1, for example, 3:2.

[0046] In addition, in the etching, the etching rate of the capacitor conductive layers 314, 318 is within 300% of the etching rate of the photoresist 402 and / or is equal to or greater than the etching rate of the photoresist 402. In some examples, the etching may have substantially equal etching selectivity to the capacitor conductive layers 314, 318 relative to the photoresist 402. The ratio of the etching rate of the capacitor conductive layers 314, 318 to the etching rate of the photoresist 402 may be in the range of 1:1 to 1:3. In addition, the etching rate of the capacitor dielectric layers 312, 316 is within 140% of the etching rate of the photoresist 402 and / or is equal to or greater than the etching rate of the photoresist 402. In some examples, the etching may have substantially equal etching selectivity to the capacitor dielectric layers 312, 316 relative to the photoresist 402. The ratio of the etching rate of the capacitor dielectric layers 312, 316 to the etching rate of the photoresist 402 may be in the range of 1.4:1 to 1:10.

[0047] In some examples, the etching rate of the capacitor conductive layers 314, 318 is about 10 angstroms per second. arrive The etching rate of the capacitor dielectric layers 312 and 316 is within the range of arrive The etching rate of the photoresist 402 is within the range of arrive within the range.

[0048] As previously stated, etching implements a balance between physical etching and chemical etching. Physical etching uses argon (Ar) with bias power to sputter the photoresist 402, the capacitor conductive layers 314, 318, and the capacitor dielectric layers 312, 316. Physical etching uses a high argon to nitrogen gas flow ratio and a high bias power. In some examples, the bias power is at least one-tenth of the source power. Chemical etching uses reactants to react with the materials of the photoresist 402, the capacitor conductive layers 314, 318, and the capacitor dielectric layers 312, 316. Chemical etching uses chlorine-based chemicals, such as chlorine (Cl2) gas and boron trichloride (BCl3) gas. For alternating silicon oxide (SiO2) and titanium nitride (TiN) capacitor stacks, the flow rates of chlorine (Cl2) gas and boron trichloride (BCl3) gas may be close to equal to increase the etching rate of silicon oxide (SiO2). Balancing the physical etch and the chemical etch allows the sloped sidewalls to be transferred from the photoresist 402 to the capacitor conductive layers 314, 318 and the capacitor dielectric layers 312, 316. Having only the physical etch may take an impractically long amount of time to etch the capacitor stack. Having too high a chemical etch relative to the physical etch may not transfer the sloped sidewalls to the capacitor conductive layers 314, 318 and the capacitor dielectric layers 312, 316, but may result in the capacitor conductive layers 314, 318 and the capacitor dielectric layers 312, 316 having vertical sidewalls because the chemical etch generally does not consume the photoresist 402. The balance between at least some of the process parameters including the source power and the bias power and the gas flow rate allows the sloped sidewalls to be transferred to the capacitor conductive layers 314, 318 and the capacitor dielectric layers 312, 316. Significantly modifying any of the parameters may result in the etch not transferring the sloped sidewalls to the layers.

[0049] In the case of forming the sloped sidewalls in the capacitor stack, performing the etching as described above allows the formation of metal vias that reach the intermediate capacitor conductive layer (e.g., the lower capacitor conductive layer 314) while using a single etching process to pattern the capacitor stack. The formation of this metal via is described subsequently. Performing this etching can avoid the use of multiple photolithography processes (using corresponding photolithography masks) and multiple etching processes to pattern the capacitor stack.

[0050] After etching, any remaining photoresist 402 may be removed, such as by ashing. Photoresist 402 may be removed while in the same chamber where etching is performed or after removal from the chamber.

[0051] refer to Figure 2 At block 210, the semiconductor substrate 302 is removed from the chamber. Figure 1As an example, the semiconductor processing tool 100 of the embodiment of the present invention can transfer the semiconductor substrate 302 from the support surface 114 of the substrate support 110 using, for example, a transfer chamber or load lock that is external to the lower chamber housing 104 and engages the lower chamber housing 104 at the slit valve 118 so that the internal volume of the semiconductor processing tool 100 and the semiconductor substrate 302 are not exposed to the atmospheric surrounding environment during the transfer. With the pedestal 112 in the upper position so that the semiconductor substrate 302 is in the upper chamber housing 102, the pedestal 112 is lowered so that the substrate support 110 is in the lower chamber housing 104. With the pedestal 112 in the lower position, the semiconductor substrate 302 is transferred from the support surface 114 of the substrate support 110 to the transfer chamber or load lock through the slit valve 118.

[0052] Also refer to Figure 2 Box 212 and Figure 6 , an interconnect dielectric layer 602 is formed over the etched capacitor stack. The interconnect dielectric layer 602 may be an ILD, an IMD, etc., and may be or include silicon oxide, phosphosilicate glass (PSG), etc., or a combination thereof. The interconnect dielectric layer 602 may be formed by CVD, PECVD, etc. The interconnect dielectric layer 602 is formed over the top surface of the upper capacitor conductive layer 318 and over and on the sloped sidewalls 502, 504, 506, 508. A planarization step, such as chemical mechanical polishing (CMP), may be performed after forming the interconnect dielectric layer 602.

[0053] Also refer to Figure 2 Box 214 and Fig. 7A, forming metal vias 702, 704, 706 reaching the conductive layers of the capacitor stack. Using appropriate photolithography and etching processes, an opening can be formed through the interconnect dielectric layer 602 to the conductive layer 310; an opening can be formed through the interconnect dielectric layer 602 and the sloped sidewall 506 of the second capacitor dielectric layer 316 to the lower capacitor conductive layer 314; and an opening can be formed through the interconnect dielectric layer 602 to the upper capacitor conductive layer 318. One or more metals of the metal vias 702, 704, 706 are deposited in the openings. The one or more metals can be deposited using one or more appropriate deposition processes (e.g., CVD, PVD, etc.). The one or more metals of metal vias 702, 704, 706 may include: one or more barrier layers and / or adhesion layers (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc., or a combination thereof) conforming in the corresponding openings; and fill metals (e.g., tungsten (W), copper (Cu), aluminum (Al), etc., or a combination thereof) above and / or on the one or more barrier layers and / or adhesion layers. The one or more metals in the corresponding openings form metal vias 702, 704, 706. Metal via 702 extends through interconnect dielectric layer 602 and contacts conductive layer 310; metal via 704 extends through interconnect dielectric layer 602 and second capacitor dielectric layer 316 (through inclined sidewall 506) and contacts lower capacitor conductive layer 314; and metal via 706 extends through interconnect dielectric layer 602 and contacts upper capacitor conductive layer 318.

[0054] As depicted, metal vias 702, 706 (which contact conductive layer 310 and upper capacitor conductive layer 318) are electrically connected together. Thus, conductive layer 310 and upper capacitor conductive layer 318 form a first terminal of the capacitor, and lower capacitor conductive layer 314 forms a second terminal of the capacitor. The capacitor may include additional dielectric layers and conductive layers. A capacitor having any configuration may be formed. The capacitor may at least partially form a circuit with an active device (e.g., transistor 304) within and / or above semiconductor substrate 302.

[0055] refer to Fig. 7A The cross-sectional view and Figure 7B In the layout diagram of FIG. 3 , the portion of the lower capacitor conductive layer 314 below the sloped sidewall 506 of the second capacitor dielectric layer 316 allows a larger landing area for the metal via 704 on the top surface of the lower capacitor conductive layer 314. Figure 7B , the inclined sidewall 506 of the second capacitor dielectric layer 316 extends along and beyond the edge of the inclined sidewall 508 of the upper capacitor conductive layer 318. The portion of the inclined sidewall 506 extending beyond and along the edge of the inclined sidewall 508 has a lateral distance L parallel to the edge of the inclined sidewall 508. ⊥ . Horizontal distance L⊥ The lateral distance L is parallel to the long axis of the portion of the second capacitor dielectric layer 316 that extends beyond and along the respective edge of the sloped sidewall 508. In the illustrated example, and for the respective edge, the lateral distance L ⊥ In the y direction and perpendicular to Fig. 7A As previously described, the inclined sidewall 506 has a lateral distance L D2 , which is the lateral dimension in the depicted plane of the cross section of the landing area. D2 A lateral distance L parallel to the minor axis of the portion of the inclined sidewall 506 extending along and beyond the respective edge of the inclined sidewall 508 and perpendicular to the portion of the inclined sidewall 506 ⊥ (eg, long axis). The metal via 704 is in the plane of the cross section and at a lateral distance L from D2 The same direction (eg, the x direction in the illustrated example) has a lateral dimension L V (e.g., width). Typically, the lateral distance L D2 and horizontal dimension L V Parallel to a lateral direction perpendicular to the nearest edge of the sloping sidewall 508. Although the above description is in the context of an edge of the sloping sidewall 508, the edges of the sloping sidewalls 502, 504, 506, 508 (whether lower edges at respective lower corners or upper edges at respective upper corners) may be parallel to each other on corresponding sides, such that any dimension or distance described with respect to a given edge may likewise refer to any other edge of the sloping sidewalls 502, 504, 506, 508.

[0056] The lateral dimension L of the metal via 704 V is smaller than the lateral distance L of the inclined side wall 506 D2 In some examples, the lateral distance L of the inclined sidewall 506 is D2 is the lateral dimension L of the metal via 704 V at least twice (e.g., three times) of . Figure 8 The benefit of a larger landing area is illustrated. A larger landing area allows for greater misalignment tolerance for the photolithography process that forms the opening to the lower capacitor conductive layer 314 for forming the metal via 704. Figure 8 As shown in FIG. 7 (relative to FIG. 7 ), the metal via 704 is formed to have a misalignment distance Δ V Due to the inclined sidewall 506, the misalignment distance Δ V Can be larger.

[0057] Fig. 9906 is a scanning electron microscope (SEM) image of a capacitor structure formed according to some examples. The capacitor structure includes a first silicon oxide layer 902, a first titanium nitride layer 904, a second silicon oxide layer 906, and a second titanium nitride layer 908. A photoresist 910 is above the second titanium nitride layer 908. The first silicon oxide layer 902 has a sloping sidewall forming an angle of 14.6° and a lateral distance of 579nm. The first titanium nitride layer 904 has a sloping sidewall forming an angle of 16.4° and a lateral distance of 319nm. The second silicon oxide layer 906 has a sloping sidewall forming an angle of 4.7° and a lateral distance of 1.380μm. The second titanium nitride layer 908 has a sloping sidewall forming an angle of 15.6° and a lateral distance of 423nm. In other examples with other angles and lateral distances, other materials may be implemented.

[0058] Fig.10 1000 is a block diagram of a processor-based system 1000 according to some examples. The processor-based system 1000 may be or include a computer, a server, a programmable logic controller (PLC), etc. or a combination thereof. The processor-based system 1000 may be implemented as a controller 180 or any other processor-based system to implement any operations described herein. The processor-based system 1000 includes one or more processors 1002, a memory system 1012, a communication bus 1022, one or more input / output (I / O) interfaces 1032, and a network interface 1042.

[0059] Each processor 1002 may include one or more processor cores 1004. Each processor 1002 and / or processor core 1004 may be, for example, a hardened processor such as a central processing unit (CPU), a reduced instruction set computing (RISC) processor, a complex instruction set computing (CISC) processor, a graphics processing unit (GPU), a digital signal processor (DSP), an application specific integrated circuit (ASIC), etc. or a combination thereof, or a soft processor implemented on programmable logic, such as a field programmable gate array (FPGA).

[0060] The memory system 1012 includes one or more memory controllers 1014 and memory 1016. The memory controller 1014 is configured to control read and / or write access to a specific memory 1016 or a subset of the memory 1016. The memory 1016 may include main memory, disk storage, or any suitable combination thereof. The memory 1016 may include any type of volatile or non-volatile memory, such as dynamic random access memory (DRAM), static random access memory (SRAM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory, solid-state storage, etc. The memory 1016 is a non-transitory machine-readable storage medium. Instructions 1018 are stored in the memory 1016. The instructions 1018 may be machine executable code (e.g., machine code) and may include firmware, software, programs, applications, or other machine executable code. The instructions 1018 may, for example, embody a software module 1020 that, when executed by the one or more processors 1002, performs the various functionalities and operations described herein. For example, the instructions 1018 may embody a software module 1020 that, when executed by the one or more processors 1002, controls the semiconductor processing tool 100 to perform the etching of block 208, among other things.

[0061] The one or more I / O interfaces 1032 are configured to be electrically and / or communicatively coupled to one or more I / O devices 1034. The I / O devices 1034 include the base 112, the power supplies 128, 134, and the mass flow controllers 160-166. Other example I / O devices 1034 include a keyboard, a mouse, a display device, a printer, etc. The one or more I / O interfaces 1032 may include connectors or coupling circuitry, such as industrial application connections, universal serial bus (USB) connections, high-definition multimedia interface (HDMI) connections, Circuit system, etc.

[0062] The network interface 1042 is configured to be communicatively coupled to the network 1044. The network interface 1042 may include circuitry for wired communication, such as an Ethernet connection, and / or may include circuitry for wireless communication, such as a wireless communication. Communicative Circuitry. For example, one or more computers and / or servers communicatively coupled to the network 1044 may transmit recipes, process conditions, etc. to the processor-based system 1000 via the network 1044 and the network interface 1042.

[0063] The communication bus 1022 is communicatively connected to one or more processors 1002, the memory system 1012, one or more I / O interfaces 1032, and a network interface 1042. The various components may communicate with each other via the communication bus 1022. The communication bus 1022 may control the flow of communications, for example, by including an arbitrator to arbitrate communications.

[0064] Although various examples have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the scope defined by the appended claims.

Claims

1. An integrated circuit IC, comprising: a semiconductor substrate having a top surface; A capacitor is provided over the semiconductor substrate, the capacitor having a capacitor stack, the capacitor stack comprising: a first capacitor conductive layer over the semiconductor substrate; a first capacitor dielectric layer overlying the first capacitor conductive layer, the first capacitor dielectric layer having a first dielectric sloped sidewall surface; and a second capacitor conductive layer overlying the first capacitor dielectric layer; an interconnect dielectric layer overlying the second capacitor conductive layer; and A metal via penetrates the interconnect dielectric layer and the first dielectric sloped sidewall surface of the first capacitor dielectric layer to reach the first capacitor conductive layer.

2. The IC of claim 1, wherein: The first dielectric sloped sidewall surface extends a lateral distance above the semiconductor substrate, the first dielectric sloped sidewall surface having a long lateral axis, the lateral distance being along a short lateral axis of the first dielectric sloped sidewall surface that is perpendicular to the long lateral axis; and The metal via has a via width at the first capacitor conductive layer, the via width is along the short horizontal axis, and the lateral distance is greater than the via width.

3. The IC of claim 2, wherein the lateral distance is at least twice the width of the via. 4 . The IC of claim 1 , wherein the second capacitor conductive layer has a conductive sloped sidewall surface having a bottom angle that meets a top angle of the first dielectric sloped sidewall surface.

5. The IC of claim 4, wherein: The first dielectric sloped sidewall surface has a first angle relative to the top surface of the semiconductor substrate; The conductive sloped sidewall surface has a second angle relative to the top surface of the semiconductor substrate; and The first angle is smaller than the second angle.

6. The IC of claim 5, wherein: The first angle is less than 10 degrees; and The second angle is greater than 10 degrees.

7. The IC of claim 4, wherein: the first dielectric sloped sidewall surface extending a first lateral distance above the semiconductor substrate; the conductive sloped sidewall surface extends a second lateral distance above the semiconductor substrate, the second lateral distance being laterally aligned with the first lateral distance; and The first lateral distance is at least twice the second lateral distance.

8. The IC of claim 1 , wherein the metal via is a first metal via, and the IC further comprises: a conductive layer over the semiconductor substrate; a second capacitor dielectric layer between the conductive layer and the first capacitor conductive layer; a second metal via extending through the interconnect dielectric layer to the conductive layer; and A third metal via extends through the interconnect dielectric layer to the second capacitor conductive layer, the second metal via being electrically connected to the third metal via.

9. The IC of claim 1, wherein the capacitor forms a circuit with an active device formed in or above the semiconductor substrate.

10. A method for manufacturing an integrated circuit IC, the method comprising: A capacitor is formed over a semiconductor substrate having a top surface, the capacitor having a capacitor conductive-dielectric stack, the capacitor conductive-dielectric stack comprising: a first conductive layer; a capacitor dielectric layer overlying the first conductive layer; and a second conductive layer over the capacitor dielectric layer, the forming comprising: etching the second conductive layer and the capacitor dielectric layer, thereby forming a sloped dielectric sidewall of the capacitor dielectric layer; forming an interconnect dielectric layer over the first conductive layer, the capacitor dielectric layer, and the second conductive layer; and A metal via is formed through the interconnect dielectric layer and the sloped dielectric sidewall to the first conductive layer.

11. The method of claim 10, further comprising patterning a photoresist layer over the capacitor conductive-dielectric stack using grayscale lithography, the patterned photoresist layer serving as a mask when etching the second conductive layer and the capacitor dielectric layer.

12. The method of claim 11, wherein etching the second conductive layer comprises: A ratio of an etch rate of the second conductive layer to an etch rate of the capacitor dielectric layer is in a range of 1:1 to 10:1; and A ratio of the etch rate of the second conductive layer to an etch rate of the patterned photoresist layer is in a range of 1:1 to 3:

1.

13. The method of claim 11, wherein etching the second conductive layer comprises an etch rate of the capacitor dielectric layer that is equal to or greater than each of etch rates of the patterned photoresist layer and equal to or less than an etch rate of the second conductive layer.

14. A method for semiconductor processing, the method comprising: A capacitor stack is formed over a top surface of a semiconductor substrate, the capacitor stack comprising: a first conductive layer over the semiconductor substrate; a dielectric layer overlying the first conductive layer; and a second conductive layer overlying the dielectric layer; patterning a photoresist layer over the capacitor stack using grayscale lithography, thereby forming a patterned photoresist layer over the second conductive layer, the patterned photoresist layer having a sloped sidewall forming an angle less than 60° with respect to the top surface; and The capacitor stack is etched using the patterned photoresist layer as a mask, the etching comprising forming a plasma using a gas mixture including chlorine (Cl2) gas, boron chloride (BCl3) gas, argon (Ar) gas and nitrogen (N2) gas, a source power and a bias power, wherein the bias power is at least one tenth of the source power.

15. The method of claim 14, wherein the flow rate of the Cl2 gas is in the range of 5 standard cubic centimeters (sccm) to 150 sccm, the flow rate of the BCl3 gas is in the range of 5 sccm to 70 sccm, the flow rate of the Ar gas is in the range of 5 sccm to 150 sccm, and the flow rate of the N2 gas is in the range of 5 sccm to 150 sccm.

16. The method of claim 15, wherein: The source power is in the range of 0.5 kilowatts (kW) to 2 kW; and The bias power is in the range of 50W to 250W.

17. The method of claim 16, wherein the etching is performed at a pressure of less than 15 mtorr (about 2 Pascals (Pa)).

18. The method of claim 14, wherein a flow rate of the Cl2 gas is about 15 sccm, a flow rate of the BCl3 gas is about 15 sccm, a flow rate of the Ar gas is about 50 sccm, and a flow rate of the N2 gas is about 10 sccm.

19. The method of claim 18, wherein: The source power is about 1 kW; and The bias power is about 150W.

20. The method of claim 19, wherein the etching is performed at a pressure of 8 mtorr (1.0667 Pa).

21. The method of claim 14, wherein: The first conductive layer comprises titanium nitride; The dielectric layer comprises silicon oxide, silicon nitride, hafnium oxide, or a combination thereof; and The second conductive layer includes titanium nitride.

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