A preparation method of a trench-gate SiC MOSFET for reducing the gate oxide electric field

Abstract

The present invention relates to the field of semiconductor technology, and particularly to a preparation method of a trench-gate SiC MOSFET for reducing the gate oxide electric field. In this preparation method, the source electrode is made into an inclined trench, and then P-type doping is injected to form an inclined P-well shielding region. The inclined shielding region can not only shield the electric field to reduce the peak electric field at the bottom of the gate oxide, but also guide the current to flow obliquely downward, improving the utilization rate of the second epitaxial layer; the first electric field absorption layer and the second electric field absorption layer utilize different directions of the same mask, saving the number of masks, and the electric field absorption layer can further reduce the peak electric field at the bottom of the gate oxide layer and can also reduce the saturation current density of the device without increasing the on-resistance, improving the short-circuit tolerance of the device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a method for manufacturing a trench-gate SiC MOSFET that reduces the gate oxide electric field. Background Art

[0002] As a third-generation semiconductor material, silicon carbide (SiC) has many advantages such as a large bandgap, high melting point, low dielectric constant, high breakdown field strength, high saturated electron drift velocity, high thermal conductivity, and stable chemical properties. Compared with conventional silicon devices under the same voltage, SiC power devices can have a higher doping concentration and a thinner drift layer thickness, thereby achieving a lower on-resistance.

[0003] Some problems have emerged in the application of trench gates in SiC MOSFETs. When the device is reverse-biased, an electric field spike appears at the bottom of the gate oxide, resulting in a decrease in the breakdown reliability at the bottom of the gate oxide. In the latest technologies, methods for reducing the electric field at the bottom of the gate oxide include, for example, in patent CN116759454A, using a P well to surround one side of the gate trench to shield the electric field; for example, in patent CN116936620A, using an epitaxial P layer to surround both sides of the gate trench and setting up a current channel; for example, in patent CN117894802A, designing an array of P buried layers; for example, in patent CN116072710B, designing an epitaxial layer part P buried layer and a P buried layer under the gate; for example, in patent CN116344588A, designing a P buried layer at the epitaxial layer; for example, in patent CN117174756A, designing multiple P shielding regions under the gate and under the P-type base region; for example, in patent US9761706B2, designing a P-type buried layer in the epitaxial layer; for example, in patent US11367775B1, using the method of alternating epitaxial implantation to design a very deep P-type shielding layer; for example, in patent US11600701B2, using a P well to surround the bottom of the gate trench; and the present invention uses different directions of the same mask to perform multiple epitaxial growths and implantations to form multiple layers of staggered electric field absorption layers, and also injects P-type doping into the inclined source trench to form an inclined P well shielding region, avoiding the injection of high-energy ions. The above operations greatly reduce the peak electric field at the bottom of the gate oxide, improve the device reliability, and reduce the saturation current density while keeping the on-resistance unchanged, improving the device short-circuit withstand capacity. Summary of the Invention

[0004] The object of the present invention is to provide a method for manufacturing a trench-gate SiC MOSFET that reduces the gate oxide electric field, which is used to solve the problem of the electric field spike appearing at the bottom of the gate oxide in the trench-gate structure, and reduces the device saturation current density and improves the device short-circuit withstand capacity.

[0005] The technical solution of the present invention is realized as follows:

[0006] A preparation method of a trench-gate SiC MOSFET for reducing the gate oxide electric field, comprising: growing an epitaxial layer on a semiconductor substrate to form a first epitaxial layer, and then performing P-type doping under the block of an electric field absorption layer mask to form a first electric field absorption layer; growing an epitaxial layer on the first epitaxial layer to form a second epitaxial layer, then rotating the electric field absorption layer mask by 90°, and performing P-type doping under the block of the electric field absorption layer mask to form a second electric field absorption layer; growing an epitaxial layer on the second epitaxial layer to form a third epitaxial layer, performing P-type doping on the third epitaxial layer to form a P-type base region, and performing N-type heavy doping on the third epitaxial layer to form an N+ source region; performing trench etching under the block of a source trench mask to form an inclined source trench, and then performing P-type heavy doping to form an inclined P-well shielding region; performing trench etching under the block of a gate trench mask to form a gate trench, growing gate oxide on the inner surface of the gate trench, then grinding a part of the upper surface layer of the gate trench mask, and performing polysilicon deposition after grinding; removing the redundant polysilicon, then performing field oxide growth, then removing the redundant field oxide, and then performing source ohmic contact region deposition and drain ohmic contact region deposition.

[0007] Optionally, the first electric field absorption layer and the second electric field absorption layer are vertically stacked and do not contact each other.

[0008] Optionally, the implantation energy of the P-type base region is higher than that of the N+ source region, that is, the junction depth of the P-type base region is deeper than that of the N+ source region, and the concentration of the N+ source region is higher than that of the P-type base region.

[0009] Optionally, the junction depth of the inclined P-well shielding region is deeper than that of the gate trench.

[0010] Optionally, the semiconductor substrate is an N-type heavily doped silicon carbide substrate.

[0011] The beneficial effects of the present invention are as follows:

[0012] In the present invention, the source electrode is made into an inclined trench, and then P-type doping is injected to form an inclined P-well shielding region. The inclined shielding region can not only shield the electric field to reduce the peak electric field at the bottom of the gate oxide, but also guide the current to flow obliquely downward, improving the utilization rate of the second epitaxial layer; the first electric field absorption layer and the second electric field absorption layer utilize different directions of the same mask, saving the number of masks, and the electric field absorption layer can further reduce the peak electric field at the bottom of the gate oxide layer and can also reduce the saturation current density of the device without increasing the on-resistance, improving the short-circuit tolerance of the device. Description of the Drawings

[0013] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0014] Figure 1 It is a schematic structural diagram after the formation of the first electric field absorption layer in step S01 of Embodiment 1 of the present invention;

[0015] Figure 2 It is a schematic structural diagram after the formation of the second electric field absorption layer in step S02 of Embodiment 1 of the present invention;

[0016] Figure 3 It is a schematic structural diagram after the formation of the P-type base region and the N+ source region in step S03 of Embodiment 1 of the present invention;

[0017] Figure 4 It is a schematic structural diagram after the inclined source trench etching in step S04 of Embodiment 1 of the present invention;

[0018] Figure 5 It is a schematic structural diagram after the gate trench etching in step S05 of Embodiment 1 of the present invention;

[0019] Figure 6 It is a schematic structural diagram of the gate oxide and polysilicon growth in step S06 of Embodiment 1 of the present invention;

[0020] Figure 7 It is a schematic structural diagram of the field oxide growth in step S06 of Embodiment 1 of the present invention;

[0021] Figure 8 It is a schematic structural diagram after the deposition of the source ohmic contact region and the drain ohmic contact region in step S06 of Embodiment 1 of the present invention;

[0022] Figure 9 It is a schematic diagram of the trench gate structure described in the embodiment of the present invention;

[0023] Figure 10 It is a schematic structural diagram after steps S01 and S02 of Embodiment 1 of the present invention are alternately performed multiple times.

[0024] Reference numerals of the drawings:

[0025] 1 - Semiconductor substrate; 2 - First epitaxial layer; 3 - Electric field absorption layer mask; 4 - First electric field absorption layer; 5 - Second epitaxial layer; 6 - Second electric field absorption layer; 7 - Third epitaxial layer; 8 - P-type base region; 9 - N+ source region; 10 - Source trench mask; 11 - Oblique source trench; 12 - Oblique P-well shielding region; 13 - Gate trench mask; 14 - Gate trench; 15 - Gate oxide; 16 - Polysilicon; 17 - Field oxide; 18 - Source ohmic contact region; 19 - Drain ohmic contact region. Detailed implementation mode

[0026] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments.

[0027] In the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", "front", "rear", "left", "right", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention.

[0028] Embodiment 1:

[0029] This embodiment is used to provide a preparation method for a trench-gate SiC MOSFET that reduces the gate oxide electric field, including:

[0030] Step S01: As Figure 1 shown, grow an epitaxial layer on the semiconductor substrate 1. The semiconductor substrate 1 is an N-type heavily doped silicon carbide substrate, form the first epitaxial layer 2, and then perform P-type doping under the block of the electric field absorption layer mask 3 to form the first electric field absorption layer 4;

[0031] Step S02: As Figure 2 shown, grow an epitaxial layer on the first epitaxial layer 2 to form the second epitaxial layer 5, then rotate the electric field absorption layer mask 3 by 90°, and perform P-type doping under the block of the electric field absorption layer mask 3 to form the second electric field absorption layer 6. The first electric field absorption layer 4 and the second electric field absorption layer 6 are longitudinally stacked and do not contact each other;

[0032] Step S03: As Figure 3As shown, an epitaxial layer is grown on the second epitaxial layer 5 to form a third epitaxial layer 7. P-type doping is performed on the third epitaxial layer 7 to form a P-type base region 8. N-type heavy doping is performed on the third epitaxial layer 7 to form an N+ source region 9. The implantation energy of the P-type base region 8 is higher than that of the N+ source region 9, that is, the junction depth of the P-type base region 8 is deeper than that of the N+ source region 9, and the concentration of the N+ source region 9 is higher than that of the P-type base region 8;

[0033] Step S04: As Figures 4-5 shown, under the block of the source trench mask 10, trench etching is performed to form an inclined source trench 11. Then, P-type heavy doping is performed to form an inclined P-well shielding region 12;

[0034] Step S05: As Figure 5 shown, under the block of the gate trench mask 13, trench etching is performed to form a gate trench 14, and gate oxide 15 is grown on the inner surface of the gate trench 14. Then, a part of the upper surface layer of the gate trench mask 13 is polished, and polysilicon 16 is deposited after polishing. Secondly, it should be noted that the junction depth of the inclined P-well shielding region 12 is deeper than that of the gate trench 14;

[0035] Step S06: As Figures 6-9 shown, the redundant polysilicon 16 is removed, then field oxide 17 is grown, then the redundant field oxide 17 is removed, and then source ohmic contact region 18 deposition and drain ohmic contact region 19 deposition are performed.

[0036] Secondly, in this embodiment, as Figure 10 shown, steps S01 and S02 can be repeated as needed, that is, epitaxy and electric field absorption layer implantation are alternately performed to obtain a stack of multiple electric field absorption layers, improving the electric field at the bottom of the device gate oxide. And only one mask is involved in steps S01 and S02, only the direction of the mask is changed, greatly saving the number of masks.

[0037] The above is only a preferred specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention, according to the technical solution and inventive concept of the present invention, makes equivalent substitutions or changes, and should be covered by the protection scope of the present invention.

Claims

1. A method for preparing a trench gate SiC MOSFET for reducing gate oxide electric field, characterized in that: include: Growing an epitaxial layer on a semiconductor substrate (1) to form a first epitaxial layer (2), and then performing P-type doping under the blocking of an electric field absorption layer mask (3) to form a first electric field absorption layer (4); Growing an epitaxial layer on the first epitaxial layer (2) to form a second epitaxial layer (5), then rotating the electric field absorption layer mask (3) by 90 degrees, and performing P-type doping under the blocking of the electric field absorption layer mask (3) to form a second electric field absorption layer (6); Growing an epitaxial layer on the second epitaxial layer (5) to form a third epitaxial layer (7), performing P-type doping on the third epitaxial layer (7) to form a P-type base region (8), and performing N-type heavy doping on the third epitaxial layer (7) to form an N+ source region (9); Performing trench etching under the blocking of the source trench mask (10) to form an inclined source trench (11), and then performing P-type heavy doping to form an inclined P-well shielding region (12); Performing trench etching under the blocking of the gate trench mask (13) to form a gate trench (14), growing gate oxide (15) on the inner surface of the gate trench (14), then grinding a portion of the upper surface layer of the gate trench mask (13), and depositing polysilicon (16) after grinding; Removing excess polysilicon (16), then growing field oxygen (17), then removing excess field oxygen (17), and then depositing a source ohmic contact region (18) and a drain ohmic contact region (19); The first electric field absorption layer (4) and the second electric field absorption layer (6) are overlapped in the longitudinal direction and do not contact each other, and the extension direction of the first electric field absorption layer is the same as the extension direction of the gate trench.

2. The method for preparing a trench gate SiC MOSFET for reducing gate oxide electric field according to claim 1, characterized in that: The injection energy of the P-type base region (8) is higher than that of the N+ source region (9), that is, the junction depth of the P-type base region (8) is deeper than that of the N+ source region (9), and the concentration of the N+ source region (9) is higher than that of the P-type base region (8).

3. The method for preparing a trench gate SiC MOSFET with reduced gate oxide electric field according to claim 1, characterized in that: The junction depth of the inclined P-well shielding region (12) is deeper than that of the gate trench (14).

4. The method for preparing a trench gate SiC MOSFET with reduced gate oxide electric field according to claim 1, characterized in that: The semiconductor substrate (1) is an N-type heavily doped silicon carbide substrate.

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