Chip, preparation method thereof and electronic equipment

Abstract

The invention provides a chip, a preparation method thereof and electronic equipment, relates to the technical field of electronics, and is convenient for improving the nanowire width uniformity of a nanowire device in the chip, reducing the nanowire width and improving the performance of the chip by utilizing an existing semiconductor device integration process. The chip comprises a substrate and at least one nanowire located on the substrate, and the substrate comprises a first surface and a second surface which are opposite in the thickness direction of the substrate; the second surface is provided with a step, the step comprises a first step surface, a second step surface and a first side surface connected with the first step surface and the second step surface, and the first step surface is lower than the second step surface relative to the first surface; the nanowires comprise first nanowires, and the first nanowires extend from the first step surface to the second step surface through the first side surface. The chip can be used for sensing, logic operation or information storage.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to a chip and a method for preparing the same, and an electronic device. Background Art

[0002] Semiconductor materials are the core of the modern microelectronics industry and dominate the field of microelectronics and optoelectronic devices. In recent years, with the development of informatization and intelligence, nanodevices have received extensive attention and research. Among them, semiconductor nanomaterials are increasingly valued because they are compatible with modern microelectronics processes and have unique electrical and optical properties. Semiconductor nanowires have broad application prospects in electronic devices, optical devices, various sensors, energy storage, etc.

[0003] For example, in the field of electronic devices, with the rapid development of large-scale integrated circuit technology, the number of transistors integrated on a single chip has increased dramatically, and the characteristic size of transistors has continued to decrease. In order to further improve chip integration and transistor performance, it is necessary to further develop nano devices, such as fin field effect transistors. On the basis of fin field effect transistors, in order to obtain better gate control characteristics and smaller subthreshold swing, a ring gate structure (gate all around, GAA) transistor has been developed. Nanowire structure has unique advantages in the preparation of GAA structure.

[0004] When silicon nanowires are used as channels for GAA transistors, in order to ensure reliable device performance, the nanowire line width is usually low, generally less than 30nm. In the case of limited high-precision lithography processes, the scheme of etching ultra-fine nanowire structures on silicon wafers using lithography and etching processes is difficult to implement and expensive. Silicon nanowire arrays can be prepared at low cost through various growth methods based on chemical synthesis processes, but due to the lack of effective means to control the line width of nanowires, the growth of thick nanowires in the nanowire array cannot be avoided, which ultimately affects the performance of GAA transistors. Therefore, it is urgent to develop a technology that can prepare silicon nanowire arrays with thin line widths and good line width uniformity. Summary of the invention

[0005] The embodiments of the present application provide a chip and a method for preparing the same, and an electronic device, which are used to solve the problems of difficulty in preparing thinner nanowires and low uniformity of nanowire width in existing nanowire devices (ie, devices made using nanowires).

[0006] To achieve the above purpose, this embodiment adopts the following technical solutions:

[0007] In a first aspect, a chip is provided, comprising a substrate and at least one nanowire located on the substrate, wherein the substrate comprises a first surface and a second surface opposite to each other in a thickness direction of the substrate; the second surface has a step step, the step step comprises a first step surface, a second step surface and a first side surface connecting the first step surface and the second step surface, and relative to the first surface, the first step surface is lower than the second step surface; the nanowire comprises a first nanowire, and the first nanowire extends from the first step surface to the second step surface via the first side surface.

[0008] The chip provided in this embodiment includes a nanowire device, and the performance of the chip can be improved by reducing the line width of the nanowire and improving the uniformity of the line width of the nanowire. A step step is provided on the second surface of the chip substrate, and the step step includes a first step surface, a second step surface and a first side surface. In the thickness direction of the substrate, the first step surface is lower than the second step surface, and the first side surface is used to connect the first step surface and the second step surface. When growing nanowires, a catalytic metal belt with a direction perpendicular to the arrangement direction of the first step surface and the second step surface is deposited on the first step surface. After the catalytic metal droplet is formed on the catalytic metal belt, an amorphous semiconductor film is deposited on the second surface of the substrate. Since the first side surface has a large inclination angle (for example, the inclination angle is 90 degrees, that is, the first side surface is perpendicular to the first step surface), the thickness of the amorphous semiconductor film deposited on the first side surface is less than the first step surface and the second step surface. Therefore, when the nanowire grows, if the line width of the nanowire is large, it is difficult for the catalytic metal droplet to absorb enough atoms of the amorphous semiconductor film on the first side surface, and the growth of the nanowire cannot be maintained. On the contrary, if the line width of the nanowire is small, the nanowire can continue to grow to the second step surface on the first side surface. Thus, the step steps are set to select the nanowire width, and only nanowires with a width less than the set value can be formed on the second step surface. In addition, since the nanowire width is screened, the uniformity of the width is also improved. Using these nanowires to form nanowire devices is conducive to reducing the size of the device, thereby increasing the integration of the chip and improving the performance of the chip.

[0009] In a possible implementation of the first aspect, the chip includes a plurality of nanowires, the plurality of nanowires include a second nanowire located on the substrate, the second nanowire is located on the first step surface, or, is located on the first step surface and the first side surface, but is not located on the second step surface. The second nanowire is a nanowire with a larger line width, and the first side surface cannot provide enough amorphous semiconductor film atoms for the second nanowire, so the second nanowire is only located on the first step surface and / or the first side surface.

[0010] In a possible implementation of the first aspect, the line width of the first nanowire is smaller than the line width of the second nanowire. Since the first nanowire can grow from the first step surface across the first side surface to the second step surface, while the second nanowire cannot, it can be determined that the line width of the first nanowire is smaller than the line width of the second nanowire.

[0011] In a possible implementation of the first aspect, the chip includes a plurality of nanowires, and the plurality of nanowires are all first nanowires, that is, all grown nanowires have relatively thin line widths and can all grow on the second step surface.

[0012] In a possible implementation of the first aspect, the second surface of the substrate further has a guide step, the guide step includes a first guide surface, a second guide surface and a second side surface connecting the first guide surface and the second guide surface, relative to the first surface, the first guide surface is lower than the second guide surface; the first guide surface has a step step; the first guide surface and the second guide surface are arranged along the first direction, the first step surface and the second step surface are arranged along the second direction, the first direction and the second direction are both parallel to the first surface, and the first direction and the second direction intersect. In this way, when the catalytic metal droplets are formed, the catalytic metal droplets will tend to form at the boundary line between the second side surface and the first guide surface, and the nanowires formed by the catalytic metal droplets absorbing the atoms of the amorphous semiconductor film will also be along the boundary line, thereby guiding the growth of the nanowires, making the arrangement of the nanowires regular, and facilitating the integration of nanowire devices.

[0013] In a possible implementation manner of the first aspect, the nanowire is located at a boundary line between the second side surface of the guide step and the first guide surface.

[0014] In a possible implementation of the first aspect, along the first direction, the second side surface and the second guide surface are provided on both sides of the step step, and a nanowire is provided at each intersection of the step step and the second side surfaces on both sides. In this way, nanowires can be grown on both sides of a step step, thereby increasing the density of the nanowires and improving the integration of the nanowire device.

[0015] In a possible implementation of the first aspect, the second guide surface has a stepped step, and nanowires are also arranged on the stepped step of the second guide surface, thereby increasing the density of the nanowires and improving the integration of the nanowire device.

[0016] In a possible implementation of the first aspect, the guide step further includes at least one third guide surface, the first guide surface, the second guide surface and the at least one third guide surface are arranged along the first direction, and along the direction from the first guide surface to the second guide surface, the heights of the first guide surface, the second guide surface and the at least one third guide surface are successively increased; at least one third guide surface has a stepped step, and nanowires are also arranged on the stepped step of the third guide surface. In this way, the density of nanowires is increased and the integration of nanowire devices is improved.

[0017] In a possible implementation of the first aspect, the chip includes a plurality of stepped steps arranged at intervals, and the second step surfaces of the plurality of stepped steps are at the same height, so that the first nanowires grown on the second steps are all at the same height, which is beneficial to the integration of nanowire devices.

[0018] In a possible implementation of the first aspect, the chip includes a transistor, and the first nanowire forms a channel of the transistor. In this way, the nanowire width of the transistor is uniform, which can ensure on-off control of the transistor channel.

[0019] In a possible implementation of the first aspect, a channel of a transistor includes multiple nanowires, and at least one of the multiple nanowires is a first nanowire. Thus, it can be ensured that at least one of the nanowires constituting the transistor channel is effective, that is, the effectiveness of the transistor is ensured.

[0020] In a possible implementation of the first aspect, the size of the first step surface in the second direction is smaller than the size of the second step surface in the second direction. In this way, the area of ​​the second step surface in the whole chip accounts for a larger proportion, and the area of ​​the first step surface in the whole chip accounts for a smaller proportion. Since only nanowires with a thinner line width (i.e., the first nanowire) can grow on the second step surface, it is inclined to integrate nanowire devices on the second step surface. Thereby increasing the area proportion of the second step surface in the whole chip, the integration of nanowire devices can be improved.

[0021] In a possible implementation of the first aspect, the first step surface is 30nm-80nm lower than the second step surface. The height of the first step surface lower than the second step surface will affect the quantity and quality of the first nanowires. Thus, selecting a suitable height can improve the quantity and quality of the first nanowires.

[0022] In a second aspect, the present application provides a method for preparing a chip, comprising: providing a substrate, the substrate comprising a first surface and a second surface opposite to each other in a thickness direction of the substrate; forming a step step on the second surface, the step step comprising a first step surface, a second step surface and a first side surface connecting the first step surface and the second step surface, wherein the first step surface is lower than the second step surface relative to the first surface; forming catalytic metal droplets on the first step surface; forming an amorphous semiconductor film on the second surface; annealing the substrate so that the catalytic metal droplets absorb amorphous silicon to grow on the step step to form at least one nanowire; the nanowire comprises a first nanowire, and the first nanowire extends from the first step surface via the first side surface to the second step surface.

[0023] In the chip preparation method provided in this embodiment, a step step is formed on the second surface of the substrate. The step step can realize the selection of the line width of the nanowire and screen out the nanowires with a line width less than the set value. Therefore, nanowires with thinner line width and better uniformity can be obtained.

[0024] In a possible implementation of the second aspect, before the step step is formed on the second surface, it also includes: forming a guide step on the second surface, the guide step includes a first guide surface, a second guide surface and a second side surface connecting the first guide surface and the second guide surface, relative to the first surface, the first guide surface is lower than the second guide surface; forming the step step on the second surface includes: forming a mask layer on the guide step, the mask layer includes a first opening, the first opening exposes part of the first guide surface; etching the first guide surface based on the mask layer, so that the height of the part of the first guide surface exposed by the first opening decreases, forming the step step; wherein the first guide surface and the second guide surface are arranged along the first direction, the first step surface and the second step surface are arranged along the second direction, the first direction and the second direction are parallel to the first surface, and the first direction and the second direction intersect. In this way, the guide step is formed to guide the growth of the nanowires, so that the arrangement of the nanowires is regular, which is convenient for the integration of nanowire devices.

[0025] In a third aspect, the present application provides an electronic device, comprising the chip and a printed circuit board according to any one of the first aspects, wherein the chip is combined with the printed circuit board. Thus, since a chip with better performance is used, the performance of the electronic device can also be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 A schematic diagram of an electronic device provided in an embodiment of the present application;

[0027] Figure 2 A schematic diagram of a method for preparing nanowires in the related art;

[0028] Figure 3 Schematic diagram of the relationship between the diameter of the catalytic metal droplet and the width of the nanowire;

[0029] Figure 4 A partial schematic diagram of a chip provided in an embodiment of the present application;

[0030] Figure 5-Figure 6 Schematic diagram of nanowire growth;

[0031] Figure 7-Figure 10 Schematic diagram of the nanowire growth principle;

[0032] Fig.11 for Figure 5 A top view of the chip in FIG.

[0033] Fig.12 for Figure 5 Schematic diagram of the cross-sectional structure of the chip along the AA direction;

[0034] Fig.13 is a schematic cross-sectional structure diagram of a chip in another embodiment;

[0035] Fig.14 A partial schematic diagram of another chip provided in an embodiment of the present application;

[0036] Fig.15 A flowchart of a method for preparing a chip provided in an embodiment of the present application;

[0037] Figure 16-Figure 27 A schematic diagram of the chip structure corresponding to each step in the chip preparation method provided in the embodiment of the present application. DETAILED DESCRIPTION

[0038] Unless otherwise defined, the technical terms or scientific terms used in this application should be understood by those skilled in the art in the ordinary sense. The terms "first", "second", "third" and similar words used in the specification and claims of this application do not indicate any order, quantity or importance, but are only used to distinguish different components. Thus, the features defined as "first", "second", and "third" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, unless otherwise stated, the meaning of "multiple" is two or more.

[0039] The directional terms such as "left", "right", "up" and "down" are defined relative to the orientation of the device schematically placed in the drawings. It should be understood that these directional terms are relative concepts. They are used for relative description and clarification, and they may change accordingly according to the change of the orientation of the chip or semiconductor packaging structure.

[0040] The present application provides an electronic device, which is a type of electronic device with a chip, which can be used for sensing, data storage and / or logical operations, etc. For example, a mobile phone, a tablet computer, a smart bracelet, a personal computer (PC), a server, a workstation, a vehicle-mounted device, etc.

[0041] See also Figure 1 , Figure 1 A schematic diagram of an electronic device 10 is provided in an embodiment of the present application. The electronic device 10 may be a terminal device. The electronic device 10 includes a printed circuit board (PCB) 11, on which a bus 12 and a chip connected to the bus 12 are arranged.

[0042] Please continue to see Figure 1, an embodiment of the present application also provides a chip.

[0043] In some embodiments, the chip may be a system on chip (SoC) 13. The system on chip 13 may be used to process data, such as processing application data, processing image data, and caching temporary data. The system on chip 13 may include an application processor (AP) 13a for processing applications, a graphics processing unit (GPU) 13b for processing image data, a first memory 13c for caching high-speed data, or a sensor 13d for acquiring information. The first memory 13c may be a static random access memory (SRAM) or an embedded flash (EFlash), etc.

[0044] The chip may specifically be the above-mentioned application processor 13a, image processing unit 13b, first memory 13c or sensor 13d. The application processor 13a, image processing unit 13b, first memory 13c and sensor 13d may be integrated into one die, or may be combined or separately arranged in multiple dies.

[0045] In some embodiments, the chip may be a second memory 14, which is also disposed on a printed circuit board and electrically connected to the printed circuit board. Specifically, the second memory 14 is connected to the system on chip 13 via a bus 12. The second memory 14 may be a dynamic random access memory (DRAM). The second memory 14 may be used to store volatile data, such as temporary data generated by the system on chip 13. The storage capacity of the second memory 14 is generally greater than that of the first memory 13c.

[0046] In some implementations, the chip may also be a communication chip 15 or a power management chip 16, and the communication chip 15 and the power management chip 16 are connected to the system on chip 13 via the bus 12. The communication chip 15 may be used for processing the protocol stack, or for amplifying and filtering analog radio frequency signals, or for realizing the above functions simultaneously. The power management chip 16 may be used for powering other chips.

[0047] It is understandable that the present application does not limit the type of the chip. However, the chip includes nanowire devices formed by nanowires, such as the channel of the chip transistor is a nanowire, and the sensing component of the sensor is composed of nanowires.

[0048] like Figure 2As shown, Figure 2 This is a method for preparing nanowires in the related art. First, a catalytic metal droplet 201 is formed on the substrate, and solid powder, such as amorphous silicon powder, is vaporized at high temperature. The vaporized solid powder is transported to the substrate surface by a carrier gas, and the vaporized solid powder is dissolved in the catalytic metal droplet 201. After reaching saturation, it crystallizes and nucleates to form nanowires 202. The growth direction of the nanowire 202 is perpendicular to the upper surface / lower surface direction of the substrate. Because the nanowire 202 is perpendicular to the substrate surface, the nanowire is not compatible with the current device integration process.

[0049] Please continue to see Figure 3 In this method, the nanowires 202 grown by the catalytic metal droplets 201 of different diameters have different line widths. To a certain extent, the diameter of the catalytic metal droplet 201 is positively correlated with the line width of the nanowire 202. The line width of the nanowire 202 refers to the maximum dimension of the nanowire 202 perpendicular to the growth direction of the nanowire 202. Therefore, this method mainly controls the line width of the nanowire 202 by reducing the diameter of the catalytic metal droplet 201. However, when preparing a high-density nanowire array, droplets with smaller diameters and close to each other will fuse in the early stage of the growth of the nanowire 202, and the volume will increase, catalyzing the growth of nanowires with excessively large line widths.

[0050] In order to obtain nanowires with thinner and uniform line width and prepare high-performance nanowire devices, the present application provides a chip.

[0051] like Figure 4 Shown is a partial schematic diagram of a chip provided by the present application.

[0052] The chip 100 includes a substrate 110 , which can be made of materials such as crystalline silicon, glass, aluminum foil, silicon nitride, silicon oxide, silicon carbide, sapphire, PI (polyimide) or PET (polyethylene terephthalate).

[0053] The substrate 110 includes a first surface 120 and a second surface 130. The first surface 120 and the second surface 130 are two surfaces opposite to each other in the thickness direction of the substrate 110. In some embodiments, the first surface 120 may be the bottom surface of the substrate 110, and the second surface 130 may be an upper surface opposite to the bottom surface.

[0054] For ease of description, we establish Figure 4 The XYZ coordinate system shown in FIG. 1 is a coordinate system in which the X direction and the Y direction are perpendicular to each other and form an XY plane, and the Z direction is perpendicular to the XY plane. The substrate 110 is disposed on the XY plane. Further, the first surface 120 of the substrate 110 can extend in the XY plane, and the Z direction is the thickness direction of the substrate 110.

[0055] A stepped step 140 is provided on the second surface 130 of the substrate 110, and the stepped step 140 includes a first step surface 141, a second step surface 142, and a first side surface 143, wherein the first side surface 143 connects the first step surface 141 and the second step surface 142. In other words, the first step surface 141, the second step surface 142, and the first side surface 143 are all part of the second surface 130.

[0056] The first step surface 141 and the second step surface 142 are arranged along the second direction D2. The second direction D2 may be parallel to the Y direction or may not be parallel to the Y direction. The following description will take the second direction D2 being parallel to the Y direction as an example.

[0057] The first side surface 143 and the first step surface 141 form a certain angle, such as being perpendicular to each other, or forming an acute angle or an obtuse angle. The connection between the first side surface 143 and the first step surface 141 can be smoothly transitioned through an arc surface, or the first side surface 143 and the first step surface 141 can directly intersect without a special transition structure. The connection between the first side surface 143 and the second step surface 142 can be similar to the connection between the first side surface 143 and the first step surface 141.

[0058] In the thickness direction of the substrate 110, i.e., in the Z direction, the first step surface 141 is lower than the second step surface 142, that is, the first step surface 141 is closer to the first surface 120 than the second step surface 142. On this basis, the first side surface 143 is an inclined surface relative to the first step surface 141 and the second step surface 142. When the first side surface 143 is perpendicular to the first step surface 141 and the second step surface 142, the first side surface 143 is a vertical surface.

[0059] It is easy to understand that the first surface 120, the second surface 130, the first step surface 141, the second step surface 142 and the first side surface 143 in the present application can be planes. However, the present application does not limit them to planes, for example, the first step surface 141 and the second step surface 142 are arc-shaped surfaces, and for another example, the second surface 130 has a step structure formed by the first step surface 141, the second step surface 142 and the first side surface 143.

[0060] The chip 100 further includes nanowires 150, which are used to form nanowire devices of the chip 100. For example, the nanowires 150 can be used as channels of transistors, or as sensing elements of biomolecular nanosensors integrated in the chip 100. In some embodiments, the nanowires 150 can be grown from materials such as amorphous silicon α-Si, amorphous germanium α-Ge, amorphous carbon α-C, or other amorphous alloy materials, as well as heterogeneous stacked layers (such as α-Ge / α-Si) structures.

[0061] The growth process of the nanowire 150 is described below by taking amorphous silicon α-Si grown silicon nanowire as an example.

[0062] like Figure 5-Figure 6 , which is a schematic diagram of the growth of nanowire 150.

[0063] Figure 5 is a side view of the nanowire growth. Figure 6 It is a top view of the growth of nanowires. Among them, the catalytic metal droplet 160 is formed on the substrate 110, and a layer of amorphous semiconductor thin film layer corresponding to the desired growth nanowire 150 is deposited on the surface of the substrate (i.e., the second surface), that is, when growing silicon nanowires, the amorphous semiconductor thin film layer 153 here is an amorphous silicon layer; the catalytic metal droplet 160 begins to absorb the surrounding molten amorphous silicon, and when the amorphous silicon absorbed by the catalytic metal droplet 160 is supersaturated, the catalytic metal droplet 160 will precipitate silicon crystal nuclei, and the precipitated crystal nuclei cause the surface of the catalytic metal droplet 160 to deform. However, the catalytic metal droplet 160 will always tend to maintain a shape with the minimum surface Gibbs free energy, thereby providing power for the growth of the nanowire 150.

[0064] Please continue to refer to Figure 7-Figure 10 , Figure 7-Figure 10 Schematic diagram of the nanowire growth principle.

[0065] like Figure 7 As shown, after the rear catalytic metal droplets 160 are formed, an amorphous silicon layer is deposited to cover the substrate 110 and the catalytic metal droplets 160 .

[0066] like Figure 8 As shown, when the substrate temperature is heated to a temperature higher than the eutectic point of the catalytic metal and amorphous silicon alloy, the catalytic metal droplet 160 begins to absorb the surrounding amorphous silicon, and after the silicon atoms at the interface of the catalytic metal and amorphous silicon reach an oversaturated state, crystalline silicon nano-nuclei 154 will precipitate at the interface. It is easy to understand that the nuclei 154 may precipitate in all directions of the catalytic metal droplet 160.

[0067] like Figure 9-10 As shown, since the catalytic metal droplet 160 may precipitate crystal nuclei 154 in all directions, the precipitated crystal nuclei 154 will cause the surface of the catalytic metal droplet to deform, thereby generating a force to move the catalytic metal droplet 160. Therefore, when the crystal nuclei 154 precipitated from the catalytic metal droplet 160 grow to a certain extent, the catalytic metal droplet 160 will move, thereby forming a new interface to continuously absorb amorphous silicon. The absorbed amorphous silicon will diffuse to the side of the precipitated crystal nuclei 154 due to the concentration difference, and continuously form silicon nanowires 150, thereby gradually growing silicon nanowires 150.

[0068] Figure 4In the chip shown, a step step 140 is provided in the growth direction of the nanowire 150, that is, in the second direction D2. In the process of preparing the nanowire 150, a layer of amorphous silicon is deposited on the substrate 110 on which the catalytic metal droplet 160 is formed. Due to the provision of the step step 140, the thickness of the amorphous silicon deposited on the first side surface 143 is smaller than the amorphous silicon on the first step surface 141 and the second step surface 142. When the nanowire 150 grows to the first side surface 143, if the line width of the grown nanowire 150 is large, and at the same time, since the thickness of the amorphous silicon on the first side surface 143 is lower than that on the first step surface 141 and the second step surface 142, the catalytic metal droplet 160 cannot absorb enough silicon atoms on the first side surface 143 to maintain the growth of the nanowire 150, resulting in the breakage of the nanowire 150, and thus the nanowire 150 cannot grow from the first step surface 141 to the second step surface 142. However, when the line width of the nanowire 150 is small, the silicon atoms absorbed by the catalytic metal droplet 160 on the first side surface 143 can maintain the growth of the nanowire 150, so that the nanowire 150 can grow across the first side surface 143 to the second step surface 142. Therefore, the line width of the nanowire 150 is selected by setting the stepped step 140, and the nanowire 150 can grow across the first side surface 143 on the second step surface 142 only when the line width is less than a certain size.

[0069] From the above growth process of the nanowire 150 , it can be seen that the grown nanowire 150 may include a first nanowire 151 and a second nanowire 152 , wherein the first nanowire 151 grows from the first step surface 141 to the second step surface 142 via the first side surface 143 , while the second nanowire 152 cannot grow on the second step surface 142 .

[0070] Specifically, in some embodiments, the diameter of the catalytic metal droplets 160 conforms to the normal distribution, that is, the diameter of the catalytic metal droplets 160 is not uniform. There may be some catalytic metal droplets 160 with smaller diameters, and the nanowires 150 grown from these catalytic metal droplets 160 have smaller line widths. The first side surface 143 can provide enough silicon atoms, and the nanowires 150 can cross the first side surface 143 and grow onto the second step surface 142. At this time, the nanowires 150 grown are first nanowires 151.

[0071] In some cases, there are some catalytic metal droplets 160 with larger diameters. The nanowires 150 grown from these catalytic metal droplets 160 have larger line widths and cannot grow beyond the first side surface 143 to the second step surface 142. At this time, the grown nanowires 150 are second nanowires 152. In other words, when the catalytic metal droplets 160 move to the first side surface 142, the absorbed atoms are not enough to maintain the growth of the nanowires 150, and the second nanowires 152 only grow on the first step surface 141, that is, the second nanowires 152 are only located on the first step surface 141.

[0072] In other cases, because the catalytic metal droplet 160 absorbs enough atoms on the first step surface 141, when the catalytic metal droplet 160 moves to the first side surface 142, although it cannot absorb enough atoms to maintain the line width of the growing second nanowire 152, the absorbed atoms can make the second nanowire 152 grow a certain distance on the first side surface 143. At this time, the second nanowire 152 is not only located on the first step surface 141, but also on the first side surface 143.

[0073] In the above two cases, since the absorbed atoms are not sufficient to support the second nanowire 152 to cross the first side surface 143 to reach the second step surface 142 , the second nanowire 152 is not located on the second step surface 142 .

[0074] Of course, it is easy to understand that in some other embodiments, catalytic metal droplets 160 with uniform diameter can be obtained, and the nanowires 150 grown by the catalytic metal droplets 160 can cross the first side surface 143 from the first step surface 141 and extend to the second step surface 142, that is, all nanowires 150 are first nanowires 151.

[0075] It can be seen that by setting the step steps 140, the line width of the nanowire 150 can be selected, and only the nanowire 150 with a smaller line width can cross the first side surface 143 from the first step surface 141 and extend to the second step surface 142, that is, the line width of the first nanowire 151 is smaller than the line width of the second nanowire 152.

[0076] Therefore, in order to obtain a nanowire device with uniform nanowire width, the nanowire device in the chip 100 can be integrated on the second step surface 142. Figure 4 , and please combine Fig.12 , Fig.12 for Figure 4 , when the nanowire device is a transistor 170, the nanowire serves as a channel of the transistor 170, and the transistor 170 is located on the second step surface 142, and the channel of the transistor is formed by the first nanowire 151. At this time, no transistor is formed on the first step surface 141. In order to increase the number of integrated transistors, the size of the first step surface 141 in the second direction D2 can be reduced. For example, in the second direction D2, the size of the first step surface 141 is smaller than the size of the second step surface 142.

[0077] In some embodiments, the size of the first step surface 141 in the second direction D2 may also be limited to, for example, 1 μm-10 μm.

[0078] However, it is easy to understand that when the performance of some devices is not sensitive to the line width of the nanowire, the nanowire device can also be integrated on the first step surface 141, or even the nanowire device can be made to span two or more of the first step surface 141, the first side surface 143, and the second step surface 142. For example, when the nanowire device is a transistor, the nanowire serves as the channel of the transistor, the transistor is located on the first step surface 141, and the channel of the transistor is the first nanowire 151 and / or the second nanowire 152.

[0079] See also Fig.11 , Fig.11 yes Figure 4 In some embodiments, since it cannot be guaranteed that all nanowires 150 can extend from the first step surface 141 to the second step surface 142, that is, the specific situation of the nanowires 150 grown on the substrate 110 is uncertain, there may be a second nanowire 152. Therefore, when forming a nanowire device, in order to avoid the nanowire device being invalid, one nanowire device can be made to span the expected growth area 156 of multiple nanowires 150, and the expected growth area 156 of the nanowire 150 includes the area covered by the first nanowire 151, or it is assumed that the second nanowire 152 crosses the first side surface 143 and extends to the area covered by the second step surface 142; that is, it is assumed that all nanowires 150 grown by the catalytic metal droplets 160 are the first nanowires 151, and the area covered by the first nanowire 151 is the expected growth area 156.

[0080] For example, the source 172, drain 173 and gate 171 of transistor 170 all span the expected growth regions 156 of multiple nanowires 150 in a direction perpendicular to the arrangement of the first step surface 141 and the second step surface 142, i.e., in the first direction D1. Since transistor 170 spans the expected growth regions 156 of multiple nanowires 150, it is guaranteed with a certain probability that there is at least one first nanowire 151 in transistor 170, ensuring that transistor 170 can operate normally. It can be seen that the probability here is not only related to the proportion of first nanowires 151 in the grown nanowires 150, but also to how many expected growth regions 156 of nanowires 150 the source 172, drain 173 and gate 171 of transistor 170 span. For example, the source 172, drain 173 and gate 171 of transistor 170 may span the expected growth regions 156 of 1-8 nanowires 150. Specifically, Fig.11 The source 172 , the drain 173 , and the gate 171 of the transistor 170 span across the expected growth regions 156 of the three nanowires 150 .

[0081] It can be understood that the number of nanowires 150 that the transistor 170 crosses directly affects the integration of the transistor 170. The fewer nanowires 150 that the transistor 170 crosses, the higher the integration; the more nanowires 150 that the transistor 170 crosses, the lower the integration. However, the fewer nanowires 150 that the transistor 170 crosses, the greater the possibility that the transistor 170 cannot work normally.

[0082] In some embodiments, whether the nanowire 150 can grow from the first step surface 141 across the first side surface 143 to the second step surface 142 is not only related to the line width of the grown nanowire 150, but also to the height of the step step 140. Since the number of atoms absorbed by the catalytic metal droplet 160 on the first side surface 143 is always less than the number of atoms on the first step surface 141 when the nanowire 150 is grown, when the height of the step step 140 is too high, the nanowire 150 cannot continue to grow after growing to a certain extent on the first side surface, or the force generated by the crystal nucleus precipitated by the catalytic metal droplet 160 on one side of the nanowire 150 is difficult to push the catalytic metal droplet 160 to move, and the catalytic metal droplet 160 cannot form a new interface with the deposited amorphous semiconductor film layer and absorb atoms to grow the nanowire 150. Therefore, the appropriate height of the step step 140 can be selected according to the line width of the first nanowire 151 to be prepared, for example, the height of the step step 140 is 30nm-80nm.

[0083] The above-mentioned “height of the step step 140” refers to the height difference between the second step surface 142 and the first step surface 141 of the step step 140 compared to the first surface 120 of the substrate. In the case where the first side surface 143 of the step step 140 is perpendicular to the first step surface 141 and the second step surface 142, the “height of the step step 140” is the dimension of the first side surface 143 in the thickness direction of the substrate 110, that is, the dimension along the direction Z.

[0084] In some embodiments, the catalytic metal droplet 160 may be lost during the process of growing the nanowire 150. Therefore, if the nanowire 150 grown by the same catalytic metal droplet 160 is too long, the diameter of the catalytic metal droplet 160 will become smaller due to the loss of the catalytic metal droplet 160. In other words, the line width of the same nanowire 150 will also change. In order to avoid this situation, a plurality of step steps 140 may be provided on the chip 100 along the arrangement direction (second direction D2) of the first step surface 141 and the second step surface 142. In other words, the plurality of step steps 140 are spaced apart along the arrangement direction of the first step surface 141 and the second step surface 142. In this way, the nanowire 150 can be grown in sections, limiting the length of each nanowire 150, thereby avoiding excessive changes in the line width when the nanowire 150 grows. For details, please continue to refer to Figure 4, the step steps 140 in the dotted frame S1 and the dotted frame S2 are arranged in the second direction D2, and the nanowire 151a on the step step 140 in the dotted frame S1 and the nanowire 151b on the step step 140 in the dotted frame S2 are grown in sections.

[0085] In some specific embodiments, the second step surfaces 142 of the plurality of step steps 140 are at the same height in the thickness direction of the substrate 110, that is, the second step surfaces 142 of the plurality of step steps 140 are equidistant from the first surface 120 of the substrate 110. Figure 4 In the embodiment, the distance d1 between one second step surface 142 and the first surface 120 of the substrate 110 is equal to the distance d2 between another second step surface 142 and the first surface 120 of the substrate 110. Therefore, when the nanowire 150 is used to form a nanowire device, it is easier to integrate.

[0086] In some specific embodiments, for two adjacent step steps among a plurality of step steps spaced apart along the arrangement direction (second direction D2) of the first step surface 141 and the second step surface 142, in order to prevent the nanowire 150 from growing from one step step 140 to another step step 140 during the growth process, when growing the nanowire 150, the growth length of the nanowire 150 can be controlled by limiting the growth time of the nanowire 150, thereby preventing the nanowire 150 from growing across a plurality of steps 140 along the arrangement direction (second direction D2) of the first step surface 141 and the second step surface 142.

[0087] In some embodiments, the growth length of the nanowire 150 may be limited by the structure of the stepped terrace 140 .

[0088] See also Fig.13 , Fig.13 1 is another cross-sectional structural diagram of the chip. Specifically, the structure for limiting the growth length of the nanowire 150 may be a limiting groove 144 formed on the side of the first step surface 141 away from the first side surface 143, and the limiting groove 144 is recessed from the second surface 130 to the first surface 120 in the thickness direction (Z direction) of the substrate 110, and the size of the recess in the thickness direction (Z direction) of the substrate 110 is greater than the height that the nanowire 150 can cross. When the nanowire 150 grows to a certain length, the catalytic metal droplet 160 will enter the limiting groove 144, and since the nanowire 150 cannot cross the limiting groove 144, the length of the nanowire is limited.

[0089] Please continue to see Fig.13In some embodiments, when the catalytic metal droplet 160 grows the nanowire 150, it is not possible to determine on which side of the catalytic metal droplet 160 the crystal nucleus will be precipitated, and it is not possible to determine in which direction the catalytic metal droplet 160 will move, that is, the growth direction of the nanowire 150 cannot be determined. If during the growth process, the growth direction of one nanowire 150 is opposite to the growth direction of another nanowire 150, this will cause the catalytic metal droplets 160 of the two nanowires 150 to merge into one catalytic metal droplet, and may stop growing, that is, the nanowire 150 is discontinuous, affecting the effectiveness of the nanowire device. However, after the limiting groove 144 is set, only the catalytic metal droplet 160 moving in the direction toward the first side 143 is allowed to grow to form a nanowire. If the catalytic metal droplet 160 moves in the direction away from the first side 143, the catalytic metal droplet 160 will enter the limiting groove 144, thereby interrupting the growth of the nanowire 150, that is, one nanowire 150 grows normally, and the other nanowire 150 does not grow.

[0090] The growth direction of the nanowire 150 is related to the direction of the crystal nuclei precipitated from the catalytic metal droplets 160 , but the direction of the crystal nuclei precipitated cannot be controlled, that is, the growth direction of the nanowire 150 is random. Therefore, the growth direction of the nanowire 150 needs to be controlled.

[0091] Please continue to see Figure 4 In some embodiments, in order to control the growth direction of the nanowire 150 and guide the growth of the nanowire 150, a guide step 180 is provided on the second surface 130 of the substrate 110. The guide step 180 includes a first guide surface 181, a second guide surface 182, and a second side surface 183, and in the thickness direction of the substrate 110, relative to the first surface 120, the first guide surface 181 is lower than the second guide surface 182, that is, the first guide surface 181 is closer to the first surface 120 than the second guide surface 182, wherein the step step 140 is provided on the first guide surface 181.

[0092] It can be understood that the size of the first side 143 in the thickness direction of the substrate 110 (i.e., the Z direction) is smaller than the size of the second side 183, that is, the height of the step step 140 is smaller than the height of the guide step 180, thereby ensuring that the nanowire 150 will not cross the second side 183 when growing the nanowire 150.

[0093] In order to ensure that the step step 140 plays a role in selecting the line width of the nanowire 150, the arrangement of the guide step 180 and the step step 140 needs to meet certain conditions. In a plane parallel to the first surface 120 of the substrate 110 (i.e., the XY plane), the direction in which the first guide surface 181 and the second guide surface 182 of the same guide step 180 are arranged is the first direction D1, and the first direction D1 intersects with the second direction D2, so as to simultaneously ensure the function of the guide step 180 in controlling the growth direction of the nanowire 150 and the function of the step step 140 in selecting the line width of the nanowire 150.

[0094] The intersection of the first direction D1 and the second direction D2 means that the first direction D1 is perpendicular to the second direction D2, or the first direction D1 and the second direction D2 intersect at an acute angle. The following description takes the perpendicularity of the first direction D1 and the second direction D2 as an example.

[0095] During the growth of the nanowire 150 guided by the guide step 180, the first guide surface 181 and the second side surface 183 are both covered with a layer of amorphous silicon, and the catalytic metal droplet contacts the first guide surface 181 and the second side surface 183 and moves. During the contact and movement process with the first guide surface 181 and the second side surface 183, there will be slight differences in the surface Gibbs free energy at different positions. This slight energy difference allows the catalytic metal droplet to grow along the guide step 180.

[0096] As the catalytic metal droplet contacts the first guide surface 181 and the second side surface 183 and moves, the grown nanowire 150 is located at the boundary line between the first guide surface 181 and the second side surface 183 , that is, the nanowire 150 is located at the boundary line between the step step 140 and the second side surface 183 .

[0097] In some embodiments, see Figure 4 In the first direction D1, the second side surface 183 and the second guide surface 182 are provided on both sides of the step step 140. It can also be understood that one step step 140 corresponds to two guide steps 180, and the second side surfaces 183 of the two guide steps 180 extend in the second direction D2 and intersect with the first step surface 141, the second step surface 142 and the first side surface 143 of the step step 140.

[0098] In some specific embodiments, the second side surfaces 183 disposed on both sides of the step step 140 may be parallel to each other. Thus, one step step 140 and two corresponding guide steps 180 may guide the growth of two nanowires 150, and the two nanowires 150 are respectively located at the boundary between the second side surface 183 and the step step 140.

[0099] Please continue to see Fig.14 , Fig.141 is a partial schematic diagram of another chip. In some embodiments, in order to increase the density of the growing nanowires 150 or make the growing nanowires 150 easier to form nanowire devices, the guide step 180 further includes a third guide surface 184. The number of the third guide surface 184 can be multiple or one. Figure 4 FIG. 1 shows only one third guide surface 184 . The third guide surface 184 may also be provided with a stepped step 140 .

[0100] The first guide surface 181, the second guide surface 182, and the third guide surface 184 are arranged in the first direction D1, and the first guide surface 181 and the third guide surface 184 are connected through the second side surface 183, and the third guide surface 184 and the second guide surface 182 are connected through the third side surface 185. In the direction from the first guide surface 181 to the second guide surface 182, the first guide surface 181, the second guide surface 182, and the third guide surface 184 are arranged in sequence and gradually rise. Each guide surface and the corresponding side surface can grow nanowires 150 at the boundary line, wherein the side surface corresponding to each guide surface connects the guide surface and the adjacent guide surface that is higher than the guide surface.

[0101] Furthermore, a step step 140 may also be provided on the third guide surface 184 . When the nanowire 150 grows along the first step surface 141 toward the second step surface 142 on the third guide surface 184 , the step step 140 also has the function of selecting the line width of the nanowire 150 .

[0102] When there are multiple third guide surfaces 184, adjacent third guide surfaces 184 in the multiple third guide surfaces 184 are also connected by side surfaces, and the multiple third guide surfaces 184 are arranged in sequence and gradually rise in the direction from the first guide surface 181 to the second guide surface 182, and each third guide surface 184 and the corresponding side surface can grow nanowires 150 at the boundary line, wherein the side surface corresponding to each guide surface connects the guide surface with the adjacent guide surface that is higher than the guide surface. Stepped steps 140 can be set on any third guide surface 184, that is, stepped steps 140 can be set on each third guide surface 184 or only some third guide surfaces 184 are set with stepped steps 140.

[0103] Some embodiments of the present application also provide a method for preparing a chip, and the nanowire can be used to manufacture the chip in any of the above embodiments. Fig.15 , the preparation method comprises the following steps:

[0104] S10 . Provide a substrate, wherein the substrate includes a first surface and a second surface that are opposite to each other in a thickness direction of the substrate.

[0105] See also Fig.16 , Fig.161 is a partial enlarged view of the substrate 110, the substrate 110 has a first surface 120 and a second surface 130, and the first surface 120 and the second surface 130 are arranged opposite to each other in the thickness direction of the substrate 110. The material of the substrate 110 can be crystalline silicon, glass, aluminum foil, silicon nitride, silicon oxide, silicon carbide, sapphire, PI (polyimide) or PET (polyethylene terephthalate plastic), etc.

[0106] S20. Form a stepped step 140 on the second surface 130. The stepped step 140 includes a first step surface 141, a second step surface 142, and a first side surface 143 connecting the first step surface 141 and the second step surface 142. Relative to the first surface 120, the first step surface 141 is lower than the second step surface 142.

[0107] See also Fig.17 , Fig.17 Schematic diagram of defining the second step surface using the first mask layer 191. Specifically, to form the stepped step 140, the first mask layer 191 can be formed on the second surface 130 of the substrate 110, and after forming the first mask layer 191, the first mask layer 191 on the area where the first step surface to be formed is located is removed to form a second opening 193, so that the area where the first step surface to be formed is located is exposed. At this time, the first mask layer 191 is formed on the upper part of the second step surface 142.

[0108] In some embodiments, the first mask layer 191 may be a photoresist, and the photoresist is coated by a two-step spin coating method, wherein a layer of photoresist is spin-coated, wherein the first step of the spin coating is 500 rpm for 9 seconds, and the second step of the spin coating is 4000 rpm for 30 seconds.

[0109] Figure 18-19 Schematic diagram of the structure after the step step 140 is formed on the substrate 110. In the area not covered by the first mask layer 191, that is, at the second opening 193, part of the substrate 110 is removed, for example, etching is performed in the thickness direction of the substrate 110, so that the surface of the area drops by a first height h1, and the first height h1 can be 30nm-80nm, for example, 50nm, so as to form a first step surface 141. At the same time, after the area not covered by the first mask layer 191 drops by the first height h1, there is a drop of the first height h1 between the area not covered by the first mask layer 191 and the area covered by the first mask layer 191, and this drop also forms a surface, which is the first side surface 143. The area of ​​the second surface 130 covered by the first mask layer 191 is the second step surface 142. In this way, the first step surface 141, the first side surface 143 and the second step surface 142 form the step step 140.

[0110] The removal of a portion of the substrate 110 may adopt dry etching or wet etching or other etching techniques commonly used in the semiconductor field, but the embodiments of the present application are not limited thereto.

[0111] However, the growth direction of the nanowires on the surface is uncertain. In some embodiments, in order to control the growth direction of the nanowires and arrange the nanowires according to a certain pattern to facilitate the integration of nanowire devices, it is also necessary to form a guiding step on the second surface 130 .

[0112] See also Fig. 20 The guide step 180 includes a first guide surface 181, a second guide surface 182 and a second side surface 183, and in the thickness direction of the substrate 110, relative to the first surface 120, the first guide surface 181 is lower than the second guide surface 182, that is, the first guide surface 181 is closer to the first surface 120 than the second guide surface 182.

[0113] In some embodiments, the guide step 180 may be formed by a method similar to the method of forming the step step 140. That is, a second mask layer 192 is formed on the second surface 130 of the substrate 110, and after forming the second mask layer 192, the second mask layer 192 on the region where the step step 140 is located is partially removed to expose the region where the step step 140 is located, and the region where the step step 140 is located refers to a region extending in the second direction D2 and having a certain size in the first direction D1.

[0114] Then, a portion of the substrate 110 is removed from the area not covered by the second mask layer 192, so that the surface of the area is lowered by a second height h2, thereby forming a guide step 180. The second height h2 can be selected to be 150nm-300nm, for example, 200nm. Therefore, the exposed area forms a first guide surface 181 after the drop, and the area covered by the second mask layer 192 forms a second guide surface 182. The boundary between the two areas is lowered by the second height h2, so a second side surface 183 is formed. It can be understood that since there is a step step 140 on the exposed area, after all surfaces in the area are lowered by the second height h2, the step step 140 still exists. In other words, there is a step step 140 on the formed first guide surface 181.

[0115] It can be understood that in order to ensure that the nanowire grows across the stepped step 140 rather than across the guide step 180 , the second height h2 is greater than the first height h1 .

[0116] In some embodiments, the guide step 180 may be formed first, and then the stepped step 140 may be formed.

[0117] See also Fig.21, a second mask layer 192 is used to define the second guide surface 182. The specific steps are similar to the aforementioned method of forming the step step 140, that is, a second mask layer 192 is formed on the second surface 130, and the second mask layer 192 forms a first opening 194. The area where the second guide surface 182 is located is covered by the second mask layer 192, and the area corresponding to the first opening 194 is the area where the first guide surface 182 is formed.

[0118] See also Fig. 22 After defining the second guide surface 182 using the second mask layer 192 , a portion of the substrate 110 is removed through the first opening 194 , so that the area corresponding to the first opening 194 is lowered by a second height h2 , which may be 150 nm-300 nm, for example, 200 nm, thereby forming the guide step 180 .

[0119] Similarly, a similar method can be used to form a stepped step 140 on the guide step 180. When the stepped step 140 is formed, the area where the first step surface 141 is located drops by a first height h1, and the first height h1 is less than the second height h2. The first height h1 can be 30nm-80nm, for example, 50nm. Thus, the stepped step 140 is formed on the first guide surface 181. Fig.23 As shown, it is easy to understand that in order to facilitate process implementation or form more step steps 140 , the area not covered by the second mask layer 192 is extended in the arrangement direction of the first guide surface 181 and the second guide surface 182 , thereby forming a step step 140 on the second guide surface 182 .

[0120] S30 , forming catalytic metal droplets on the first step surface 141 .

[0121] A layer of catalytic metal is deposited on the first step surface 141. Specifically, the deposition may be performed by thermal evaporation or electron beam evaporation (EBE) evaporation and other processes. The catalytic metals that can be selected include indium (In), tin (Sn), gallium indium alloy, bismuth (Bi), indium tin oxide (ITO), etc. It is easy to understand that the deposited catalytic metal may cover the entire second surface 130, so it is necessary to use a photolithography process or other semiconductor process to remove a portion of the catalytic metal so that the catalytic metal layer forms a catalytic metal belt 155.

[0122] like Fig.24 As shown, in some embodiments, the catalytic metal strip 155 is parallel to the extension direction of the first side surface 143 in the first direction D1, that is, the distance from any point on the catalytic metal strip 155 close to the first side surface 143 to the first side surface 143 is equal.

[0123] The thickness of the deposited catalytic metal layer is in the range of 5 nm to 20 nm, for example, 10 nm. The size of the catalytic metal layer in the second direction D2 is in the range of 5 nm to 30 nm, for example, 15 nm.

[0124] The substrate 110 formed with the catalytic metal strip 155 is sent into a reaction chamber. Optionally, the reaction chamber is a reaction chamber of a PECVD (Plasma Enhanced Chemical Vapor Deposition, PECVD) device. Subsequently, the temperature of the reaction chamber is raised to a temperature higher than the melting point of the catalytic metal. For example, when the catalytic metal is indium, the temperature can be raised to above 350°C. At the same time, hydrogen is introduced into the chamber under a vacuum state, and ignition is performed using a radio frequency power supply. Under the action of hydrogen plasma, the native oxide layer on the surface of the catalytic metal is reduced, and the catalytic metal is melted to form catalytic metal droplets 160.

[0125] like Fig.25 As shown, in some embodiments, a guide step 180 is formed on the substrate 110. At this time, it can be understood that the catalytic metal droplets 160 tend to form at the junction of the second side surface 183 and the first guide surface 181, or in other words, tend to form at the junction of the second side surface 183 and the guide step 140, so as to minimize the surface Gibbs free energy.

[0126] S40 , forming an amorphous semiconductor thin film on the second surface 130 .

[0127] like Fig.26 As shown, after the catalytic metal droplets 160 are formed on the substrate 110, the temperature of the substrate 110 is lowered to below the melting point of the catalytic metal. For example, when the catalytic metal is indium, the temperature of the reaction chamber is lowered to 150°C, that is, below the melting point of indium, and the catalytic metal droplets 160 are re-solidified. Specifically, in some embodiments, a precursor gas is introduced into the chamber, and after being ignited by a radio frequency power supply, a layer of amorphous semiconductor film 161 corresponding to the grown nanowire is deposited on the second surface 130 of the substrate 110 as an atomic supply source for the nanowire. For example, if the grown nanowire is a silicon nanowire, the introduced gas is silane, and the formed amorphous semiconductor film 161 is an amorphous silicon film.

[0128] It is easy to understand that the thickness of the amorphous semiconductor film 161 will affect the quality of the formed nanowires. The thickness of the amorphous semiconductor film 161 is related to the diameter of the catalytic metal droplets. When the thickness of the amorphous silicon film is low, it may cause insufficient silicon atom supply, stop the growth of the nanowires, or form an island-chain structure; and when the thickness of the amorphous silicon film is high, the nanowire width may be uneven. The thickness of the amorphous semiconductor film 161 ranges from 8nm to 45nm, for example, 20nm. Optionally, when the thickness of the catalytic metal strip 155 is 10nm, the thickness of the amorphous semiconductor film 161 is 20nm.

[0129] The reaction chamber used for this step can be the PECVD reaction chamber in step S30, which can reduce the transmission of the substrate 110 and prevent the formed catalytic metal droplets 160 from being oxidized again. However, the present application does not limit this.

[0130] S50, annealing the substrate 110 so that the catalytic metal droplets 160 absorb the amorphous semiconductor and grow on the step step 140 to form at least one nanowire 150; the nanowire 150 includes a first nanowire 151, and the first nanowire 151 extends from the first step surface 141 to the second step surface 142 through the first side surface 143.

[0131] In a vacuum environment, the temperature of the substrate 110 is raised to a temperature higher than the melting point of the catalytic metal droplets 160 and maintained for a period of time, at which time the solid catalytic metal droplets 160 will melt into liquid droplets again and be activated, and begin to absorb nearby amorphous semiconductors at the front interface and form crystalline nanowires at the rear interface. It is easy to understand that the maintenance time is related to the length of the growing nanowires 150.

[0132] like Fig. 27 As shown, the formed nanowire 150 is a first nanowire 151, and the first nanowire 151 extends from the first step surface 141 to the second step surface 142 via the first side surface 143. It can be understood that Fig. 27 Only one region of the substrate 110 is shown, and a plurality of guide steps 180 are arranged on the second surface 130 of the substrate 110, and a step step 140 is provided on the first guide surface 181 of each guide step 180. In an ideal state, a nanowire 150 grows at the boundary between the first guide surface 181 and the second side surface 183 of each guide step 180. Therefore, after the substrate 110 is annealed, a plurality of nanowires 150 are formed on the substrate 110, and some or all of the plurality of nanowires 150 extend from the first step surface 141 to the second step surface 142 via the first side surface 143, that is, some or all of the plurality of nanowires 150 are first nanowires 151.

[0133] Likewise, the reaction chamber used for this step may be the PECVD reaction chamber in step S30, which can reduce the transportation of the substrate 110 and prevent the formed catalytic metal droplets 160 from being oxidized again. However, the present application does not impose any limitation on this.

[0134] S60 , removing the residual amorphous semiconductor layer.

[0135] Since the amorphous semiconductor film is deposited on the second surface 130 of the entire substrate 110, and the catalytic metal droplet only absorbs the amorphous semiconductor film within a certain range around the moving track on its moving track, it is necessary to remove the residual amorphous semiconductor film. Taking the growth of silicon nanowires as an example, the amorphous semiconductor film is an amorphous silicon film. At this time, a relatively high-power hydrogen plasma is used to etch away the excess amorphous silicon, while the silicon nanowires are retained.

[0136] Thus, nanowires with high integration, certain arrangement rules, small line width and high uniformity can be obtained. Such nanowires can be used to integrate nanowire devices, such as integrated transistors, to prepare chips. Among them, the use of nanowires to form transistors can adopt existing semiconductor process technology, which will not be repeated in the embodiments of this application.

[0137] The above are only specific implementations of the present application, but the protection scope of the application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A chip, characterized in that: include: A substrate, comprising a first surface and a second surface opposite to each other in a thickness direction of the substrate; the second surface has a stepped step, the stepped step comprising a first step surface, a second step surface and a first side surface connecting the first step surface and the second step surface, and relative to the first surface, the first step surface is lower than the second step surface; At least one nanowire is located on the substrate, and the nanowire includes a first nanowire, and the first nanowire extends from the first step surface to the second step surface via the first side surface.

2. The chip according to claim 1, characterized in that: The chip includes a plurality of the nanowires, and the plurality of the nanowires include a second nanowire located on the substrate, and the second nanowire is located on the first step surface, or is located on the first step surface and the first side surface but not on the second step surface.

3. The chip according to claim 2, characterized in that: The line width of the first nanowire is smaller than the line width of the second nanowire.

4. The chip according to claim 1, characterized in that: The chip includes a plurality of the nanowires, and the plurality of the nanowires are all the first nanowires.

5. The chip according to any one of claims 1 to 4, characterized in that: The second surface of the substrate further has a guide step, the guide step includes a first guide surface, a second guide surface and a second side surface connecting the first guide surface and the second guide surface, and relative to the first surface, the first guide surface is lower than the second guide surface; The first guide surface has the stepped step; The first guide surface and the second guide surface are arranged along a first direction, the first step surface and the second step surface are arranged along a second direction, the first direction and the second direction are both parallel to the first surface, and the first direction and the second direction intersect.

6. The chip according to claim 5, characterized in that: The nanowire is located at a boundary line between the second side surface of the guide step and the first guide surface.

7. The chip according to claim 6, characterized in that Along the first direction, the second side surfaces and the second guide surfaces are provided on both sides of the step step, and one nanowire is provided at each junction line between the step step and the second side surfaces on both sides.

8. The chip according to any one of claims 5 to 7, characterized in that: The second guide surface has a stepped step, and nanowires are also arranged on the stepped step of the second guide surface.

9. The chip according to any one of claims 5 to 8, characterized in that: The guide step further includes at least one third guide surface, the first guide surface, the second guide surface and the at least one third guide surface are arranged along the first direction, and along the direction from the first guide surface to the second guide surface, the heights of the first guide surface, the second guide surface and the at least one third guide surface are increased in sequence; At least one of the third guide surfaces has a stepped step, and nanowires are also arranged on the stepped step of the third guide surface.

10. The chip according to any one of claims 1 to 9, characterized in that: The chip includes a plurality of stepped steps arranged at intervals, and the second step surfaces of the plurality of stepped steps are at the same height.

11. The chip according to any one of claims 1 to 10, characterized in that: The chip includes a transistor, and the first nanowire forms a channel of the transistor.

12. The chip according to claim 11, characterized in that: A channel of the transistor includes a plurality of the nanowires, and at least one of the plurality of the nanowires is the first nanowire.

13. The chip according to any one of claims 1 to 12, characterized in that: The dimension of the first step surface in the second direction is smaller than the dimension of the second step surface in the second direction.

14. The chip according to any one of claims 1 to 13, characterized in that: The first step surface is 30 nm-80 nm lower than the second step surface.

15. A method for preparing a chip, characterized in that: include: providing a substrate, the substrate comprising a first surface and a second surface opposite to each other in a thickness direction of the substrate; forming a stepped step on the second surface, the stepped step comprising a first step surface, a second step surface, and a first side surface connecting the first step surface and the second step surface, and relative to the first surface, the first step surface is lower than the second step surface; forming catalytic metal droplets on the first step surface; forming an amorphous semiconductor thin film on the second surface; The substrate is annealed so that the catalytic metal droplets absorb amorphous silicon grown on the step terrace to form at least one nanowire; the nanowire includes a first nanowire, and the first nanowire extends from the first step surface to the second step surface via the first side surface.

16. The method according to claim 15, characterized in that Before the second surface forms a stepped step, the method further comprises: A guide step is formed on the second surface, the guide step comprising a first guide surface, a second guide surface and a second side surface connecting the first guide surface and the second guide surface, and relative to the first surface, the first guide surface is lower than the second guide surface; Forming a stepped step on the second surface includes: forming a mask layer on the guide step, wherein the mask layer comprises a first opening, wherein the first opening exposes a portion of the first guide surface; etching the first guide surface based on the mask layer, so that the height of the portion of the first guide surface exposed by the first opening is reduced to form the step step; The first guide surface and the second guide surface are arranged along a first direction, the first step surface and the second step surface are arranged along a second direction, the first direction and the second direction are both parallel to the first surface, and the first direction and the second direction intersect.

17. An electronic device, characterized in that: The invention comprises a chip and a printed circuit board as claimed in any one of claims 1 to 14, wherein the chip is combined with the printed circuit board.

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