Metal oxide semiconductor field effect transistor, preparation method thereof and electronic equipment

Abstract

According to the metal oxide semiconductor field effect transistor, the preparation method thereof and the electronic equipment provided by the invention, the contact between the source electrode conductive layer and the first N-type drift layer and the contact between the source electrode conductive layer and the second N-type drift layer are Schottky contact, and a Schottky diode is integrated in the device, so that the conduction voltage drop of the diode of the device body can be reduced; the reverse recovery characteristic is improved, the device area can be effectively saved, and the parasitic parameter problem caused by a conventional anti-parallel scheme is eliminated. According to the Schottky diode, the source conducting layer is in contact with part of the upper surface of the first N-type drift layer and the side surface of the second N-type drift layer, so that the Schottky contact area can be larger, the on resistance can be lower, the conduction voltage drop can be further reduced, the conduction characteristic of the Schottky diode is better, and the further reduction of the cellular size is not limited. The P + shielding layer and the source conducting layer form ohmic contact, so that the electric field of the Schottky contact area can be reduced, the electric leakage of the source conducting layer is reduced, and the stability and reliability of the device are improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a metal oxide semiconductor field effect transistor, a preparation method thereof, and an electronic device. Background Art

[0002] Bridge circuits, such as half-bridge circuits and full-bridge circuits, are widely used due to their simple circuit structure and simple drive. In bridge circuits, diodes are often required or the body diode of MOSFET is used to freewheel the current in the inductive load. Since the body diode in the MOSFET is a PiN diode, there are a large number of free carriers in the drift region when the body diode is turned on. Although this is beneficial to reducing the conduction voltage drop of the body diode, it will lead to higher reverse recovery charge and reverse recovery current, which not only leads to higher power consumption and limits the increase in device frequency, but also affects the long-term reliability of the device. In addition, in SiC MOSFET, the body diode turn-on voltage is high, resulting in large device conduction power consumption, and the holes when the body diode is turned on will produce a bipolar degradation effect, affecting the long-term reliability of the device. Therefore, it is necessary to reduce the reverse recovery charge of the body diode of the MOSFET and improve the reverse recovery characteristics.

[0003] Schottky diodes have a lower turn-on voltage than PN junctions, and can achieve a lower conduction voltage drop than PiN diodes at relatively low currents. And because Schottky diodes are unipolar when turned on, they have almost no reverse recovery charge, which can improve the reverse recovery characteristics. Therefore, Schottky diodes are often used in anti-parallel with MOSFETs, and the Schottky diodes are used for freewheeling. However, anti-parallel Schottky diodes have the problem of large system volume and the introduction of parasitic parameters.

[0004] like Figure 1 As shown, Figure 1 The MOSFET device structure with an internally integrated Schottky diode proposed by Mitsubishi Corporation of Japan (publication number: US9214458B2) includes, from bottom to top: drain electrode 85, back ohmic electrode 71, n-type substrate 10, drift layer 20, first separation region 22, p-type well region 30, source region 40, well contact region 35, gate insulating film 50, gate electrode 60, interlayer insulating film 55, source ohmic electrode 70, Schottky electrode 75 and source electrode 80. Figure 1 In the semiconductor device shown, a Schottky electrode 75 is formed on the first separation region 22 . The Schottky electrode 75 forms a Schottky contact with silicon carbide of the first separation region 22 , thereby introducing a Schottky diode as a reflux diode into the device. Figure 1 Although the structure shown solves the problem of large system volume and introduction of parasitic parameters of anti-parallel Schottky diodes, Figure 1 The structure also has certain defects, such as Figure 1 If the structure shown wants to reduce the reverse conduction voltage drop of the device, it is necessary to increase the Schottky contact area between the Schottky electrode 75 and the first separation region 22, that is, it is necessary to increase the lateral width of the Schottky electrode 75 and the first separation region 22, so that the Schottky contact area occupies the area of ​​the semiconductor device, limiting the further reduction of the cell size. Summary of the invention

[0005] In view of this, the embodiments of the present disclosure provide a metal oxide semiconductor field effect transistor, a method for manufacturing the same, and an electronic device, which are used to reduce the conduction voltage drop of the device body diode, improve the reverse recovery characteristics, and will not increase the cell size.

[0006] The embodiments of the present disclosure provide a metal oxide semiconductor field effect transistor, a method for manufacturing the same, and an electronic device, the specific scheme of which is as follows:

[0007] In one aspect, an embodiment of the present disclosure provides a metal oxide semiconductor field effect transistor, comprising:

[0008] N+ substrate;

[0009] A drain conductive layer, located on one side of the N+ substrate;

[0010] A first N-type drift layer, located on a side of the N+ substrate away from the drain conductive layer;

[0011] A P+ shielding structure is located in the first N-type drift layer and close to a side of the first N-type drift layer away from the N+ substrate, wherein the P+ shielding structure includes two P+ shielding layers that are spaced apart and arranged laterally;

[0012] A second N-type drift layer, located at a side of the first N-type drift layer away from the N+ substrate, and a contact region is provided at the periphery of the second N-type drift layer;

[0013] A source conductive layer is located on a side of the second N-type drift layer away from the N+ substrate, the source conductive layer fills the contact area, and the source conductive layer is respectively in contact with a side of the first N-type drift layer away from the N+ substrate, a side of the P+ shielding layer away from the N+ substrate, and a side surface of the second N-type drift layer.

[0014] In some embodiments, in the above-mentioned metal oxide semiconductor field effect transistor provided in the embodiments of the present disclosure, the contact region extends to the interior of the first N-type drift layer and the P+ shielding layer, and the P+ shielding layer wraps the corner area of ​​the source conductive layer in the contact region close to the center of the P+ shielding structure.

[0015] In some embodiments, the above-mentioned metal oxide semiconductor field effect transistor provided in the embodiments of the present disclosure further includes: two P-type well regions located in the second N-type drift layer and close to the side of the second N-type drift layer away from the N+ substrate, and an N+ source region and a P+ source region located in each of the P-type well regions and close to the side of the second N-type drift layer away from the N+ substrate; wherein the N+ source region and the P+ source region are arranged laterally and contact each other, and the P+ source region is arranged close to the side of the second N-type drift layer, and the P-type well region covers the P+ source region and the side of the N+ source region close to the N+ substrate.

[0016] In some embodiments, in the above-mentioned metal oxide semiconductor field effect transistor provided in the embodiments of the present disclosure, the second N-type drift layer has a groove on a side away from the N+ substrate, and the groove is located between the two P-type well regions, the groove is filled with a gate conductive layer, and a gate dielectric layer is provided between the gate conductive layer and the side walls and bottom walls of the groove, the gate dielectric layer is in contact with the P-type well region, the side of the N+ source region and the second N-type drift layer, an isolation dielectric layer is provided between the P+ source region, the N+ source region, the gate dielectric layer, the gate conductive layer and the source conductive layer, the isolation dielectric layer is in contact with the gate conductive layer and the gate dielectric layer and is in contact with a partial area of ​​the N+ source region.

[0017] In some embodiments, in the above-mentioned metal oxide semiconductor field effect transistor provided by the embodiments of the present disclosure, the thickness of the second N-type drift layer covered by the gate dielectric layer is smaller than the thickness of the second N-type drift layer covered by the P-type well region.

[0018] In some embodiments, in the above-mentioned metal oxide semiconductor field effect transistor provided by the embodiments of the present disclosure, the P-type well region also covers the side of the N+ source region away from the P+ source region;

[0019] The metal oxide semiconductor field effect transistor also includes: a gate dielectric layer located on a side of the second N-type drift layer away from the N+ substrate, a gate conductive layer located on a side of the gate dielectric layer away from the N+ substrate, and an isolation dielectric layer located on a side of the gate conductive layer away from the N+ substrate; the gate dielectric layer is in contact with the second N-type drift layer, the P-type well region and the N+ source region, and the isolation dielectric layer wraps the gate conductive layer and is in contact with the gate dielectric layer.

[0020] In some embodiments, the metal oxide semiconductor field effect transistor provided in the embodiments of the present disclosure further includes: a third N-type drift layer located between the first N-type drift layer and the N+ substrate, and an N-type buffer layer located between the third N-type drift layer and the N+ substrate.

[0021] On the other hand, the present disclosure also provides a method for preparing a metal oxide semiconductor field effect transistor, which is used to prepare the metal oxide semiconductor field effect transistor provided in the present disclosure, and the preparation method comprises:

[0022] epitaxially forming a first N-type drift layer on one side of the N+ substrate;

[0023] Implanting P-type impurities on a side of the first N-type drift layer away from the N+ substrate to form an interval P+ shielding layer;

[0024] epitaxially forming a second N-type drift layer on a side of the first N-type drift layer away from the N+ substrate;

[0025] Carving through the periphery of the second N-type drift layer to form a contact region;

[0026] forming a source conductive layer on a side of the second N-type drift layer away from the N+ substrate, the source conductive layer filling the contact area, and the source conductive layer respectively contacts the side of the first N-type drift layer away from the N+ substrate, the side of the P+ shielding layer away from the N+ substrate, and the side surface of the second N-type drift layer;

[0027] Thinning the N+ substrate;

[0028] A drain conductive layer is formed on a side of the thinned N+ substrate away from the first N-type drift layer.

[0029] In some embodiments, in the above-mentioned preparation method provided in the embodiments of the present disclosure, after epitaxially forming a second N-type drift layer on a side of the first N-type drift layer away from the N+ substrate and before etching through the periphery of the second N-type drift layer to form a contact region, the method further includes:

[0030] Forming a P-type well region, an N+ source region and a P+ source region by injecting corresponding N-type or P-type impurities on a side of the second N-type drift layer away from the N+ substrate;

[0031] Carving through the middle area between the N+ source region and the P-type well region to form a groove;

[0032] forming a gate dielectric layer and a gate conductive layer in the groove in sequence to fill the groove;

[0033] An isolation dielectric film is deposited on a side of the P+ source region, the N+ source region, the gate dielectric layer and the gate conductive layer away from the N+ substrate.

[0034] In some embodiments, in the above-mentioned preparation method provided by the embodiments of the present disclosure, when the middle area between the N+ source region and the P-type well region is etched to form a groove, the groove also penetrates a part of the thickness of the second N-type drift layer.

[0035] In some embodiments, in the above-mentioned preparation method provided by the embodiment of the present disclosure, when etching through the periphery of the second N-type drift layer to form a contact area, it also includes: simultaneously etching through the peripheral areas of the isolation dielectric film, the P+ source region, and the P-type well region.

[0036] In some embodiments, in the above-mentioned preparation method provided by the embodiments of the present disclosure, when the periphery of the second N-type drift layer is etched through to form a contact region, the contact region also penetrates into the interior of the first N-type drift layer and the P+ shielding layer.

[0037] In some embodiments, in the above-mentioned preparation method provided in the embodiments of the present disclosure, after the periphery of the second N-type drift layer is etched through to form a contact region and before a source conductive layer is formed on a side of the second N-type drift layer away from the N+ substrate, the method further includes:

[0038] The remaining isolation dielectric film is etched to form an isolation dielectric layer, wherein the isolation dielectric layer is in contact with the gate conductive layer and the gate dielectric layer and is in contact with a portion of the N+ source region.

[0039] On the other hand, an embodiment of the present disclosure further provides an electronic device, comprising the above-mentioned metal oxide semiconductor field effect transistor provided by an embodiment of the present disclosure.

[0040] The beneficial effects of the present disclosure are as follows:

[0041] The embodiments of the present disclosure provide a metal oxide semiconductor field effect transistor, a method for preparing the transistor, and an electronic device. A contact region is provided on the periphery of the second N-type drift layer, and the source conductive layer fills the contact region, so that the source conductive layer contacts the first N-type drift layer, the P+ shielding layer, and the side of the second N-type drift layer, respectively, and the contact between the source conductive layer and the first N-type drift layer and the second N-type drift layer is a Schottky contact. In this way, the present disclosure integrates the Schottky diode inside the device, which is beneficial to reducing the conduction voltage drop of the device body diode, and the Schottky diode has almost no reverse recovery charge. Therefore, the present disclosure can also improve the reverse recovery characteristics, and by integrating the Schottky diode inside the device, the device area can be effectively saved, and the parasitic parameter problem caused by the conventional anti-parallel scheme can be eliminated. Moreover, compared with Figure 1In the structure shown, since the source conductive layer of the present invention contacts part of the upper surface of the first N-type drift layer and the side of the second N-type drift layer, the Schottky contact area of ​​the present invention can be larger, and the on-resistance of the Schottky diode can be lower, so that the on-voltage drop can be further reduced, so that the on-characteristics of the Schottky diode can be better, and it will not limit the further reduction of the cell size. In addition, the P+ shielding layer forms an ohmic contact with the source conductive layer, which can reduce the electric field in the Schottky contact area, thereby reducing the leakage of the source conductive layer and improving the stability and reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 A structure of a semiconductor device provided in the prior art;

[0043] Figure 2 A schematic diagram of a structure of a metal oxide semiconductor field effect transistor provided in an embodiment of the present disclosure;

[0044] Figure 3 for Figure 2 A schematic diagram of the current path when the metal oxide semiconductor field effect transistor is reversely conducted;

[0045] Figure 4 A schematic diagram of another structure of a metal oxide semiconductor field effect transistor provided in an embodiment of the present disclosure;

[0046] Figure 5 A flow chart of a method for preparing a metal oxide semiconductor field effect transistor provided in an embodiment of the present disclosure;

[0047] Figure 6 A flow chart of another method for preparing a metal oxide semiconductor field effect transistor provided in an embodiment of the present disclosure;

[0048] Fig. 7A for Figure 2 A schematic diagram of the structure of a metal oxide semiconductor field effect transistor during the preparation process shown;

[0049] Figure 7B for Figure 2 Another structural schematic diagram of a metal oxide semiconductor field effect transistor during the preparation process is shown;

[0050] Figure 7C for Figure 2 Another structural schematic diagram of a metal oxide semiconductor field effect transistor during the preparation process is shown;

[0051] Fig.7D for Figure 2 Another structural schematic diagram of a metal oxide semiconductor field effect transistor during the preparation process is shown;

[0052] Fig. 7E for Figure 2 Another structural schematic diagram of a metal oxide semiconductor field effect transistor during the preparation process is shown;

[0053] Figure 7F for Figure 2 Another structural schematic diagram of a metal oxide semiconductor field effect transistor during the preparation process is shown;

[0054] Figure 7G for Figure 2 Another structural schematic diagram of a metal oxide semiconductor field effect transistor during the preparation process is shown;

[0055] Figure 7H for Figure 2 Another structural schematic diagram of a metal oxide semiconductor field effect transistor during the preparation process is shown;

[0056] Fig.7I for Figure 2 Another structural schematic diagram of a metal oxide semiconductor field effect transistor during the preparation process is shown;

[0057] Figure 7J for Figure 2 Another structural schematic diagram of a metal oxide semiconductor field effect transistor during the preparation process is shown;

[0058] Figure 7K for Figure 2 Another structural schematic diagram of a metal oxide semiconductor field effect transistor during the preparation process is shown. DETAILED DESCRIPTION

[0059] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described in conjunction with the drawings of the embodiments of the present disclosure. It should be noted that in the drawings, the thickness of the layers, films, panels, regions, etc. is magnified for clarity. In the present disclosure, exemplary embodiments are described with reference to cross-sectional views of schematic diagrams of idealized embodiments. In this way, deviations from the shapes of the figures as a result of, for example, manufacturing technology and / or tolerances will be expected. Therefore, the embodiments described in the present disclosure should not be interpreted as being limited to the specific shapes of the regions shown in the present disclosure, but include deviations in shape caused by, for example, manufacturing. For example, an area illustrated or described as flat may typically have rough and / or nonlinear features; the illustrated sharp corners may be rounded, etc. Therefore, the areas shown in the figures are schematic in nature, and their sizes and shapes do not represent the exact shapes of the illustrated areas, do not reflect the true proportions, and the purpose is only to illustrate the contents of the present disclosure. And the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of well-known functions and well-known components.

[0060] Unless otherwise defined, the technical terms or scientific terms used herein shall have the usual meanings understood by persons of ordinary skill in the field to which the present disclosure belongs. The words "first", "second" and similar words used in the present disclosure specification and claims do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" and the like mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" and the like are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Inside", "outside", "upper", "lower", etc. are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0061] In the following description, when an element or layer is referred to as being "on" or "connected to" another element or layer, the element or layer may be directly on, directly connected to, or there may be an intermediate element or intermediate layer. When an element or layer is referred to as being "disposed on one side of" another element or layer, the element or layer may be directly on one side of, directly connected to, or there may be an intermediate element or intermediate layer. However, when an element or layer is referred to as being "directly on" or "directly connected to" another element or layer, there are no intermediate elements or intermediate layers. The term "and / or" includes any and all combinations of one or more of the related listed items.

[0062] The present disclosure provides a metal oxide semiconductor field effect transistor, such as Figure 2 As shown, including:

[0063] N+ substrate 1;

[0064] A drain conductive layer 2, located on one side of the N+ substrate 1;

[0065] A first N-type drift layer 3 is located on a side of the N+ substrate 1 away from the drain conductive layer 2;

[0066] The P+ shielding structure 4 is located in the first N-type drift layer 3 and close to a side of the first N-type drift layer 3 away from the N+ substrate 1. The P+ shielding structure 4 includes two P+ shielding layers 41 that are spaced apart and arranged laterally. Specifically, the two P+ shielding layers 41 can be formed by selectively injecting P-type impurities on a side of the first N-type drift layer 3 away from the N+ substrate 1.

[0067] A second N-type drift layer 5 is located on a side of the first N-type drift layer 3 away from the N+ substrate 1, and a contact region V is provided at the periphery of the second N-type drift layer 5;

[0068] The source conductive layer 6 is located on the side of the second N-type drift layer 5 away from the N+ substrate 1. The source conductive layer 6 fills the contact area V, and the source conductive layer 6 is respectively in contact with the side of the first N-type drift layer 3 away from the N+ substrate 1, the side of the P+ shielding layer 41 away from the N+ substrate 1, and the side of the second N-type drift layer 5.

[0069] The above-mentioned metal oxide semiconductor field effect transistor provided by the embodiment of the present disclosure has a contact area on the periphery of the second N-type drift layer, and the source conductive layer fills the contact area, so that the source conductive layer contacts the first N-type drift layer, the P+ shielding layer and the side of the second N-type drift layer respectively, and the contact between the source conductive layer and the first N-type drift layer and the second N-type drift layer is Schottky contact. In this way, the present disclosure integrates the Schottky diode inside the device, which is beneficial to reduce the conduction voltage drop of the device body diode, and the Schottky diode has almost no reverse recovery charge. Therefore, the present disclosure can also improve the reverse recovery characteristics, and by integrating the Schottky diode inside the device, the device area can be effectively saved, and the parasitic parameter problem caused by the conventional anti-parallel scheme can be eliminated. In addition, compared with Figure 1 In the structure shown, since the source conductive layer of the present invention contacts part of the upper surface of the first N-type drift layer and the side of the second N-type drift layer, the Schottky contact area of ​​the present invention can be larger, and the on-resistance of the Schottky diode can be lower, so that the on-voltage drop can be further reduced, so that the on-characteristics of the Schottky diode can be better, and it will not limit the further reduction of the cell size. In addition, the P+ shielding layer forms an ohmic contact with the source conductive layer, which can reduce the electric field in the Schottky contact area, thereby reducing the leakage of the source conductive layer and improving the stability and reliability of the device.

[0070] In some embodiments, in the above-mentioned metal oxide semiconductor field effect transistor provided in the embodiments of the present disclosure, as Figure 2 As shown, the contact region V can extend to the inside of the first N-type drift layer 2 and the P+ shielding layer 41, and the P+ shielding layer 41 wraps the corner area of ​​the source conductive layer 6 close to the center of the P+ shielding structure 4 in the contact region V. In this way, the P+ shielding layer 41 contacts the corner of the source conductive layer 6, so that it can be ensured that the Schottky contact can be formed on the side and bottom of the source conductive layer 6, so that the Schottky contact area can be increased.

[0071] In some embodiments, in the above-mentioned metal oxide semiconductor field effect transistor provided in the embodiments of the present disclosure, as Figure 2 As shown, it also includes: two P-type well regions 7 located in the second N-type drift layer 5 and close to the side of the second N-type drift layer 5 away from the N+ substrate 1, and an N+ source region 8 and a P+ source region 9 located in each P-type well region 7 and close to the side of the second N-type drift layer 5 away from the N+ substrate 1; wherein the N+ source region 8 and the P+ source region 9 are arranged laterally and contact each other, and the P+ source region 9 is arranged close to the side of the second N-type drift layer 5, and the P-type well region 7 covers the side of the P+ source region 9 and the N+ source region 8 close to the N+ substrate 1. Specifically, as Figure 2As shown, the P-type well region 7, the N+ source region 8 and the P+ source region 9 are all formed by ion implantation on the side of the second N-type drift layer 5 away from the N+ substrate 1. That is, the contact region V sequentially penetrates the P+ source region 9, the P-type well region 7 and the second N-type drift layer 5, and penetrates part of the first N-type drift layer 3 and the P+ shielding layer 41, the source conductive layer 6 fills the contact region V and is inserted into the first N-type drift region 3, and the P+ shielding layer 41 wraps the corner area of ​​the source conductive layer 6 in the contact region V close to the center of the P+ shielding structure 4, so that a part of the bottom of the source conductive layer 6 contacts the first N-type drift layer 3, another part of the bottom and part of the side wall contact the P+ shielding layer 41, and another part of the side wall contacts the side of the second N-type drift layer 5, and the contacts between the source conductive layer 6 and the second N-type drift layer 5 and the first N-type drift layer 3 are all Schottky contacts, compared to Figure 1 According to the scheme shown, the present disclosure can increase the area of ​​the Schottky contact. On the basis of improving the reverse recovery characteristics, the present disclosure can further reduce the conduction voltage drop of the device body diode and will not limit the further reduction of the cell size.

[0072] In some embodiments, in the above-mentioned metal oxide semiconductor field effect transistor provided in the embodiments of the present disclosure, as Figure 2 As shown, the second N-type drift layer 5 has a groove U on the side away from the N+ substrate 1, and the groove U is located between the two P-type well regions 7. The groove U is filled with a gate conductive layer 11, and a gate dielectric layer 12 is provided between the gate conductive layer 11 and the side wall and bottom wall of the groove U. The gate dielectric layer 12 is in contact with the P-type well region 7, the side of the N+ source region 8 and the second N-type drift layer 5. An isolation dielectric layer 13 is provided between the P+ source region 9, the N+ source region 8, the gate dielectric layer 12, and the gate conductive layer 11 and the source conductive layer 6. The isolation dielectric layer 13 is in contact with the gate conductive layer 11 and the gate dielectric layer 12 and is in contact with a part of the N+ source region 8. Specifically, the P+ shielding layer 41 can also reduce the electric field at the gate dielectric layer 12, thereby increasing the breakdown voltage of the gate conductive layer 11 and improving the stability and reliability of the device.

[0073] Optionally, the material of the gate dielectric layer 12 and the isolation dielectric layer 13 may be SiO 2 , HfO 2 , Al 2 O 3 , Si 3 N 4 , or the like.

[0074] In some embodiments, in the above-mentioned metal oxide semiconductor field effect transistor provided in the embodiments of the present disclosure, as Figure 2 As shown, the thickness of the second N-type drift layer 5 covered by the dielectric layer 12 is less than the thickness of the second N-type drift layer 5 covered by the P-type well region 7. In this way, the channel generated at the interface between the P-type well region 7 and the gate dielectric layer 12 can be connected to the second N-type drift layer 5 to form a conductive channel.

[0075] In some embodiments, in the above-mentioned metal oxide semiconductor field effect transistor provided in the embodiments of the present disclosure, as Figure 2 As shown, it also includes: a third N-type drift layer 14 located between the first N-type drift layer 3 and the N+ substrate 1, and an N-type buffer layer 15 located between the third N-type drift layer 14 and the N+ substrate 1. Optionally, the doping concentration of the first N-type drift layer 3 may be greater than or equal to the doping concentration of the third N-type drift layer 14, and the doping concentration of the second N-type drift layer 5 may be greater than or equal to the doping concentration of the third N-type drift layer 14.

[0076] Specifically, Figure 2 As shown, the P-type well region 7, N+ source region 8, P+ source region 9 and source conductive layer 6 constitute the source region of the device, the gate dielectric layer 12, the gate conductive layer 11 and the isolation dielectric layer 13 constitute the gate region of the device, the first N-type drift layer 3, the second N-type drift layer 5 and the third N-type drift layer 14 constitute the drift region of the device, and the N+ substrate 1, the N-type buffer layer 15 and the drain conductive layer 2 constitute the drain region of the device. The cell structure of the device includes the above-mentioned source region, gate region, drift region and drain region, and a cell may include multiple P-type well regions 7, N+ source regions 8, P+ source regions 9 and source conductive layers 6.

[0077] In some embodiments, in the above-mentioned metal oxide semiconductor field effect transistor provided in the embodiments of the present disclosure, the source conductive layer, the drain conductive layer and the gate conductive layer can all be made of one or more materials such as doped polysilicon and metal.

[0078] like Figure 3 As shown, Figure 3 for Figure 2 The current distribution diagram of the metal oxide semiconductor field effect transistor when the Schottky diode is turned on in the reverse freewheeling state is shown in FIG. Figure 3 It can be seen that the current (arrow pointing) can flow through the Schottky junction located in the second N-type drift layer 5 and the Schottky junction located in the first N-type drift layer 3, so the effective conduction area is relatively large. Figure 1 The solution shown is larger, the current distribution is more uniform, and the on-resistance is reduced, thereby reducing the reverse conduction voltage drop and achieving lower on-state power consumption.

[0079] In some embodiments, in the above-mentioned metal oxide semiconductor field effect transistor provided in the embodiments of the present disclosure, as Figure 2 As shown, the gate structure composed of the gate dielectric layer 12, the gate conductive layer 11 and the isolation dielectric layer 13 is a trench gate, which can also be Figure 4 The planar grid shown is not limited in the present disclosure.

[0080] In some embodiments, in the above-mentioned metal oxide semiconductor field effect transistor provided in the embodiments of the present disclosure, as Figure 4 As shown, the P-type well region 7 also covers the side of the N+ source region 8 away from the P+ source region 9;

[0081] The metal oxide semiconductor field effect transistor also includes: a gate dielectric layer 12 located on the side of the second N-type drift layer 5 away from the N+ substrate 1, a gate conductive layer 11 located on the side of the gate dielectric layer 12 away from the N+ substrate 1, and an isolation dielectric layer 13 located on the side of the gate conductive layer 11 away from the N+ substrate 1; the gate dielectric layer 12 is in contact with the second N-type drift layer 5, the P-type well region 7 and the N+ source region 8, and the isolation dielectric layer 13 wraps the gate conductive layer 11 and is in contact with the gate dielectric layer 12.

[0082] It should be noted that this disclosure Figure 4 The structure shown is Figure 2 The difference between the structures shown is that the device gate is a planar gate structure, and the other structures of the devices are the same, and the current distribution when the Schottky diode is turned on in the reverse freewheeling condition is also the same.

[0083] In some embodiments, the material of the N+ substrate in the present disclosure can be single crystal silicon, silicon carbide or gallium nitride, that is, the metal oxide semiconductor field effect transistor provided in the embodiment of the present disclosure can be based on semiconductor materials such as single crystal silicon, silicon carbide or gallium nitride, and can be prepared through processes such as epitaxy and ion implantation.

[0084] In some embodiments, in the above-mentioned metal oxide semiconductor field effect transistor provided in the embodiments of the present disclosure, as Figure 2 and Figure 4 As shown, the gate structure and the source conductive layer 6 can be called the front structure of the metal oxide semiconductor field effect transistor, and the drain conductive layer 2 can be called the back structure of the metal oxide semiconductor field effect transistor. The front structure of the device and the drain conductive layer 2 may not be in a one-to-one correspondence. For example, one drain conductive layer 2 may correspond to multiple repeated front structures.

[0085] It should be noted that the thickness of each region, the type of doped ions, and the ion doping concentration in the metal oxide semiconductor field effect transistor provided in the embodiments of the present disclosure can be designed as needed, and the present disclosure does not limit this.

[0086] Based on the same inventive concept, an embodiment of the present disclosure provides a method for preparing the above-mentioned metal oxide semiconductor field effect transistor. Since the principle of solving the problem by the preparation method is similar to the principle of solving the problem by the above-mentioned metal oxide semiconductor field effect transistor, the implementation of the preparation method provided by the embodiment of the present disclosure can refer to the implementation of the above-mentioned metal oxide semiconductor field effect transistor provided by the embodiment of the present disclosure, and the repeated parts will not be repeated.

[0087] In some embodiments, the method for preparing the metal oxide semiconductor field effect transistor provided in the embodiments of the present disclosure is as follows: Figure 5 As shown, this may include:

[0088] S501, epitaxially forming a first N-type drift layer on one side of an N+ substrate;

[0089] S502, implanting P-type impurities into a side of the first N-type drift layer away from the N+ substrate to form an interval P+ shielding layer;

[0090] S503, epitaxially forming a second N-type drift layer on a side of the first N-type drift layer away from the N+ substrate;

[0091] S504, etching the periphery of the second N-type drift layer to form a contact region;

[0092] S505, forming a source conductive layer on a side of the second N-type drift layer away from the N+ substrate, the source conductive layer filling the contact area, and the source conductive layer respectively contacts with a side of the first N-type drift layer away from the N+ substrate, a side of the P+ shielding layer away from the N+ substrate, and a side surface of the second N-type drift layer;

[0093] S506, thinning the N+ substrate;

[0094] S507 , forming a drain conductive layer on a side of the thinned N+ substrate away from the first N-type drift layer.

[0095] In some embodiments, in the above-mentioned preparation method provided by the embodiment of the present disclosure, after performing step S503 to epitaxially form a second N-type drift layer on a side of the first N-type drift layer away from the N+ substrate, and before performing step S504 to etch through the periphery of the second N-type drift layer to form a contact region, as shown in FIG. Figure 6 As shown, it also includes:

[0096] S601, forming a P-type well region, an N+ source region and a P+ source region by injecting corresponding N-type or P-type impurities on a side of the second N-type drift layer away from the N+ substrate;

[0097] S602, etching the middle area between the N+ source region and the P-type well region to form a groove;

[0098] S603, forming a gate dielectric layer and a gate conductive layer in the groove in sequence to fill the groove;

[0099] S604 , depositing an isolation dielectric film on the side of the P+ source region, the N+ source region, the gate dielectric layer and the gate conductive layer away from the N+ substrate.

[0100] In some embodiments, in the above-mentioned preparation method provided by the embodiments of the present disclosure, when performing step S602 to etch through the middle area between the N+ source region and the P-type well region to form a groove, the groove also penetrates part of the thickness of the second N-type drift layer.

[0101] In some embodiments, in the above-mentioned preparation method provided by the embodiment of the present disclosure, when performing step S504 to etch through the periphery of the second N-type drift layer to form a contact region, as Figure 6 As shown, it also includes: simultaneously etching through the isolation dielectric film, the P+ source region, and the peripheral region of the P-type well region.

[0102] In some embodiments, in the above-mentioned preparation method provided by the embodiment of the present disclosure, when performing step S504 to etch through the periphery of the second N-type drift layer to form a contact region, as Figure 6 As shown, the contact region also penetrates into the first N-type drift layer and the P+ shielding layer to expose a portion of the surface of the first N-type drift layer and a portion of the surface of the P+ shielding layer in the groove.

[0103] In some embodiments, in the above-mentioned preparation method provided by the embodiment of the present disclosure, after performing step S504 to etch through the periphery of the second N-type drift layer to form a contact region, and before performing step S505 to form a source conductive layer on a side of the second N-type drift layer away from the N+ substrate, as shown in FIG. Figure 6 As shown, it also includes:

[0104] S605 , etching the remaining isolation dielectric film to form an isolation dielectric layer, wherein the isolation dielectric layer is in contact with the gate conductive layer and the gate dielectric layer and is in contact with a portion of the N+ source region.

[0105] In order to better understand the above preparation method provided in the embodiments of the present disclosure, Figure 2 Taking the metal oxide semiconductor field effect transistor shown in the figure as an example, the preparation process of the metal oxide semiconductor field effect transistor is described in detail.

[0106] In some embodiments, Figure 2 The preparation process of the metal oxide semiconductor field effect transistor may specifically include the following steps:

[0107] (1) Fig. 7A As shown, an N-type buffer layer 15, a third N-type drift layer 14, and a first N-type drift layer 3 are epitaxially grown in sequence on one side of an N+ substrate 1;

[0108] (2) Then, Figure 7B As shown, P-type impurities are selectively implanted into a region on one side of the first N-type drift layer 3 away from the N+ substrate 1 to form two spaced P+ shielding layers 41;

[0109] (3) Then, Figure 7C As shown, a second N-type drift layer 5 is epitaxially formed on a side of the first N-type drift layer 3 away from the N+ substrate 1;

[0110] (4) Then, Fig.7D As shown, corresponding N-type or P-type impurities are selectively implanted into a region on one side of the second N-type drift layer 5 away from the N+ substrate 1 to form a P-type well region 7, an N+ source region 8 and a P+ source region 9, and high temperature annealing is used to activate the impurities;

[0111] (5) Then, Fig. 7E As shown, the middle area between the N+ source region 8 and the P-type well region 7 is etched to form a groove U, and the groove U also penetrates part of the thickness of the second N-type drift layer 5, that is, it is etched into the second N-type drift layer 5, but does not etch through the second N-type drift layer 5;

[0112] (6) Then, Figure 7F As shown, a gate dielectric layer 12 and a gate conductive layer 11 are sequentially formed in the groove U to fill the groove U;

[0113] (7) Then, Figure 7G As shown, an isolation dielectric film 13' is deposited on the side of the P+ source region 9, the N+ source region 8, the gate dielectric layer 12 and the gate conductive layer 11 away from the N+ substrate 1;

[0114] (8) Then, Figure 7H As shown, the periphery of the isolation dielectric film 13', the P+ source region 9, the P-type well region 7 and the second N-type drift layer 5 is etched through to form a contact region V, and the contact region V also penetrates into the first N-type drift layer 3 and the P+ shielding layer 41, so that part of the surface of the first N-type drift layer 3 and part of the surface of the P+ shielding layer 41 are exposed in the groove U;

[0115] (9) Then, Fig.7I As shown, the remaining isolation dielectric film 13' is etched to form an isolation dielectric layer 13, and the isolation dielectric layer 13 is in contact with the gate conductive layer 11 and the gate dielectric layer 12 and is in contact with a part of the N+ source region 8;

[0116] (10) Then, Figure 7J As shown, a source conductive layer 6 is formed on the side of the second N-type drift layer 5 away from the N+ substrate 1 by sputtering or other methods, the source conductive layer 6 fills the contact region V, and the source conductive layer 6 is in contact with the side of the first N-type drift layer 3 away from the N+ substrate 1, the side of the P+ shielding layer 41 away from the N+ substrate 1, and the side of the second N-type drift layer 5 respectively;

[0117] (11) Then, Figure 7K As shown, the N+ substrate 1 is thinned;

[0118] (12) Finally, a drain conductive layer 2 is formed on the side of the thinned N+ substrate 1 away from the first N-type drift layer 3 by sputtering or other methods, such as Figure 2 shown.

[0119] Through the above steps (1)-(12) a Figure 2 The metal oxide semiconductor field effect transistor shown.

[0120] Need to explain yes, Figure 4 The preparation method of the metal oxide semiconductor field effect transistor shown in Figure 2 The preparation method shown is basically the same, except that: in the above step (4), the selective injection is directly performed to form Figure 4 The P-type well region 7, N+ source region 8 and P+ source region 9 in the step (5) do not need the groove U, and a planar gate structure is directly formed on the side of the P+ source region 9, N+ source region 8 and the second N-type drift layer 5 away from the N+ substrate 1.

[0121] It should be noted that in the above-mentioned preparation method provided in the embodiment of the present disclosure, the patterning process involved in forming each layer structure may include not only part or all of the process such as deposition, photoresist coating, mask masking, exposure, development, etching, photoresist stripping, etc., but also other process, which is subject to the graphics of the required composition formed in the actual production process, and is not limited here. For example, a post-baking process may also be included after development and before etching. Among them, the deposition process may be chemical vapor deposition, plasma enhanced chemical vapor deposition or physical vapor deposition, which is not limited here; the mask used in the mask process may be a half-tone mask (Half Tone Mask), a single slit diffraction mask (Single Slit Mask) or a gray tone mask (Gray Tone Mask), which is not limited here; etching may be dry etching or wet etching, which is not limited here.

[0122] Based on the same inventive concept, an embodiment of the present disclosure provides an electronic device, including the metal oxide semiconductor field effect transistor provided in the embodiment of the present disclosure. Since the principle of solving the problem by the electronic device is similar to the principle of solving the problem by the metal oxide semiconductor field effect transistor, the implementation of the electronic device provided in the embodiment of the present disclosure can refer to the implementation of the metal oxide semiconductor field effect transistor provided in the embodiment of the present disclosure, and the repeated parts will not be repeated.

[0123] In some embodiments, the electronic devices provided by the embodiments of the present disclosure may include, but are not limited to: radio frequency amplifiers, mixers, radars, satellites, power supplies, automotive electronics, energy-saving lamps, household appliances, etc. Of course, in addition to metal oxide semiconductor field effect transistors, the electronic devices provided by the present disclosure may also include other structures, for example, when the electronic device is a radar, it also includes: transmitters, antennas, receivers, etc.; when the electronic device is a mixer, it also includes: input ports, output ports, etc.

[0124] The embodiments of the present disclosure provide a metal oxide semiconductor field effect transistor, a method for preparing the transistor, and an electronic device. A contact region is provided on the periphery of the second N-type drift layer, and the source conductive layer fills the contact region, so that the source conductive layer contacts the first N-type drift layer, the P+ shielding layer, and the side of the second N-type drift layer, respectively, and the contact between the source conductive layer and the first N-type drift layer and the second N-type drift layer is a Schottky contact. In this way, the present disclosure integrates the Schottky diode inside the device, which is beneficial to reducing the conduction voltage drop of the device body diode, and the Schottky diode has almost no reverse recovery charge. Therefore, the present disclosure can also improve the reverse recovery characteristics, and by integrating the Schottky diode inside the device, the device area can be effectively saved, and the parasitic parameter problem caused by the conventional anti-parallel scheme can be eliminated. Moreover, compared with Figure 1 In the structure shown, since the source conductive layer of the present invention contacts part of the upper surface of the first N-type drift layer and the side of the second N-type drift layer, the Schottky contact area of ​​the present invention can be larger, and the on-resistance of the Schottky diode can be lower, so that the on-voltage drop can be further reduced, so that the on-characteristics of the Schottky diode can be better, and it will not limit the further reduction of the cell size. In addition, the P+ shielding layer forms an ohmic contact with the source conductive layer, which can reduce the electric field in the Schottky contact area, thereby reducing the leakage of the source conductive layer and improving the stability and reliability of the device.

[0125] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present disclosure.

[0126] Obviously, those skilled in the art can make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to include these modifications and variations.

Claims

1. A metal oxide semiconductor field effect transistor, characterized in that: include: N+ substrate; A drain conductive layer, located on one side of the N+ substrate; A first N-type drift layer, located on a side of the N+ substrate away from the drain conductive layer; A P+ shielding structure is located in the first N-type drift layer and close to a side of the first N-type drift layer away from the N+ substrate, wherein the P+ shielding structure includes two P+ shielding layers that are spaced apart and arranged laterally; A second N-type drift layer, located at a side of the first N-type drift layer away from the N+ substrate, and a contact region is provided at the periphery of the second N-type drift layer; A source conductive layer is located on a side of the second N-type drift layer away from the N+ substrate, the source conductive layer fills the contact area, and the source conductive layer is respectively in contact with a side of the first N-type drift layer away from the N+ substrate, a side of the P+ shielding layer away from the N+ substrate, and a side surface of the second N-type drift layer.

2. The metal oxide semiconductor field effect transistor according to claim 1, characterized in that The contact region extends to the inside of the first N-type drift layer and the P+ shielding layer, and the P+ shielding layer wraps a corner region of the source conductive layer in the contact region close to the center of the P+ shielding structure.

3. The metal oxide semiconductor field effect transistor according to claim 2, characterized in that: Also includes: Two P-type well regions located in the second N-type drift layer and close to the side of the second N-type drift layer away from the N+ substrate, and an N+ source region and a P+ source region located in each of the P-type well regions and close to the side of the second N-type drift layer away from the N+ substrate; wherein the N+ source region and the P+ source region are arranged laterally and contact each other, and the P+ source region is arranged close to the side of the second N-type drift layer, and the P-type well region covers the P+ source region and the side of the N+ source region close to the N+ substrate.

4. The metal oxide semiconductor field effect transistor according to claim 3, characterized in that: The second N-type drift layer has a groove on a side away from the N+ substrate, and the groove is located between the two P-type well regions. The groove is filled with a gate conductive layer, and a gate dielectric layer is provided between the gate conductive layer and the side wall and the bottom wall of the groove. The gate dielectric layer is in contact with the P-type well region, the side of the N+ source region and the second N-type drift layer. An isolation dielectric layer is provided between the P+ source region, the N+ source region, the gate dielectric layer, the gate conductive layer and the source conductive layer, and the isolation dielectric layer is in contact with the gate conductive layer and the gate dielectric layer and is in contact with a partial area of ​​the N+ source region.

5. The metal oxide semiconductor field effect transistor according to claim 4, characterized in that: The thickness of the second N-type drift layer covered by the gate dielectric layer is smaller than the thickness of the second N-type drift layer covered by the P-type well region.

6. The metal oxide semiconductor field effect transistor according to claim 3, characterized in that: The P-type well region also covers the side of the N+ source region away from the P+ source region; The metal oxide semiconductor field effect transistor also includes: a gate dielectric layer located on a side of the second N-type drift layer away from the N+ substrate, a gate conductive layer located on a side of the gate dielectric layer away from the N+ substrate, and an isolation dielectric layer located on a side of the gate conductive layer away from the N+ substrate; the gate dielectric layer is in contact with the second N-type drift layer, the P-type well region and the N+ source region, and the isolation dielectric layer wraps the gate conductive layer and is in contact with the gate dielectric layer.

7. The metal oxide semiconductor field effect transistor according to any one of claims 1 to 6, characterized in that: The invention also includes: a third N-type drift layer located between the first N-type drift layer and the N+ substrate, and an N-type buffer layer located between the third N-type drift layer and the N+ substrate.

8. A method for preparing a metal oxide semiconductor field effect transistor, characterized in that: For preparing the metal oxide semiconductor field effect transistor according to any one of claims 1 to 7, the preparation method comprising: epitaxially forming a first N-type drift layer on one side of the N+ substrate; Implanting P-type impurities on a side of the first N-type drift layer away from the N+ substrate to form an interval P+ shielding layer; epitaxially forming a second N-type drift layer on a side of the first N-type drift layer away from the N+ substrate; Carving through the periphery of the second N-type drift layer to form a contact region; forming a source conductive layer on a side of the second N-type drift layer away from the N+ substrate, the source conductive layer filling the contact area, and the source conductive layer respectively contacts the side of the first N-type drift layer away from the N+ substrate, the side of the P+ shielding layer away from the N+ substrate, and the side surface of the second N-type drift layer; Thinning the N+ substrate; A drain conductive layer is formed on a side of the thinned N+ substrate away from the first N-type drift layer.

9. The preparation method according to claim 8, characterized in that: After forming a second N-type drift layer by epitaxial growth on a side of the first N-type drift layer away from the N+ substrate and before etching through the periphery of the second N-type drift layer to form a contact region, the method further includes: Forming a P-type well region, an N+ source region and a P+ source region by injecting corresponding N-type or P-type impurities on a side of the second N-type drift layer away from the N+ substrate; Carving through the middle area between the N+ source region and the P-type well region to form a groove; forming a gate dielectric layer and a gate conductive layer in the groove in sequence to fill the groove; An isolation dielectric film is deposited on a side of the P+ source region, the N+ source region, the gate dielectric layer and the gate conductive layer away from the N+ substrate.

10. The preparation method according to claim 9, characterized in that: When the middle region between the N+ source region and the P-type well region is etched to form a groove, the groove also penetrates a portion of the thickness of the second N-type drift layer.

11. The preparation method according to claim 9, characterized in that: When the periphery of the second N-type drift layer is etched through to form the contact region, the method further includes: simultaneously etched through the periphery of the isolation dielectric film, the P+ source region, and the P-type well region.

12. The preparation method according to claim 11, characterized in that: When the periphery of the second N-type drift layer is etched through to form a contact region, the contact region also penetrates into the first N-type drift layer and the P+ shielding layer.

13. The preparation method according to claim 12, characterized in that: After the periphery of the second N-type drift layer is etched through to form a contact region and before a source conductive layer is formed on a side of the second N-type drift layer away from the N+ substrate, the method further includes: The remaining isolation dielectric film is etched to form an isolation dielectric layer, wherein the isolation dielectric layer is in contact with the gate conductive layer and the gate dielectric layer and is in contact with a portion of the N+ source region.

14. An electronic device, characterized in that: Comprising the metal oxide semiconductor field effect transistor as described in any one of claims 1 to 7.

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