VDMOSFET with low switching loss and preparation method thereof

Abstract

The invention relates to the technical field of MOS (metal oxide semiconductor), and discloses a VDMOSFET (vertical double-diffused metal oxide semiconductor field effect transistor) with low switching loss, which comprises a metal drain electrode, a metal source electrode, a semiconductor epitaxial layer, a grid electrode and a grid oxide layer covering the surface of the grid electrode, and is characterized in that the semiconductor epitaxial layer internally comprises a sinking layer, a drift layer, a P well layer, a highly doped P layer and an N well layer; a conducting medium is arranged in the drift layer and below the grid electrode, and the section contour of the conducting medium is semicircular; the conducting medium is made of one of silicon dioxide, aluminum oxide, zirconium oxide or titanium oxide, a U-shaped diffusion layer is further arranged on the outer side of the conducting medium, and the U-shaped diffusion layer is in contact with the P well layer. By doping the conductive medium, the conductivity of the drift layer can be increased, the resistance of the drift region is reduced, the on resistance of the device is reduced, and the efficiency of the device in the switching process is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of MOS semiconductors, and in particular to a VDMOSFET with low switching loss and a preparation method thereof. Background Art

[0002] Low switching loss VDMOSFET (Vertical Double-Diffused MOSFET) is commonly used in power management and switching circuits. It is characterized by low switching loss and is suitable for high-speed switching applications.

[0003] The existing patent discloses a split-gate MOSFET device with reduced switching loss and a manufacturing method thereof (publication number CN111430464A), which includes a first conductive type substrate, a first conductive type epitaxial layer, a trench, a second conductive type body region, a first conductive type source region, an insulating dielectric layer, a gate metal, a source metal, a control gate polysilicon, a gate oxide layer, a split gate polysilicon, a dielectric isolation cavity and a drain metal, wherein the volume of the split gate polysilicon is smaller than the volume of the control gate polysilicon, and the thickness of the dielectric isolation cavity between the split gate polysilicon and the control gate polysilicon is greater than the thickness of the gate oxide layer. In the technology disclosed in the patent, the minimum spacing between the gate and the drain is increased, thereby increasing the risk of breakdown between the gate and the drain, which enhances the instability of the device under high voltage conditions. Summary of the invention

[0004] The main technical problem solved by the present invention is to provide a VDMOSFET with low switching loss and a preparation method thereof, which solves the problems in the above-mentioned background technology.

[0005] To solve the above technical problems, according to one aspect of the present invention, more specifically, a VDMOSFET with low switching loss includes a metal drain, a metal source, a semiconductor epitaxial layer, a gate, and a gate oxide layer covering the surface of the gate, wherein the semiconductor epitaxial layer includes a sink layer, a drift layer, a P-well layer, a highly doped P-layer and an N-well layer; A conductive medium is provided inside the drift layer and below the gate, and the cross-sectional profile of the conductive medium is in a semicircular shape; The conductive medium is made of one of silicon dioxide, aluminum oxide, zirconium oxide or titanium oxide.

[0006] Furthermore, a U-shaped diffusion layer is provided on the outer side of the conductive medium, and the U-shaped diffusion layer is in contact with the P-well layer.

[0007] Furthermore, a heavily doped diffusion layer a and a lightly doped diffusion layer are further disposed outside the dielectric. The cross-sectional profile of the heavily doped diffusion layer a is rectangular, and the cross-sectional profile of the lightly doped diffusion layer is U-shaped.

[0008] Furthermore, heavily doped diffusion layers b are provided on both left and right sides of the conductive medium, and the heavily doped diffusion layers b are only in contact with the conductive medium and the P-well layer.

[0009] A method for preparing a VDMOSFET with low switching loss, characterized in that it comprises the following steps: S1. Depositing a layer of silicon dioxide as a gate oxide layer on the surface of the silicon substrate through a thermal oxidation process, wherein the thickness of the gate oxide layer is in the range of tens of nanometers; S2, doping is performed in the area below the gate to form a conductive medium; S3, using ion implantation technology to form n-type or p-type doped regions on the silicon substrate, and controlling the doping concentration to optimize the switching performance of the VDMOSFET device; S4, depositing a layer of metal on the source and drain regions using evaporation or sputtering technology to form electrodes; S5, depositing a metal layer in the gate region to form a gate electrode, and defining the shape of the gate through a photolithography process to form the gate electrode; S6. Perform surface cleaning to remove impurities and perform electrical performance testing on the VDMOSFET device.

[0010] Furthermore, in the step S, a U-shaped diffusion layer is formed at the edge of the conductive medium by ion implantation.

[0011] Furthermore, in the step S, the deposited metal is one of aluminum or titanium, and an annealing treatment is performed to ensure good contact between the electrode and the silicon material.

[0012] Furthermore, in step S, according to the thermal resistance of the VDMOSFET device, the maximum voltage that the VDMOSFET device can withstand between the metal drain and the metal source, and the energy loss caused by switching the VDMOSFET device from the on state to the off state, there are: In the formula, Indicates the electrical performance qualification coefficient of the sampled VDMOSFET devices, It indicates the change in resistance of VDMOSFET device when the temperature rises from standard temperature to °C. It indicates the maximum voltage that the VDMOSFET device can withstand between the metal drain and the metal source. Represents the energy loss caused by the VDMOSFET device switching from the on state to the off state.

[0013] Furthermore, when When , it means that the electrical performance of the sampled VDMOSFET device is qualified; when When , it means that the electrical performance of the sampled VDMOSFET device is unqualified.

[0014] Beneficial effects: 1. The present invention can increase the conductivity of the drift layer and reduce the resistance of the drift region by doping with a conductive medium, which helps to reduce the on-resistance of the device and improve the efficiency of the device during the switching process.

[0015] 2. The present invention can effectively control the distribution and diffusion of carriers and reduce the recombination effect of carriers in the drift region by doping a conductive medium into the drift layer and adding a U-shaped diffusion layer. This can accelerate the switching process of the device, increase the switching speed, reduce the switching loss, and show better performance in high-frequency applications.

[0016] 3. The addition of the heavily doped diffusion layer a of the present invention helps to enhance the withstand voltage characteristics of the drift region. The presence of the heavily doped diffusion layer a improves the conductivity of the device, reduces the electric field strength in the drift region, enhances the stability of the device under high voltage conditions, and reduces the risk of voltage breakdown. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a structural schematic diagram of Embodiment 1 of the present invention; Figure 2 This is a schematic diagram of the structure of Embodiment 2 of the present invention; Figure 3 This is a schematic diagram of the structure of Embodiment 3 of the present invention; Figure 4 It is a structural schematic diagram of embodiment 4 of the present invention.

[0018] In the figure: 1. Metal drain; 2. Metal source; 3. Gate oxide layer; 4. Gate; 5. Conductive medium; 6. Substrate layer; 7. Drift layer; 8. P-well layer; 9. Highly doped P layer; 10. N-well layer; 11. U-shaped diffusion layer; 1101. Heavily doped diffusion layer a; 1102. Lightly doped diffusion layer; 1103. Heavily doped diffusion layer b. DETAILED DESCRIPTION

[0019] In order to make the technical solution of the present invention clearer, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0020] A method for preparing a VDMOSFET with low switching loss comprises the following steps: Step 1: deposit a layer of silicon dioxide as a gate oxide layer 3 on the surface of the silicon substrate through a thermal oxidation process. The thickness of the gate oxide layer 3 is in the range of tens of nanometers.

[0021] Step 2: doping is performed in the area below the gate 4 to form a conductive medium 5; and a U-shaped diffusion layer 11 is formed at the edge of the conductive medium 5 by ion implantation.

[0022] Step 3: Use ion implantation technology to form an n-type or p-type doped region on the silicon substrate, and control the doping concentration to optimize the switching performance of the VDMOSFET device.

[0023] Step 4: Use evaporation or sputtering technology to deposit a layer of metal in the source and drain regions to form electrodes; the deposited metal is one of aluminum or titanium, and annealing is performed to ensure good contact between the electrode and the silicon material.

[0024] Step 5: depositing a metal layer in the gate region to form a gate electrode, and defining the shape of the gate through a photolithography process to form the gate electrode.

[0025] Step 6: Perform surface cleaning to remove impurities and perform electrical performance testing on the VDMOSFET device.

[0026] According to the thermal resistance of the VDMOSFET device, the maximum voltage that the VDMOSFET device can withstand between the metal drain 1 and the metal source 2, and the energy loss caused by the VDMOSFET device switching from the on state to the off state, we have: In the formula, Indicates the electrical performance qualification coefficient of the sampled VDMOSFET devices, It indicates the change in resistance of the VDMOSFET device when the standard temperature rises by 70°C. It represents the maximum voltage that the VDMOSFET device can withstand between the metal drain 1 and the metal source 2. Represents the energy loss caused by the VDMOSFET device switching from the on state to the off state.

[0027] when When , it means that the electrical performance of the sampled VDMOSFET device is qualified; when When , it means that the electrical performance of the sampled VDMOSFET device is unqualified.

[0028] The electrical performance of any device X is tested. The resistance change of the VDMOSFET device when the standard temperature rises by 70°C is taken as (The change in resistance from standard room temperature of 25°C to 95°C = the increase in resistance ÷ the resistance at standard room temperature of 25°C).

[0029] The maximum voltage that the VDMOSFET device can withstand between the metal drain 1 and the metal source 2 is (Unit V).

[0030] The energy loss caused by the VDMOSFET device switching from the on state to the off state is (Unit: W). For VDMOSFET devices, the switching loss is usually calculated as: In the formula, It represents the energy loss caused by the VDMOSFET device switching from the on state to the off state. represents the drain-source voltage during switching, represents the drain current during switching, It indicates the time required from the beginning of conduction to full conduction. It indicates the time required from the start of shutdown to complete shutdown. Indicates the switching frequency.

[0031] Then, the electrical performance qualification coefficient of the sampled VDMOSFET devices can be calculated through the above data: That is, the electrical performance of the sampled VDMOSFET devices is qualified.

[0032] Example 1 like Figure 1 As shown, according to one aspect of the present invention, a VDMOSFET with low switching loss is provided, comprising a metal drain 1, a metal source 2, a semiconductor epitaxial layer, a gate 4, and a gate oxide layer 3 covering the surface of the gate 4, wherein the interior of the semiconductor epitaxial layer comprises a sink layer 6, a drift layer 7, a P well layer 8, a highly doped P layer 9, and an N well layer 10; a conductive medium 5 is provided inside the drift layer 7 and below the gate 4, and the cross-sectional profile of the conductive medium 5 is semicircular; the material of the conductive medium 5 is one of silicon dioxide, aluminum oxide, zirconium oxide, or titanium oxide. By doping the conductive medium 5, the conductivity of the drift layer 7 can be increased and the resistance of the drift region can be reduced. This helps to reduce the on-resistance of the device and improve the efficiency of the device during the switching process.

[0033] Example 2 like Figure 2 As shown, a U-shaped diffusion layer 11 is also provided on the outside of the conductive medium 5, and the U-shaped diffusion layer 11 is in contact with the P-well layer 8. By doping the conductive medium 5 in the drift layer 7 and adding the U-shaped diffusion layer 11, the distribution and diffusion of carriers can be effectively controlled, and the recombination effect of carriers in the drift region can be reduced. This can accelerate the switching process of the device, increase the switching speed, reduce the switching loss, and show better performance in high-frequency applications.

[0034] Example 3 like Figure 3 As shown, a heavily doped diffusion layer a1101 and a lightly doped diffusion layer 1102 are also provided on the outside of the dielectric 5. The cross-sectional profile of the heavily doped diffusion layer a1101 is rectangular, and the cross-sectional profile of the lightly doped diffusion layer 1102 is in a 'U' shape. The addition of the heavily doped diffusion layer a1101 helps to enhance the withstand voltage characteristics of the drift region. The presence of the heavily doped diffusion layer a1101 improves the conductivity of the device, reduces the electric field strength in the drift region, enhances the stability of the device under high voltage conditions, and reduces the risk of voltage breakdown.

[0035] Example 4 like Figure 4 As shown, heavily doped diffusion layers b1103 are provided on both the left and right sides of the conductive medium 5, and the heavily doped diffusion layers b1103 are only in contact with the conductive medium 5 and the P-well layer 8. The configuration of the conductive medium 5 and the heavily doped diffusion layer b1103 helps to make the electric field distribution of the device more uniform, reduce current fluctuations, and reduce the electromagnetic interference generated thereby. This design helps to improve the electromagnetic compatibility of the device and reduce interference to surrounding circuits, which is of great significance, especially in high-frequency applications.

[0036] The above-mentioned embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the patent of the present invention. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A low switching loss VDMOSFET, comprising a metal drain (1), a metal source (2), a semiconductor epitaxial layer, a gate (4), and a gate oxide layer (3) covering the surface of the gate (4), characterized in that: The semiconductor epitaxial layer comprises a sink layer (6), a drift layer (7), a P-well layer (8), a highly doped P-layer (9) and an N-well layer (10); A conductive medium (5) is provided inside the drift layer (7) and below the gate (4), and the cross-sectional profile of the conductive medium (5) is in a semicircular shape; The conductive medium (5) is made of one of silicon dioxide, aluminum oxide, zirconium oxide or titanium oxide.

2. The low switching loss VDMOSFET according to claim 1, characterized in that: A U-shaped diffusion layer (11) is also provided on the outside of the conductive medium (5), and the U-shaped diffusion layer (11) is in contact with the P-well layer (8).

3. The low switching loss VDMOSFET according to claim 1, characterized in that: A heavily doped diffusion layer a (1101) and a lightly doped diffusion layer (1102) are also provided on the outside of the dielectric (5); the cross-sectional profile of the heavily doped diffusion layer a (1101) is rectangular, and the cross-sectional profile of the lightly doped diffusion layer (1102) is in a 'U' shape.

4. The low switching loss VDMOSFET according to claim 1, characterized in that: A heavily doped diffusion layer b (1103) is provided on both left and right sides of the conductive medium (5), and the heavily doped diffusion layer b (1103) is only in contact with the conductive medium (5) and the P well layer (8).

5. A method for preparing a VDMOSFET with low switching loss according to any one of claims 1 to 4, characterized in that: The steps include: S1. depositing a layer of silicon dioxide as a gate oxide layer (3) on the surface of a silicon substrate through a thermal oxidation process, wherein the thickness of the gate oxide layer (3) is in the range of several tens of nanometers; S2, doping the area below the gate (4) to form a conductive medium (5); S3, using ion implantation technology to form n-type or p-type doped regions on the silicon substrate, and controlling the doping concentration to optimize the switching performance of the VDMOSFET device; S4, depositing a layer of metal on the source and drain regions using evaporation or sputtering technology to form electrodes; S5, depositing a metal layer in the gate region to form a gate electrode, and defining the shape of the gate through a photolithography process to form the gate electrode; S6. Perform surface cleaning to remove impurities and perform electrical performance testing on the VDMOSFET device.

6. The method for preparing a VDMOSFET with low switching loss according to claim 5, characterized in that: In the step S2, a U-shaped diffusion layer (11) is formed at the edge of the conductive medium (5) by ion implantation.

7. The method for preparing a VDMOSFET with low switching loss according to claim 5, characterized in that: In the step S4, the deposited metal is one of aluminum and titanium, and an annealing treatment is performed.

8. The method for preparing a VDMOSFET with low switching loss according to claim 5, characterized in that: In step S6, based on the thermal resistance of the VDMOSFET device, the maximum voltage that the VDMOSFET device can withstand between the metal drain (1) and the metal source (2), and the energy loss caused by switching the VDMOSFET device from the on state to the off state, there are: In the formula, Indicates the electrical performance qualification coefficient of the sampled VDMOSFET devices, It indicates the change in resistance of the VDMOSFET device when the standard temperature rises by 70°C. VD is the maximum voltage that a MOSFET device can withstand between the metal drain (1) and the metal source (2). Represents the energy loss caused by the VDMOSFET device switching from the on state to the off state.

9. The method for preparing a VDMOSFET with low switching loss according to claim 8, characterized in that: when When , it means that the electrical performance of the sampled VDMOSFET device is qualified; when When , it means that the electrical performance of the sampled VDMOSFET device is unqualified.

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