SiC lateral JFET device and manufacturing method thereof
By introducing a high doping concentration gate buffer layer and gate metal compound layer into the SiC transverse JFET device, the problem of low drain breakdown voltage of existing devices is solved, and the performance and breakdown voltage of the device are improved.
Patent Information
- Application Number
- CN202411899899.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-20
- Publication Date
- 2025-03-28
AI Technical Summary
The existing SiC transverse JFET devices have a low drain breakdown voltage in the off state, which affects device performance.
A gate buffer layer is introduced in the SiC transverse JFET device, with a doping concentration greater than the doping concentration of the gate implantation region, and a gate metal compound layer is formed to electrically contact the gate buffer layer.
The highly doped gate buffer layer forms good ohmic contact with the gate implant region, which improves the performance of the device and increases the breakdown voltage between the drift region and the gate implant region, thereby increasing the drain breakdown voltage.
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Figure CN119730338A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to semiconductor technology, and more particularly to a SiC lateral JFET device and a method for manufacturing the same. Background Art
[0002] SiC lateral JFET device (Junction Field-Effect Transistor) is a semiconductor device that is very suitable for use as a radio frequency amplifier (RF PA). An existing JFET device such as Figure 1 As shown, the device includes: a substrate 101, a P+ epitaxial layer 102, a P- epitaxial layer 103, a drift region 104, a drain injection region 105, a drain 106, a source 107, a first source contact region 108, a channel region 109, a gate 110, a second source contact region 111, an oxide layer 206, etc.
[0003] When the above device is in the off state, the pressure on the drain is achieved by the reverse bias of the three PN junctions of the drift region 104-gate 110, the drift region 104-source 107, and the drift region 104-epitaxial layer 103. If the breakdown voltage of any of the three junctions is very low, it will affect the final drain breakdown voltage. The gate 110 is generally a p-type region formed by injection, and this region needs to form a good ohmic contact, that is, the injection concentration of this region must be very high, which will reduce the breakdown voltage of the junction of the drift region 104-gate 110, resulting in a decrease in the drain breakdown voltage of the device, so that the performance of the device cannot meet the requirements. Summary of the invention
[0004] In order to solve one of the above technical defects, a SiC lateral JFET device and a manufacturing method thereof are provided in an embodiment of the present application.
[0005] According to a first aspect of an embodiment of the present application, a SiC lateral JFET device is provided, comprising:
[0006] substrate;
[0007] an epitaxial layer, formed on the substrate;
[0008] A gate injection region is formed in the epitaxial layer and is located at an upper portion of the epitaxial layer;
[0009] A gate buffer layer is formed on the gate injection region and is in electrical contact with the gate injection region, wherein the doping concentration of the gate buffer layer is greater than the doping concentration of the gate injection region;
[0010] The gate metal compound layer is formed on the gate buffer layer and is in electrical contact with the gate buffer layer.
[0011] According to a second aspect of an embodiment of the present application, a method for manufacturing a SiC lateral JFET device is provided, comprising:
[0012] forming an epitaxial layer on the substrate;
[0013] forming a gate implantation region at an upper portion of the epitaxial layer;
[0014] forming a gate buffer layer on the gate injection region, the gate buffer layer being in electrical contact with the gate injection region, and the doping concentration of the gate buffer layer being greater than the doping concentration of the gate injection region;
[0015] A gate metal compound layer is formed on the gate buffer layer, and the gate metal compound layer is in electrical contact with the gate buffer layer.
[0016] The technical solution provided by the embodiment of the present application is to form an epitaxial layer on the substrate, to form a gate injection region in the upper part of the epitaxial layer, to form a gate buffer layer on the gate injection region and to be in electrical contact with the gate injection region, and to form a gate buffer layer with a doping concentration greater than that of the gate injection region; and to form a gate metal compound layer on the gate buffer layer and to be in electrical contact with the gate buffer layer. The doping concentration of the gate buffer layer is greater than that of the gate injection region, and is heavily doped, so that a good ohmic contact is formed between the gate buffer layer and the gate injection region, thereby improving the performance of the device, and the gate injection region does not need to be heavily doped, thereby increasing the breakdown voltage between the drift region and the gate injection region, thereby increasing the drain breakdown voltage. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:
[0018] Figure 1 It is a structural schematic diagram of a JFET device in the related art;
[0019] Figure 2 A schematic diagram of the structure of a SiC lateral JFET device provided in an embodiment of the present application;
[0020] Figure 3 A flow chart of a method for manufacturing a SiC lateral JFET device provided in an embodiment of the present application;
[0021] Figure 4 A schematic diagram of a structure in which epitaxial layers are sequentially formed on a substrate in a method for manufacturing a SiC lateral JFET device provided in an embodiment of the present application;
[0022] Figure 5 A schematic diagram of the structure of forming various regions in the epitaxial layer in the method for manufacturing a SiC lateral JFET device provided in an embodiment of the present application;
[0023] Figure 6 A schematic structural diagram of forming a drain metal compound layer and a source metal compound layer on the drain and the source, respectively, in the method for manufacturing a SiC lateral JFET device provided in an embodiment of the present application;
[0024] Figure 7 A schematic diagram of the structure of forming a gate buffer layer and a gate metal compound layer in the method for manufacturing a SiC lateral JFET device provided in an embodiment of the present application;
[0025] Figure 8 A schematic diagram of simulation results of a SiC lateral JFET device provided in an embodiment of the present application;
[0026] Fig. 9 An Id-Vg graph of a SiC lateral JFET device provided in an embodiment of the present application;
[0027] Fig.10 This is a breakdown voltage curve of the SiC lateral JFET device provided in an embodiment of the present application.
[0028] Reference numerals:
[0029] 1-substrate; 2-first epitaxial layer; 3-second epitaxial layer; 4-drift region; 5-drain injection region; 6-drain contact region; 7-body region; 8-body region contact region; 9-source contact region; 10-gate injection region; 11-channel region; 12-source metal compound layer; 13-source contact through hole; 14-drain metal compound layer; 15-drain contact through hole; 16-gate buffer layer, 161-first inclined section; 162-first field plate section; 17-gate metal compound layer; 18-gate contact through hole; 19-insulating layer; 20-field plate; 21-metal electrode layer; 22-back hole. DETAILED DESCRIPTION
[0030] In order to make the technical solutions and advantages in the embodiments of the present application more clearly understood, the exemplary embodiments of the present application are further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than an exhaustive list of all the embodiments. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.
[0031] This embodiment provides a SiC lateral JFET device, such as Figure 2 As shown, the device includes: a substrate 1 , an epitaxial layer, a gate implantation region 10 , a gate buffer layer 16 and a gate metal compound layer 17 .
[0032] Wherein, the substrate 1 is a silicon carbide substrate, and the epitaxial layer is formed on the upper surface of the substrate 1. The conductivity type of the substrate 1 is opposite to that of the epitaxial layer, for example, the substrate 1 is n-type and the epitaxial layer is p-type; or the substrate 1 is p-type and the epitaxial layer is n-type. In this embodiment, the substrate 1 is an n+ substrate, and the epitaxial layer includes a p+-type first epitaxial layer 2 and a p-type second epitaxial layer 3, wherein the first epitaxial layer 2 is formed on the upper surface of the substrate 1, and the second epitaxial layer 3 is formed on the upper surface of the first epitaxial layer 2.
[0033] The gate implantation region 10 is formed in the epitaxial layer and located at the upper part of the epitaxial layer, specifically, formed in the second epitaxial layer 3 and located at the upper part of the second epitaxial layer 3. The gate implantation region 10 is located in the middle of the device.
[0034] In addition, a channel region 11 is provided below the gate injection region 10, and a body region 7 is provided below the channel region 11, and the body region 7 extends to one side edge of the device in the lateral direction. A body region contact region 8 and a source contact region 9 are also formed above the body region 7. Furthermore, a drift region 4 is also formed in the upper part of the second epitaxial layer 3. Based on the above scheme, when the substrate 1 is an n+ substrate, the drift region 4 is n-type. The drain injection region 5 is located at the other side edge of the device and is formed on the upper part of the drift region 4. The drain contact region 6 is formed in the drain injection region 5 and is located on the upper part of the drain injection region 5.
[0035] The gate buffer layer 16 is formed on the upper surface of the gate injection region 10, and the doping concentration of the gate buffer layer 16 is greater than the doping concentration of the gate injection region 10, so that a good ohmic contact is formed between the gate buffer layer 16 and the gate injection region 10. The gate metal compound layer 17 is formed on the gate buffer layer 16 and is in electrical contact with the gate buffer layer 16.
[0036] Specifically, after each region is formed by implanting into the epitaxial layer, an insulating layer 19 is grown on the epitaxial layer, and after a certain thickness is grown, holes are punched and filled with metal to form a gate buffer layer 16, a gate metal compound layer 17, a drain metal compound layer 14, and a source metal compound layer 12. The drain metal compound layer 14 is located on the upper surface of the drain contact region 6 and is in electrical contact with the drain contact region 6. The source metal compound layer 12 is located on the upper surface of the body contact region 8 and the source contact region 9 and is in electrical contact with the body contact region 8 and the source contact region 9.
[0037] In addition, according to the structure of the preset device, in the process of growing the insulating layer 19, a source contact through hole 13, a drain contact through hole 15, and a gate contact through hole 18 are respectively formed through a development and etching process. The source contact through hole 13 extends downward to be in electrical contact with the source metal compound layer 12, the drain contact through hole 15 extends downward to be in electrical contact with the drain metal compound layer 14, and the gate contact through hole 18 extends downward to be in electrical contact with the gate metal compound layer 17.
[0038] In addition, a metal electrode layer 21 is formed on the upper portion of the insulating layer 19 to serve as extraction electrodes of the source, drain, and gate injection regions, respectively. Figure 2 Only the metal electrode layer 21 corresponding to the source is marked. A back hole 22 is also provided on the side of the device where the source is provided. The back hole 22 penetrates from the metal electrode layer 21 corresponding to the source all the way to the substrate 1, so that the source is grounded through the back hole.
[0039] The technical solution provided in this embodiment is to form an epitaxial layer on the substrate, to form a gate injection region in the upper part of the epitaxial layer, to form a gate buffer layer on the gate injection region and to be in electrical contact with the gate injection region, and to form a gate buffer layer with a doping concentration greater than that of the gate injection region; and to form a gate metal compound layer on the gate buffer layer and to be in electrical contact with the gate buffer layer. The doping concentration of the gate buffer layer is greater than that of the gate injection region, and is heavily doped, so that a good ohmic contact is formed between the gate buffer layer and the gate injection region, thereby improving the performance of the device, and the gate injection region does not need to be heavily doped, thereby increasing the breakdown voltage between the drift region and the gate injection region, thereby increasing the drain breakdown voltage.
[0040] The gate metal compound layer 17 , the source metal compound layer 12 , and the drain metal compound layer 14 may be compounds of metals such as aluminum Al and titanium Ti, or gold Au may be doped into the compounds.
[0041] The gate buffer layer 16 may be a polycrystalline silicon carbide layer, which has the advantage of high p-type doping activation concentration and can form a good electrical contact with the gate injection region 10 composed of single-crystalline silicon carbide, thereby further improving device performance.
[0042] In the above scheme, the width of the gate buffer layer 16 is equal to that of the gate injection region 10, so that the two sides of the gate buffer layer 16 are aligned with the gate injection region 10 to form a good ohmic contact. The gate buffer layer 16 extends in the longitudinal direction. Figure 2 The left and right directions in the middle, and the vertical direction is Figure 2 The vertical direction is perpendicular to both the horizontal and vertical directions, that is, the direction perpendicular to the paper surface.
[0043] The thickness of the gate buffer layer 16 is 0.1 micrometer to 1 micrometer, and specifically 0.1 micrometer to 0.3 micrometer.
[0044] On the basis of the above technical solution, one end of the gate buffer layer 16 is extended to form a field plate portion, which can improve the depletion performance of the device and further increase the breakdown voltage.
[0045] One implementation mode is: the field plate portion includes: a first inclined section 161 and a first field plate section 162, the first inclined section is connected to the gate buffer layer 16 and extends obliquely upward, and the first field plate section 162 is connected to the first inclined section 161 and extends in the lateral direction. The first inclined section 161 and the first field plate section 162 are both formed in the process of growing the insulating layer 19. The first inclined section 161 and the first field plate section 162 can adjust the electric field distribution of the PN junction formed between the drift region 4, the drain injection region 5, the drain contact region 6, the body region 7, the body region contact region 8, the source contact region 9, and the gate injection region 10 in the depletion state, thereby improving the breakdown voltage at this position, thereby improving the drain breakdown voltage of the entire device.
[0046] Furthermore, the shape of the gate metal compound layer 17 matches the gate buffer layer 16, for example: one end of the gate metal compound layer 17 extends to form a second inclined section and a second field plate section, the second inclined section is connected to the second contact section and extends obliquely upward, and the inclination angle is the same as that of the first inclined section 161; the second field plate section is connected to the second inclined section and extends laterally to be located on the upper surface of the first field plate section 162.
[0047] On the basis of the above technical solution, this embodiment also provides a method for manufacturing a SiC lateral JFET device, such as Figure 3 As shown, the method includes:
[0048] Step 10: forming an epitaxial layer on the substrate.
[0049] like Figure 4 As shown, the substrate 1 is a heavily doped n-type substrate. A heavily doped p-type first epitaxial layer 2 is grown on the upper surface of the substrate 1 , and then a lightly doped p-type second epitaxial layer 3 is grown on the upper surface of the first epitaxial layer 2 .
[0050] Step 20: forming a gate implantation region in the upper portion of the epitaxial layer.
[0051] Specific as Figure 5 As shown, an n-type drift region 4, a drain implantation region 5, a drain contact region 6, a body region 7, a body contact region 8, a source contact region 9, a channel region 11 and a gate implantation region 10 are formed in the second epitaxial layer 3 by an implantation process.
[0052] Afterwards, if Figure 6 As shown, a source metal compound layer 12 is formed on the upper surface of the body contact region 8 and the source contact region 9, and a drain metal compound layer 14 is formed on the upper surface of the drain contact region 6. In this step, an insulating layer can be grown on the upper surface of the second epitaxial layer 3, and when it grows to a certain thickness, it is exposed, developed, and etched to form a through hole, and a corresponding metal compound layer is deposited in the through hole.
[0053] Step 30 : forming a gate buffer layer on the gate injection region, wherein the gate buffer layer is in electrical contact with the gate injection region, and the doping concentration of the gate buffer layer is greater than the doping concentration of the gate injection region.
[0054] Step 40 : forming a gate metal compound layer on the gate buffer layer, wherein the gate metal compound layer is in electrical contact with the gate buffer layer.
[0055] Based on the above structure, Figure 7 As shown, a gate buffer layer 16 , a gate metal compound layer 17 and a field plate 20 are formed in the insulating layer above the gate injection region 10 through multiple deposition, photolithography and etching.
[0056] Further, by multiple deposition, polishing, and etching methods, a source contact through hole 13, a drain contact through hole 15, a gate contact through hole 18, a metal electrode layer 21, and a back hole 22 are formed to obtain Figure 2 The structure shown.
[0057] In the above scheme, a gate buffer layer is formed on the gate injection region and is in electrical contact with the gate injection region, and the doping concentration of the gate buffer layer is greater than the doping concentration of the gate injection region; a gate metal compound layer is formed on the gate buffer layer and is in electrical contact with the gate buffer layer. The doping concentration of the gate buffer layer is greater than the doping concentration of the gate injection region, and is heavily doped, so that a good ohmic contact is formed between the gate buffer layer and the gate injection region, thereby improving the performance of the device, and the gate injection region does not need to be heavily doped, thereby increasing the breakdown voltage between the drift region and the gate injection region, thereby increasing the drain breakdown voltage.
[0058] The gate buffer layer 16 may be a polycrystalline buffer layer with a doping concentration greater than 1e19 cm 3 , can make good ohmic contact with the gate injection region 10, ensuring good contact of the gate injection region. And it can also improve the breakdown voltage. The gate injection region 10 no longer needs a high injection concentration, and the concentration of the gate injection region 10 is lower than 1e17cm 3 That's it.
[0059] Furthermore, the gate injection region 10 also includes an extended field plate portion, which can improve the depletion performance of the device, thereby further increasing the breakdown voltage.
[0060] like Figure 8 As shown, the above technical solution is used for process simulation through simulation software, and the simulation result of the device structure being normal can be obtained, indicating that the above solution can be used to manufacture actual devices on a conventional process production line.
[0061] like Fig. 9As shown, it can be seen from the Id-Vg curve that when the gate voltage of the device is lower than a certain value (about -8V), the device is turned off; when the gate voltage is higher than a certain value (about -8V), the drain current increases with the increase of the gate voltage, and the overall device can be turned on and off, with good gate control capability.
[0062] like Fig.10 As shown, the drain breakdown voltage curve (green) of the gate injection region structure of the device provided in this embodiment is compared with the drain breakdown voltage curve (red) of the traditional device. The breakdown voltage of the traditional device is about 638V, and the breakdown voltage of the device provided in this embodiment is about 691V. It can be seen that the breakdown voltage of the device can be improved by about 50V.
[0063] In addition, the bandgap width of SiC used in this application is several times larger than that of Si. Under the same operating voltage, the size of SiC devices is expected to be reduced to a fraction of that of silicon devices, and the on-resistance can be reduced several times. Secondly, unlike MOS devices (Metal-Oxide-Semiconductor Field-Effect Transistor), the current conduction of JFET devices is inside the device and will not be affected by the high defect density of the SiC-oxide interface, thereby achieving a higher saturation current density and, in turn, a higher saturation output power. In addition, SiC materials have a high thermal conductivity and have a natural advantage in solving heat dissipation problems under high power output conditions.
[0064] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.
[0065] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.
[0066] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or can communicate with each other; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0067] Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.
[0068] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.
Claims
1. A SiC lateral JFET device, characterized in that: include: substrate; an epitaxial layer, formed on the substrate; A gate injection region is formed in the epitaxial layer and is located at an upper portion of the epitaxial layer; A gate buffer layer is formed on the gate injection region and is in electrical contact with the gate injection region, wherein the doping concentration of the gate buffer layer is greater than the doping concentration of the gate injection region; The gate metal compound layer is formed on the gate buffer layer and is in electrical contact with the gate buffer layer.
2. The SiC lateral JFET device according to claim 1, characterized in that: The gate buffer layer is a polycrystalline silicon carbide layer.
3. The SiC lateral JFET device according to claim 1, characterized in that: The width of the gate buffer layer is equal to that of the gate injection region.
4. The SiC lateral JFET device according to claim 3, characterized in that: The gate buffer layer extends in a longitudinal direction.
5. The SiC lateral JFET device according to claim 3, characterized in that: The thickness of the gate buffer layer is 0.1 micrometer to 1 micrometer.
6. The SiC lateral JFET device according to claim 1, characterized in that: One end of the gate buffer layer extends to form a field plate portion.
7. The SiC lateral JFET device according to claim 6, characterized in that: The field plate portion includes: a first inclined section and a first field plate section. The first inclined section is connected to the gate buffer layer and extends obliquely upward. The first field plate section is connected to the first inclined section and extends in the transverse direction.
8. The SiC lateral JFET device according to claim 7, characterized in that: One end of the gate metal compound layer extends to form a second inclined section and a second field plate section, the second inclined section is connected to the second contact section and extends obliquely upward, and the inclination angle is the same as that of the first inclined section; the second field plate section is connected to the second inclined section and extends laterally and is located on the upper surface of the first field plate section.
9. The SiC lateral JFET device according to claim 1, characterized in that: An insulating layer is formed on the epitaxial layer, and a gate metal hole is arranged in the insulating layer. The metal hole extends downward to be in electrical contact with the gate metal compound layer.
10. A method for manufacturing a SiC lateral JFET device, characterized in that: include: forming an epitaxial layer on the substrate; forming a gate implantation region at an upper portion of the epitaxial layer; forming a gate buffer layer on the gate injection region, the gate buffer layer being in electrical contact with the gate injection region, and the doping concentration of the gate buffer layer being greater than the doping concentration of the gate injection region; A gate metal compound layer is formed on the gate buffer layer, and the gate metal compound layer is in electrical contact with the gate buffer layer.