Transistor structure and electronic equipment

Abstract

The invention discloses a transistor structure and an electronic device. The transistor structure comprises a substrate, a transistor module and a clamping module, wherein the transistor module and the clamping module are located on one side of the substrate. One side of the substrate is provided with a buffer layer which is located on the substrate and comprises a first buffer layer located on the transistor module and a second buffer layer located on the clamping module; the potential barrier layer is located on the buffer layer and comprises a first potential barrier layer located on the transistor module and a second potential barrier layer located on the clamping module; the cap layer is located on the barrier layer and comprises a first cap layer located on the transistor module and a second cap layer located on the clamping module; the first cap layer is arranged between the source electrode and the drain electrode at an interval; the connecting electrode is in ohmic contact with the first barrier layer, and the grid is in Schottky contact with the first barrier layer; the anode and the cathode are located on the side, away from the buffer layer, of the barrier layer and located on the clamping module, the cathode is electrically connected with the grid electrode, and the anode is electrically connected with the connecting electrode. The transistor structure can improve the gate reliability.

Description

Technical Field

[0001] The present invention relates to the technical field of display devices, and in particular to a transistor structure and electronic equipment. Background Art

[0002] Thanks to its excellent material properties, gallium nitride (GaN)-based power electronic devices can surpass the performance limits of silicon (Si) and silicon carbide (SiC) devices to achieve high-efficiency, miniaturized, and high-power density power electronic systems. As an enhancement-mode device, the p-type gate GaN high electron mobility transistor (HEMT) is leading the commercialization of GaN power devices with its normally-off characteristics. However, due to a series of reliability issues with GaN power device materials, p-type gate GaN HEMTs have not yet been able to replace traditional silicon-based devices on a large scale. The gate of the GaN HEMT determines the on and off of the device, and its stability directly affects the stable operation of the device. Therefore, the reliability of the gate of GaN power devices is of particular concern.

[0003] At present, the research on gate reliability issues of p-type gate GaN HEMT mainly includes two categories: gate safe working voltage and threshold voltage stability. Gate safe working voltage refers to the gate voltage of GaN HEMT devices for long-term reliable operation. Under a ten-year working life, the voltage of P-type gate GaN HEMT stable operation is usually only 7V, while the gate working voltage recommended by GaN manufacturers is usually greater than 5V. The low gate working life seriously limits the freedom of gate drive circuit design, so efforts should be made to optimize the gate working life of GaN HEMT; on the other hand, there are various defects in the gallium nitride material in the cap layer. Under voltage stress, carriers are captured by these defects and cannot be released in time, which will cause the device threshold voltage to drift, which may lead to problems such as device mis-conduction and increased switching loss. Summary of the invention

[0004] The present invention provides a transistor structure and an electronic device. The transistor structure can increase the working life of a gate and can make the threshold voltage more stable, thereby improving the reliability of the gate.

[0005] In order to achieve the above object, the present invention provides the following technical solutions:

[0006] A transistor structure comprises a substrate, a transistor module and a clamping module located on one side of the substrate, wherein an electrical isolation region exists between the transistor module and the clamping module;

[0007] Wherein, one side of the substrate has:

[0008] A buffer layer, located on the substrate, including a first buffer layer located in the transistor module and a second buffer layer located in the clamping module;

[0009] A barrier layer, located on a side of the buffer layer away from the substrate, including a first barrier layer located in the transistor module and a second barrier layer located in the clamping module;

[0010] A capping layer, located on a side of the barrier layer away from the buffer layer, comprising a first capping layer located in the transistor module and a second capping layer located in the clamping module;

[0011] A source electrode and a drain electrode are located on a side of the barrier layer away from the buffer layer and located in the transistor module, the source electrode and the drain electrode are in ohmic contact with the first barrier layer, and the first cap layer is spaced between the source electrode and the drain electrode;

[0012] A connecting electrode and a gate are arranged at intervals on a side of the cap layer away from the barrier layer and located in the transistor module, the connecting electrode is in ohmic contact with the first cap layer, and the gate is in Schottky contact with the first cap layer;

[0013] an anode and a cathode, located on a side of the barrier layer away from the buffer layer and located in the clamping module, the cathode being electrically connected to the gate, and the anode being electrically connected to the connecting electrode;

[0014] The voltage clamping module is used to clamp the voltage between the anode and the cathode within a preset voltage regulation value.

[0015] Optionally, the clamping module comprises a first clamping unit; wherein,

[0016] The second buffer layer includes a first sub-buffer layer located in the first clamping unit;

[0017] The second barrier layer includes a first sub-barrier layer located in the first clamping unit;

[0018] The second capping layer comprises a first sub-capping layer located in the first clamping unit, and the first sub-capping layer is arranged between the anode and the cathode;

[0019] Also includes a first electrode, a second electrode and a third electrode located in the first clamping unit;

[0020] The first electrode, the second electrode, the anode, the cathode, the source and the drain are arranged in the same layer, the first electrode is arranged at a distance from the anode on a side away from the first sub-capping layer, the second electrode is arranged at a distance from the cathode on a side away from the first sub-capping layer, and the first electrode and the second electrode are in ohmic contact with the first sub-barrier layer;

[0021] The third electrode is disposed in the same layer as the gate, the third electrode is in Schottky contact with the first sub-cap layer, and the third electrode is electrically connected to the first electrode and the second electrode.

[0022] Optionally, the clamping module includes a second clamping unit, and the second clamping unit includes N sub-clamping units, where N is an integer greater than or equal to 1; wherein,

[0023] The second buffer layer includes a second sub-buffer layer located in the sub-clamping unit;

[0024] The second barrier layer includes a second sub-barrier layer located in the sub-clamping unit;

[0025] The second capping layer comprises a second sub-capping layer located in the sub-clamping unit;

[0026] Also includes a fourth electrode, a fifth electrode and a sixth electrode located at the sub-clamping unit;

[0027] The fourth electrode and the fifth electrode are arranged in the same layer as the source and the drain, the fourth electrode and the fifth electrode are located on both sides of the second sub-cap layer and are in ohmic contact with the second sub-barrier layer, and the fifth electrode is spaced apart from the second sub-cap layer;

[0028] The sixth electrode is disposed in the same layer as the gate, the sixth electrode is in Schottky contact with the second sub-cap layer, and is in ohmic contact with the second sub-barrier layer through the fourth electrode;

[0029] When N=1, the sixth electrode of the sub-clamping unit is the cathode of the second clamping unit, and the fifth electrode of the sub-clamping unit is the anode of the second clamping unit;

[0030] When N≥2, the second sub-buffer layer and the second sub-barrier layer of each sub-clamping unit are electrically isolated, the N sub-clamping units are connected in series in sequence, the sixth electrode of the first sub-clamping unit is the cathode of the second clamping unit, the fifth electrode of the (N-1)th sub-clamping unit is connected to the sixth electrode of the Nth sub-clamping unit, and the fifth electrode of the Nth sub-clamping unit is the anode of the second clamping unit.

[0031] Optionally, the clamping module includes the first clamping unit and the second clamping unit;

[0032] The anode of the first clamping unit is the anode of the clamping module, and the cathode of the first clamping unit is the cathode of the clamping module;

[0033] The third electrode of the first clamping unit is connected to the first electrode through the second clamping unit, a cathode of the second clamping unit is connected to the third electrode, and an anode of the second clamping unit is connected to the first electrode.

[0034] Optionally, a passivation layer and a routing layer are also included;

[0035] The passivation layer is located on a side of the gate and the connecting electrode facing away from the substrate;

[0036] The wiring layer is located on a side of the passivation layer away from the substrate, and the wiring layer includes a first connecting line and a second connecting line;

[0037] The cathode of the voltage clamping module is connected to the grid through a first connection line, and the anode of the voltage clamping module is connected to the connection electrode through a second connection line.

[0038] Optionally, a material of the gate electrode is different from a material of the connecting electrode.

[0039] Optionally, the material of the buffer layer includes gallium nitride, the material of the barrier layer includes aluminum gallium nitride, and the material of the cap layer includes p-type gallium nitride.

[0040] Optionally, the material of the source and drain electrodes includes at least one of titanium, aluminum, gold, nickel and titanium nitride;

[0041] The material of the gate includes at least one of titanium nitride, titanium, nickel and gold;

[0042] The material of the connection electrode includes at least one of nickel, gold and titanium.

[0043] Optionally, the buffer layer includes a plurality of sub-film layers stacked sequentially on the substrate;

[0044] The sub-film layer on the side of the buffer layer away from the substrate is a channel layer, and the channel layer and the barrier layer form a heterostructure.

[0045] Optionally, an insertion layer is provided between the buffer layer and the barrier layer, a material of the insertion layer comprises aluminum nitride, and the insertion layer located in the transistor module is electrically isolated from the insertion layer located in the clamping module.

[0046] Optionally, the electrical isolation region between the transistor module and the voltage clamping module is electrically isolated by ion implantation or trench etching.

[0047] The present invention also includes an electronic device, comprising any one of the transistor structures provided in the above technical solutions.

[0048] The present invention provides a transistor structure and an electronic device, in which a first buffer layer, a first barrier layer, a first cap layer, a source electrode, a drain electrode, a connecting electrode and a gate electrode are located in a transistor module, and a second buffer layer, a second barrier layer, a second cap layer, an anode electrode and a cathode electrode are located in a voltage clamping module, and the transistor module and the voltage clamping module are prepared in the same layer; since the gate electrode of the transistor module is connected to the cathode electrode of the voltage clamping module, the connecting electrode of the transistor module is connected to the anode electrode of the voltage clamping module; when the voltage applied to the gate electrode exceeds a preset value, the voltage clamping module can clamp the voltage on the gate electrode within a preset voltage regulation value to avoid excessive voltage on the gate electrode, thereby improving the working life of the gate electrode; and, since there is ohmic contact between the connecting electrode and the first capping layer, the traps of the first capping layer that capture electrons will be quickly recombined by the holes injected by the connecting electrode, thereby avoiding the problem that the traps of the first capping layer capture electrons and cannot be released in time, therefore, the threshold voltage of the transistor structure is no longer offset, so that the threshold voltage becomes more stable, thereby ultimately improving the reliability of the gate electrode of the transistor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 A schematic diagram of a transistor structure provided by an embodiment of the present invention;

[0050] Figure 2 An equivalent schematic diagram of a transistor structure provided by an embodiment of the present invention;

[0051] Figure 3 An equivalent circuit diagram of a transistor structure provided by an embodiment of the present invention;

[0052] Figure 4 A volt-ampere characteristic curve diagram of a voltage stabilizing diode provided in an embodiment of the present invention;

[0053] Figure 5 An equivalent circuit diagram of a transistor structure provided by an embodiment of the present invention;

[0054] Figure 6 An equivalent schematic diagram of a transistor structure provided by an embodiment of the present invention;

[0055] Figure 7 An equivalent circuit diagram of a first clamping unit provided by an embodiment of the present invention;

[0056] Figure 8 A schematic structural diagram of a second clamping unit provided in an embodiment of the present invention;

[0057] Fig. 9 An equivalent circuit diagram of a second clamping unit provided by an embodiment of the present invention;

[0058] Fig.10 An equivalent circuit diagram of a clamping module provided by an embodiment of the present invention;

[0059] Fig.11 A schematic diagram of a transistor structure provided by an embodiment of the present invention;

[0060] Fig.12 A schematic plan view of a transistor structure provided by an embodiment of the present invention;

[0061] Fig.13 A schematic plan view of a transistor structure provided by an embodiment of the present invention;

[0062] Figures 14 to 21 A schematic diagram of a manufacturing process of a transistor structure provided by an embodiment of the present invention.

[0063] icon:

[0064] 1-substrate; 2-transistor module; 21-first buffer layer; 22-first barrier layer; 23-first cap layer; S-source; D-drain; G-gate; 24-connecting electrode; 25-passivation layer; 26-routing layer; L1-first connecting line; L2-second connecting line; L3-third connecting line; L4-fourth connecting line; 3-clamping module; 31-first clamping unit; 311-first sub-buffer layer; 312-first sub-barrier layer; 313-first sub-cap layer; 314-first electrode; 315-second electrode; 316-third electrode; A-anode; C-cathode; 32-second clamping unit; 320-sub-clamping unit; 321-second sub-buffer layer; 322-second sub-barrier layer; 323-second sub-cap layer; 324-fourth electrode; 325-fifth electrode; 326-sixth electrode. DETAILED DESCRIPTION

[0065] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0066] Please refer to Figure 1 and Figure 2 , the present invention provides a transistor structure, including a substrate 11 and a transistor module 2 and a clamping module 3 located on one side of the substrate 11, and an electrical isolation region exists between the transistor module 2 and the clamping module 3;

[0067] Wherein, one side of the substrate 1 has:

[0068] A buffer layer, located on the substrate 1, including a first buffer layer 21 located in the transistor module 2 and a second buffer layer located in the clamping module 3;

[0069] The barrier layer is located on the side of the buffer layer facing away from the substrate 1, including a first barrier layer 22 located in the transistor module 2 and a second barrier layer located in the clamping module 3;

[0070] The cap layer is located on the side of the barrier layer away from the buffer layer, including a first cap layer 23 located in the transistor module 2 and a second cap layer located in the clamping module 3;

[0071] The source electrode S and the drain electrode D are located on the side of the barrier layer away from the buffer layer and located in the transistor module 2. The source electrode S and the drain electrode D are in ohmic contact with the first barrier layer 22. The first cap layer 23 is disposed between the source electrode S and the drain electrode D.

[0072] The connecting electrode 24 and the gate G are spaced apart and arranged on the side of the cap layer away from the barrier layer and located in the transistor module 2, the connecting electrode 24 is in ohmic contact with the first cap layer 23, and the gate G is in Schottky contact with the first cap layer 23;

[0073] The anode A and the cathode C are located on the side of the barrier layer away from the buffer layer and located in the clamping module 3 , the cathode C is electrically connected to the gate G, and the anode A is electrically connected to the connecting electrode 24 ;

[0074] The voltage clamping module 3 is used to clamp the voltage between the anode A and the cathode C within a preset voltage regulation value.

[0075] In the transistor structure provided by the embodiment of the present invention, the first buffer layer 21, the first barrier layer 22, the first cap layer 23, the source S, the drain D, the connecting electrode 24 and the gate G are located in the transistor module 2, and the second buffer layer, the second barrier layer, the second cap layer, the anode A and the cathode C are located in the clamping module 3. The transistor module 2 and the clamping module 3 are prepared in the same layer. A two-dimensional electron gas is formed at the interface of the heterojunction formed by the first buffer layer 21 and the first barrier layer 22 in the transistor module 2. The first cap layer 23 is used to deplete the two-dimensional electron gas at the heterojunction interface between the first buffer layer 21 and the first barrier layer 22. The gate G forms a Schottky contact with the first cap layer 23. The concentration of the two-dimensional electron gas at the heterojunction interface between the first buffer layer 21 and the first barrier layer 22 can be controlled by adjusting the voltage applied to the gate G, thereby controlling the on and off states of the source S and the drain D.

[0076] Among them, since the gate G of the transistor module 2 is connected to the cathode C of the clamping module 3, the connecting electrode 24 of the transistor module 2 is connected to the anode A of the clamping module 3; when the voltage applied to the gate G exceeds the preset value, the clamping module 3 can clamp the voltage on the gate G within the preset voltage regulation value to avoid excessive voltage on the gate G, which can improve the working life of the gate G; and, since the connecting electrode 24 is in ohmic contact with the first capping layer 23, the traps that capture electrons in the first capping layer 23 will quickly be recombined by the holes injected by the connecting electrode 24, which can avoid the problem that the traps in the first capping layer 23 capture electrons and cannot be released in time. Therefore, the threshold voltage of the transistor structure is no longer offset, so that the threshold voltage becomes more stable, and the reliability of the gate G of the transistor structure can be ultimately improved.

[0077] In the embodiment of the present invention, the voltage clamping module 3 may be any two-port module that exhibits voltage stabilization characteristics, which is not limited here and is determined according to actual conditions.

[0078] In the above transistor structure, if the gate of the transistor module 2 is not connected to the clamping module 3, the gate G of the transistor module 2 can be equivalent to an anti-parallel connection of a Schottky diode (formed by the Schottky contact between the gate G and the first cap layer 23) and a PIN diode (formed by the heterojunction of the first cap layer 23, the first barrier layer 22 and the first buffer layer 21); when a voltage is applied to the gate G, the Schottky diode initially bears all the gate G voltage; when the PIN diode is turned on, the increased gate G voltage will also fall on the reverse-biased Schottky diode until the gate G voltage causes the gate G to break down.

[0079] In the embodiment of the present invention, Figure 2 As shown, the gate G is in Schottky contact with the first cap layer 23, and the contact interface between the gate G and the first cap layer 23 can be equivalent to a Schottky diode D1; the heterostructure formed by the first cap layer 23, the first barrier layer 23 and the first buffer layer 31 can be equivalent to a PIN diode D2; the clamping module 3 can be equivalent to a Zener diode D3; then in the transistor structure, the gate G structure can be equivalent to the anti-parallel connection of the Schottky diode D1 and the Zener diode D3. Therefore, in the above transistor structure, the equivalent circuit of the gate can be as follows Figure 3 As shown; Figure 4 : is the volt-ampere characteristic curve of the Zener diode D3. When the voltage between the anode and cathode of the Zener diode D3 exceeds the preset voltage value Vz, the current in the Zener diode D3 will increase sharply.

[0080] Specifically, when the voltage applied to the gate G increases from 0V to the preset voltage regulation value Vz, due to the voltage clamping characteristics of the voltage zener diode D3, the current on the voltage zener diode D3 will increase sharply, and the current on the corresponding PIN diode D2 will increase sharply, and the equivalent resistance of the PIN diode D2 is greater than the equivalent resistance of the voltage zener diode D3, so that the PIN diode D2 will bear a large voltage, so that the voltage across the anode and cathode of the voltage zener diode D3 is limited to the preset voltage regulation value, that is, the voltage across the Schottky diode D1 will be limited to the preset voltage regulation value Vz, and the voltage on the gate G will be limited to the preset voltage regulation value Vz, which can avoid excessive voltage on the gate G and improve the working life of the gate G. Compared with the prior art, the transistor structure provided in the embodiment of the present invention can have a higher safe working voltage.

[0081] In addition, since the connecting electrode 24 is in ohmic contact with the first cap layer 23, the structure of the clamping module 3, the connecting electrode 24 and the first cap layer 23 can be equivalent to a resistor R connected in parallel with the Schottky diode D1, and the equivalent circuit of the transistor structure can be as follows: Figure 5 As shown, the holes injected by the gate G into the first capping layer 23 are no longer restricted by the Schottky junction formed at the metal-semiconductor interface, and can be directly injected into the first capping layer 23. Therefore, the carriers captured by the defects of the gate G in the first capping layer 23 can be recombined in time, so that the threshold voltage of the gate G of the transistor structure can be more stable.

[0082] In the transistor structure provided by the embodiment of the present invention, the clamping module 3 may include a first clamping unit 31; wherein the second buffer layer may include a first sub-buffer layer 311 located in the first clamping unit 31; the second barrier layer may include a first sub-barrier layer 312 located in the first clamping unit 31; the second cap layer may include a first sub-cap layer 313 located in the first clamping unit 31, and the first sub-cap layer 313 is arranged between the anode A and the cathode C;

[0083] In addition, the transistor structure may further include a first electrode 314, a second electrode 315 and a third electrode 316 located in the first clamping unit 31; the first electrode 314, the second electrode 315, the anode A, the cathode C, the source S and the drain D are arranged in the same layer, the first electrode 314 is arranged at a distance on the side of the anode A away from the first sub-capping layer 313, the second electrode 315 is arranged at a distance on the side of the cathode C away from the first sub-capping layer 313, the first electrode 314 and the second electrode 315 are in ohmic contact with the first sub-barrier layer 312; the third electrode 316 is arranged in the same layer as the gate G, the third electrode 316 is in Schottky contact with the first sub-capping layer 313, and the third electrode 316 is electrically connected to the first electrode 314 and the second electrode 315;

[0084] The first sub-buffer layer 311 , the second sub-barrier layer 322 , the first sub-cap layer 313 , the anode A, the cathode C, the first electrode 314 , the second electrode 315 and the third electrode 316 constitute a first clamping unit 31 .

[0085] Specifically, in the first clamping unit 31, the first sub-buffer layer 311, the first sub-barrier layer 312, the first sub-cap layer 313, the first electrode 314, the second electrode 315 and the third electrode 316 form a structure of an enhancement-type transistor. A two-dimensional electron gas is formed at the interface of the heterojunction formed by the first sub-buffer layer 311 and the first sub-barrier layer 312. The first sub-cap layer 313 is used to deplete the two-dimensional electron gas at the heterojunction interface between the first sub-buffer layer 311 and the first sub-barrier layer 312. The voltage on the third electrode 316 can control the concentration of the two-dimensional electron gas at the heterojunction interface between the second buffer layer 311 and the second barrier layer 312, and further control the conduction and disconnection between the first electrode 314 and the second electrode 315.

[0086] like Figure 6 As shown, since the first electrode 314 and the anode A are in ohmic contact with the first sub-barrier layer 312, the connection between the anode A and the first electrode 314 can be equivalent to being connected through the first resistor R1; since the second electrode 315 and the cathode C are in ohmic contact with the first sub-barrier layer 312, the connection between the cathode C and the second electrode 315 can be equivalent to being connected through the second resistor R2; therefore, the equivalent circuit of the first clamping unit 31 can be as follows Figure 7 As shown, the equivalent circuit structure has the characteristics of a voltage-stabilizing diode. The equivalent circuit includes a first resistor R1, a second resistor R2 and an enhancement transistor M.

[0087] The clamping module 3 may be a first clamping unit 31, and the first clamping unit 31 is prepared in the same layer as the transistor module 2; Figure 1 As shown, when the voltage V between the cathode C and the anode A on the first clamping unit 31 is AC When rising from 0V, the resistors connected in series with the first resistor R1 and the second resistor R2 share the voltage V between the cathode C and the anode A. AC Since the voltage is less than the threshold voltage VTH of the enhancement transistor M, the enhancement transistor M remains in the off state, and the current between the anode A and the cathode C of the first clamping unit 31 is only determined by the values ​​of the first resistor R1 and the second resistor R2. At this time, the equivalent circuit of the transistor structure can be as follows: Figure 5 As shown; when V ACWhen R2 / (R1+R2) exceeds the threshold voltage VTH of the enhancement transistor M, the enhancement transistor M starts to conduct. At this time, the current between the anode A and the cathode C of the first clamping unit 31 is dominated by the current passing through the enhancement transistor M. At this time, the volt-ampere characteristic of the first clamping unit 31 exhibits a volt-ampere characteristic similar to that of a Zener diode. The first clamping unit 31 can clamp the voltage on the gate G at a preset regulated voltage value Vz. The preset regulated voltage value Vz between the anode A and the cathode C of the first clamping unit 31 is V AC R2 / (R1+R2) is equal to VTH. The equivalent circuit of the transistor structure can be Figure 3 shown.

[0088] In the embodiment of the present invention, Figure 8 As shown, the clamping module 3 may further include a second clamping unit 32, the second clamping unit 32 includes N sub-clamping units 320, N is an integer greater than or equal to 1; wherein the second buffer layer includes a second sub-buffer layer 321 located in the sub-clamping unit 320; the second barrier layer includes a second sub-barrier layer 322 located in the sub-clamping unit 320; the second cap layer includes a second sub-cap layer 323 located in the sub-clamping unit 320;

[0089] In addition, the transistor structure further includes a fourth electrode 324, a fifth electrode 325 and a sixth electrode 326 located in the sub-clamping unit 320; the fourth electrode 324 and the fifth electrode 325 are arranged in the same layer as the source electrode S and the drain electrode D, the fourth electrode 324 and the fifth electrode 325 are located on both sides of the second sub-cap layer 323, and are in ohmic contact with the second sub-barrier layer 322, and the fifth electrode 325 is arranged at intervals from the second sub-cap layer 323; the sixth electrode 326 is arranged in the same layer as the gate G, the sixth electrode 326 is in Schottky contact with the second sub-cap layer 323, and is in ohmic contact with the second sub-barrier layer 322 through the fourth electrode 324;

[0090] In the above transistor structure, the second sub-buffer layer 321 , the second sub-barrier layer 322 , the second sub-capping layer 323 , the fourth electrode 324 , the fifth electrode 325 and the sixth electrode 326 constitute a sub-clamping unit 320 , and N sub-clamping units 320 constitute a second clamping unit 32 .

[0091] When N=1, the sixth electrode 326 of the sub-clamping unit 320 may be the cathode C of the second clamping unit 32, and the fifth electrode 325 of the sub-clamping unit 320 may be the anode A of the second clamping unit 32;

[0092] When N≥2, the second sub-buffer layer 321 and the second sub-barrier layer 322 of each sub-clamping unit 320 are electrically isolated, and the N sub-clamping units 320 are connected in series in sequence. The sixth electrode 326 of the first sub-clamping unit 320 can be the cathode C of the second clamping unit 32, and the fifth electrode 325 of the (N-1)th sub-clamping unit 320 is connected to the sixth electrode 326 of the Nth sub-clamping unit 320, and the fifth electrode 325 of the Nth sub-clamping unit 320 can be the anode A of the second clamping unit 32.

[0093] A two-dimensional electron gas is formed at the interface of the heterojunction formed by the second sub-buffer layer 321 and the second sub-barrier layer 322 in the above-mentioned sub-clamping unit 320. The second sub-cap layer 323 is used to deplete the two-dimensional electron gas at the heterojunction interface between the second sub-buffer layer 321 and the second sub-barrier layer 322. The on and off states of the sub-clamping unit 320 can be controlled by controlling the voltage between the sixth electrode 326 and the fifth electrode 325. The sub-clamping unit 320 can be equivalent to a diode, and the threshold voltage of the sub-clamping unit 320 can be VON.

[0094] Specifically, the clamping module 3 may be a second clamping unit 32, and the N sub-clamping modules 320 in the second clamping unit 32 are all prepared on the same layer as the transistor module 2; when the second clamping unit 32 includes one sub-clamping unit 320, that is, when N=1, after the voltage between the anode and cathode of the second clamping unit 32 reaches VON, the volt-ampere characteristic of the sub-clamping unit 320 exhibits a volt-ampere characteristic similar to that of a Zener diode, and the voltage on the gate G can be clamped at Vz equal to VON;

[0095] When the second clamping unit 32 includes at least two sub-clamping units 320, that is, N ≥ 2, the equivalent circuit of the second clamping unit 32 can be a series connection of N diodes D4, such as Fig. 9 As shown; when the voltage between the anode A and the cathode C of the second clamping unit 32 reaches N×VON, the volt-ampere characteristic of the second clamping unit 32 exhibits a volt-ampere characteristic similar to that of a Zener diode, and can clamp the voltage on the gate G at a preset stabilization value Vz, Vz is equal to N×VON, which can increase the safe operating voltage of the transistor structure.

[0096] In the embodiment of the present invention, the clamping module 3 may include only the first clamping unit 31 ; may include only the second clamping unit 32 ; or may include both the first clamping unit 31 and the second clamping unit 32 .

[0097] For example, the clamping module 3 may include a first clamping unit 31 and a second clamping unit 32; wherein the anode A of the first clamping unit 31 is the anode A of the clamping module 3, the cathode C of the first clamping unit 31 is the cathode C of the clamping module 3, the third electrode 316 of the first clamping unit 31 is connected to the first electrode 314 through the second clamping unit 32, the cathode C of the second clamping unit 32 is connected to the third electrode 316, and the anode A of the second clamping unit 32 is connected to the first electrode 314.

[0098] The equivalent circuit of the clamping module 3 can be expressed as follows: Fig.10 As shown, it includes an enhancement transistor M and N diodes D4, the volt-ampere characteristic of the first clamping unit 31 is similar to the volt-ampere characteristic of a Zener diode, and the volt-ampere characteristic of the second clamping unit 32 is similar to the volt-ampere characteristic of a Zener diode. Then the volt-ampere characteristic of the above-mentioned clamping module 3 can also show a volt-ampere characteristic similar to that of a Zener diode; the threshold voltage of the first clamping unit 31 is VTH, and the threshold voltage of the second clamping unit 32 is N×VON, then the preset regulated voltage value Vz between the anode and cathode of the clamping module 3 is VTH+N×VON.

[0099] In the embodiment of the present invention, Fig.11 , Fig.12 and Fig.13 As shown, the transistor structure may further include a passivation layer 25 and a wiring layer 26; the passivation layer 25 may be located on a side of the gate G and the connection electrode 24 away from the substrate 1; the wiring layer 26 is located on a side of the passivation layer 25 away from the substrate 1, and the wiring layer 26 may include a first connection line L1 and a second connection line L2;

[0100] The cathode C of the voltage clamp module 3 may be connected to the gate G of the transistor module 2 via a first connection line L1 , and the anode A of the voltage clamp module 3 may be connected to the connection electrode 24 of the transistor module 2 via a second connection line L2 .

[0101] When the clamping module 3 includes the first clamping unit 31, the wiring layer 26 also includes a third connecting wiring L3 and a fourth connecting wiring L4, the first electrode 314 and the third electrode 316 of the first clamping unit 31 can be connected through the third connecting wiring L3, and the second electrode 315 and the third electrode 316 of the first clamping unit 31 can be connected through the fourth connecting wiring L4;

[0102] Specifically, the passivation layer 25 can protect the source S, drain D, gate G, connecting electrode 24, first electrode 314, second electrode 315, third electrode 316, fourth electrode 324, fifth electrode 325 and sixth electrode 326 in the transistor structure, and facilitate the wiring of the routing layer 26.

[0103] In the embodiment of the present invention, the material of the gate G is different from that of the connecting electrode 24 , so that the gate G is in Schottky contact with the first cap layer 23 , and the connecting electrode 24 is in ohmic contact with the first cap layer 23 .

[0104] Specifically, the material of the gate G may be at least one of titanium nitride (TiN), titanium (Ti), nickel (Ni) and gold (Au). For example, the material of the gate G may be titanium nitride, nickel / gold alloy, or titanium / gold alloy, etc., which is not limited here and depends on the actual situation.

[0105] The material of the connecting electrode 24 can be at least one of nickel (Ni), gold (Au) and titanium (Ti). For example, the material of the connecting electrode 24 can be a nickel / gold alloy, or a titanium / gold alloy, etc. There is no limitation here and it depends on the actual situation.

[0106] Specifically, the materials of the source S and the drain D may include at least one of titanium, aluminum, gold, nickel and titanium nitride. For example, the materials of the source S and the drain D may be titanium / aluminum / gold alloy, titanium / aluminum / nickel / gold alloy or titanium nitride / titanium / aluminum alloy, etc., which are not limited here and depend on actual conditions; the source S and the drain D may be formed in multiple layers.

[0107] Specifically, the material of the buffer layer may include gallium nitride (GaN), the material of the barrier layer may include aluminum gallium nitride (AlGaN), and the material of the cap layer may include p-type gallium nitride (p-GaN).

[0108] In addition, the buffer layer can be a C-doped GaN layer with a C concentration between 1e 19 -1e 20 It can also be a superlattice structure composed of one or more of AlN, AlGaN, and GaN.

[0109] Specifically, the buffer layer may include a plurality of sub-film layers stacked in sequence on the substrate 1; the sub-film layer on the side of the buffer layer facing away from the substrate 1 may be a channel layer, and the channel layer and the barrier layer form a heterostructure.

[0110] In an embodiment of the present invention, an insertion layer is provided between the buffer layer and the barrier layer. The material of the insertion layer includes aluminum nitride. The insertion layer located in the transistor module 2 is electrically isolated from the insertion layer located in the clamping module 3. The insertion layer can enhance the confinement of the two-dimensional electron gas (2DEG) and increase the electron mobility.

[0111] In the embodiment of the present invention, the electrical isolation region between the transistor module 2 and the voltage clamping module 3 is electrically isolated by ion implantation or trench etching.

[0112] Specifically, electrical isolation is achieved between the first buffer layer 21 and the second buffer layer or between the first barrier layer 22 and the second barrier layer by ion implantation or trench etching, and the structure is simple and easy to implement.

[0113] In the embodiment of the present invention, Figures 11 to 13 FIG. 1 is a schematic diagram of a planar structure of a transistor structure when the voltage clamping module 3 includes a first voltage clamping unit 31. The specific manufacturing steps of the transistor structure may include the following steps:

[0114] S1: Patterning the capping layer on the epitaxial wafer to form a first capping layer 23 and a first sub-capping layer 313, such as Fig.14 As shown; the epitaxial wafer includes a substrate 1, a buffer layer 201, a barrier layer 202 and a cap layer formed sequentially on the substrate 1.

[0115] Specifically, the etching of the cap layer on the epitaxial wafer is completed by ICP, RIE, etc. using a hard mask;

[0116] The material of the substrate 1 can be Si, SiC, sapphire, etc., the material of the buffer layer 201 can be GaN, the material of the barrier layer 202 can be AlGaN, the material of the cap layer can be p-GaN, and the Mg doping concentration in the cap layer 203 can be in the range of 5×10 18 ~10×10 19 cm -3 .

[0117] S2: dividing the entire buffer layer 201 and the barrier layer 202 to form a first buffer layer 21, a first sub-buffer layer 311, a first barrier layer 22 and a first sub-barrier layer 312, such as Fig.15 As shown;

[0118] Specifically, the buffer layer 201 and the barrier layer 202 are separated by ion implantation or ICP etching.

[0119] S3: forming a structure of a source electrode S, a drain electrode D, a first electrode 314, a second electrode 315, an anode electrode A and a cathode electrode C, such as Fig.16 As shown;

[0120] Specifically, a metal stack is grown and RTP annealed in a N2 atmosphere to generate a source S, a drain D, a first electrode 314, a second electrode 315, an anode A and a cathode C;

[0121] The metal stack may include a combination of various III / V group compound ohmic metal species such as Ti / Al / Ti / Au, or Ti / Al / Ni / Au, or TiN / Al / Ti / TiN.

[0122] S4: forming a connection electrode 24, such as Fig.17 As shown;

[0123] Specifically, a metal stack is grown on the cap layer 203 and RTP annealed in an O 2 atmosphere to generate the connection electrode 24 . The material of the connection electrode 24 may be Ni / Au alloy, Ti / Au alloy, or the like.

[0124] S5: forming a gate G and a third electrode 316, such as Fig.18 As shown;

[0125] Specifically, a metal stack is grown on the cap layer 203 to form the gate G and the third electrode 316 . The materials of the gate G and the third electrode 316 may be TiN, Ni / Au alloy, Ti / Au alloy, or the like.

[0126] S6: forming a passivation layer 25, such as Fig.19 As shown; wherein, the material of the passivation layer 25 can be SiN, SiO2, and the passivation layer 25 can be a multilayer.

[0127] S7: Opening a hole in the passivation layer 25, such as Fig. 20 As shown; the hole opening method can use a combination of dry etching and wet etching.

[0128] S8: forming a wiring layer 26 on the passivation layer 25 to form a first connecting wiring L1, a second connecting wiring L2, a third connecting wiring L3 and a fourth connecting wiring L4, such as Fig.21 As shown; the wiring layer 26 is connected to the source S, the drain D, the gate G, the connecting electrode 24, the first electrode 314, the second electrode 315, the third electrode 316, the anode A, and the cathode C through the openings on the passivation layer 25.

[0129] In the manufacturing steps of the above transistor structure, the transistor module 2 and the voltage clamping module 3 are prepared in the same layer, which can simplify the manufacturing steps of the transistor structure and save the manufacturing cost.

[0130] In addition, when the voltage clamping module 3 includes the second voltage clamping unit 32 , the specific manufacturing steps of the transistor structure are similar to the above manufacturing steps, and the transistor module 2 and the voltage clamping module 3 are also manufactured in the same layer.

[0131] The present invention also includes an electronic device, comprising any one of the transistor structures provided in the above technical solutions.

[0132] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A transistor structure, characterized in that: It comprises a substrate, a transistor module and a clamping module located on one side of the substrate, and there is an electrical isolation area between the transistor module and the clamping module; Wherein, one side of the substrate has: A buffer layer, located on the substrate, including a first buffer layer located in the transistor module and a second buffer layer located in the clamping module; A barrier layer, located on a side of the buffer layer away from the substrate, including a first barrier layer located in the transistor module and a second barrier layer located in the clamping module; A capping layer, located on a side of the barrier layer away from the buffer layer, comprising a first capping layer located in the transistor module and a second capping layer located in the clamping module; A source electrode and a drain electrode are located on a side of the barrier layer away from the buffer layer and located in the transistor module, the source electrode and the drain electrode are in ohmic contact with the first barrier layer, and the first cap layer is spaced between the source electrode and the drain electrode; A connecting electrode and a gate are arranged at intervals on a side of the cap layer away from the barrier layer and located in the transistor module, the connecting electrode is in ohmic contact with the first cap layer, and the gate is in Schottky contact with the first cap layer; an anode and a cathode, located on a side of the barrier layer away from the buffer layer and located in the clamping module, the cathode being electrically connected to the gate, and the anode being electrically connected to the connecting electrode; The voltage clamping module is used to clamp the voltage between the anode and the cathode within a preset voltage regulation value.

2. The transistor structure according to claim 1, characterized in that: The clamping module comprises a first clamping unit; wherein, The second buffer layer includes a first sub-buffer layer located in the first clamping unit; The second barrier layer includes a first sub-barrier layer located in the first clamping unit; The second capping layer comprises a first sub-capping layer located in the first clamping unit, and the first sub-capping layer is arranged between the anode and the cathode; Also includes a first electrode, a second electrode and a third electrode located in the first clamping unit; The first electrode, the second electrode, the anode, the cathode, the source and the drain are arranged in the same layer, the first electrode is arranged at a distance from the anode on a side away from the first sub-capping layer, the second electrode is arranged at a distance from the cathode on a side away from the first sub-capping layer, and the first electrode and the second electrode are in ohmic contact with the first sub-barrier layer; The third electrode is disposed in the same layer as the gate, the third electrode is in Schottky contact with the first sub-cap layer, and the third electrode is electrically connected to the first electrode and the second electrode.

3. The transistor structure according to claim 1 or 2, characterized in that: The clamping module includes a second clamping unit, and the second clamping unit includes N sub-clamping units, where N is an integer greater than or equal to 1; wherein, The second buffer layer includes a second sub-buffer layer located in the sub-clamping unit; The second barrier layer includes a second sub-barrier layer located in the sub-clamping unit; The second capping layer comprises a second sub-capping layer located in the sub-clamping unit; Also includes a fourth electrode, a fifth electrode and a sixth electrode located at the sub-clamping unit; The fourth electrode and the fifth electrode are arranged in the same layer as the source and the drain, the fourth electrode and the fifth electrode are located on both sides of the second sub-cap layer and are in ohmic contact with the second sub-barrier layer, and the fifth electrode is spaced apart from the second sub-cap layer; The sixth electrode is disposed in the same layer as the gate, the sixth electrode is in Schottky contact with the second sub-cap layer, and is in ohmic contact with the second sub-barrier layer through the fourth electrode; When N=1, the sixth electrode of the sub-clamping unit is the cathode of the second clamping unit, and the fifth electrode of the sub-clamping unit is the anode of the second clamping unit; When N≥2, the second sub-buffer layer and the second sub-barrier layer of each sub-clamping unit are electrically isolated, the N sub-clamping units are connected in series in sequence, the sixth electrode of the first sub-clamping unit is the cathode of the second clamping unit, the fifth electrode of the (N-1)th sub-clamping unit is connected to the sixth electrode of the Nth sub-clamping unit, and the fifth electrode of the Nth sub-clamping unit is the anode of the second clamping unit.

4. The transistor structure according to claim 3, characterized in that: The clamping module includes the first clamping unit and the second clamping unit; The anode of the first clamping unit is the anode of the clamping module, and the cathode of the first clamping unit is the cathode of the clamping module; The third electrode of the first clamping unit is connected to the first electrode through the second clamping unit, a cathode of the second clamping unit is connected to the third electrode, and an anode of the second clamping unit is connected to the first electrode.

5. The transistor structure according to claim 1, characterized in that: It also includes passivation layer and routing layer; The passivation layer is located on a side of the gate and the connecting electrode facing away from the substrate; The wiring layer is located on a side of the passivation layer away from the substrate, and the wiring layer includes a first connecting line and a second connecting line; The cathode of the voltage clamping module is connected to the grid through a first connection line, and the anode of the voltage clamping module is connected to the connection electrode through a second connection line.

6. The transistor structure according to claim 1, characterized in that: The material of the gate electrode is different from that of the connection electrode.

7. The transistor structure according to claim 6, characterized in that: The material of the buffer layer includes gallium nitride, the material of the barrier layer includes aluminum gallium nitride, and the material of the cap layer includes p-type gallium nitride.

8. The transistor structure according to claim 1, characterized in that: The material of the source and drain electrodes includes at least one of titanium, aluminum, gold, nickel and titanium nitride; The material of the gate includes at least one of titanium nitride, titanium, nickel and gold; The material of the connection electrode includes at least one of nickel, gold and titanium.

9. The transistor structure according to claim 1, characterized in that: The buffer layer includes multiple sub-film layers stacked in sequence on the substrate; The sub-film layer on the side of the buffer layer away from the substrate is a channel layer, and the channel layer and the barrier layer form a heterostructure.

10. The transistor structure according to claim 1, characterized in that: An insertion layer is provided between the buffer layer and the barrier layer. The material of the insertion layer includes aluminum nitride. The insertion layer located in the transistor module is electrically isolated from the insertion layer located in the clamping module.

11. The transistor structure according to claim 1, characterized in that: The electrical isolation region between the transistor module and the voltage clamping module is electrically isolated by ion implantation or trench etching.

12. An electronic device, characterized in that: Comprising the transistor structure as claimed in any one of claims 1 to 11.

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