Semiconductor structure, manufacturing method, chip and circuit

Abstract

The invention provides a semiconductor structure, a manufacturing method, a chip and a circuit, and relates to the field of semiconductors. The semiconductor structure includes: a substrate; the well region is formed in the substrate; wherein the well region comprises a plurality of sub-well regions formed by ion implantation from outside to inside in sequence, and the relative atomic mass of the ions implanted in the sub-well region on the innermost side is larger than the relative atomic mass of the ions implanted in the other sub-well regions; the grid electrode is formed on the upper surface of the sub-well region on the innermost side of the well region in a step shape; and the side walls are formed on the two sides of the grid electrode. According to the invention, the oxidation enhancement diffusion effect and the transient enhancement effect can be reduced, so that the impurity concentration of the surface of the channel below the grid electrode does not rise too fast, the stability of the threshold voltage and saturation current of the device structure is ensured, and the performance of the finally formed semiconductor structure is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor structure, a method for manufacturing the semiconductor structure, a chip and a circuit. Background Art

[0002] As device size continues to shrink, semiconductor devices face many problems, such as severe channel effect, hot carrier effect and large leakage current. In order to solve the above problems, the substrate is usually subjected to high-temperature oxidation treatment after the gate is formed to form a sidewall structure on both sides of the gate.

[0003] In the prior art, during the high-temperature oxidation process, the doped ions in the well region below the gate are easily diffused, and then an oxidation-enhanced diffusion effect and a transient enhancement effect caused by the oxidation-enhanced diffusion effect occur, causing the impurity concentration on the channel surface below the gate to rise too quickly, resulting in instability in the threshold voltage and saturation current of the device structure, thereby affecting the performance of the semiconductor structure finally formed. Summary of the invention

[0004] In view of the technical problem that the oxidation enhanced diffusion effect and the transient enhancement effect are prone to occur in the prior art, which causes the impurity concentration on the channel surface below the gate to rise too quickly, resulting in instability of the threshold voltage and saturation current of the device structure, thereby affecting the performance of the finally formed semiconductor structure, the present invention provides a semiconductor structure, a method for manufacturing a semiconductor structure, a chip and a circuit. The use of the semiconductor structure can reduce the oxidation enhanced diffusion effect and the transient enhancement effect, so that the impurity concentration on the channel surface below the gate does not rise too quickly, thereby ensuring the stability of the threshold voltage and saturation current of the device structure, and improving the performance of the finally formed semiconductor structure.

[0005] To achieve the above-mentioned purpose, the first aspect of the present invention provides a semiconductor structure, which includes: a substrate; a well region formed in the substrate; wherein the well region includes a plurality of sub-well regions formed by ion implantation from the outside to the inside, the relative atomic mass of the ions injected into the innermost sub-well region being greater than the relative atomic mass of the ions injected into the remaining sub-well regions; a gate, which is formed in a step-like manner on the upper surface of the innermost sub-well region of the well region; and side walls formed on both sides of the gate.

[0006] Further, in the case where the well region is P-type ion implanted, the ions implanted into the innermost sub-well region include: one or more of fluoroborate ions, indium ions and aluminum ions.

[0007] Furthermore, the ion implantation energies of the plurality of sub-well regions decrease sequentially from the outside to the inside.

[0008] Furthermore, the ion implantation doses of the plurality of sub-well regions decrease sequentially from the outside to the inside.

[0009] Furthermore, the well region includes three sub-well regions formed by ion implantation from the outside to the inside; the ions implanted into the outermost sub-well region are boron ions, the energy of the ion implantation is between 150Kev and 250Kev, and the doping dose is between 3E13atom / cm 2 -6E13atom / cm 2 The ions injected into the middle sub-well region are boron ions, the energy of ion injection is between 90Kev-110Kev, and the doping dose is between 4E12atom / cm 2 -6E12atom / cm 2 The ion implantation energy of the innermost sub-well region is between 15Kev and 25Kev, and the doping dose is between 6E12atom / cm 2 -8E12atom / cm 2 .

[0010] A second aspect of the present invention provides a method for manufacturing a semiconductor structure, which comprises: providing a substrate; performing multiple ion implantations in sequence from the outside to the inside in the substrate to form a well region; wherein the well region comprises a plurality of sub-well regions formed by ion implantations in sequence from the outside to the inside, the relative atomic mass of the ions injected into the innermost sub-well region being greater than the relative atomic mass of the ions injected into the remaining sub-well regions; forming a stepped gate on the upper surface of the innermost sub-well region of the well region; and forming side walls on both sides of the gate.

[0011] Further, in the case where the well region is P-type ion implanted, the ions implanted into the innermost sub-well region include: one or more of fluoroborate ions, indium ions and aluminum ions.

[0012] Furthermore, the ion implantation energies of the plurality of sub-well regions decrease sequentially from the outside to the inside.

[0013] Furthermore, the ion implantation doses of the plurality of sub-well regions decrease sequentially from the outside to the inside.

[0014] Further, the well region includes three sub-well regions formed by sequential ion implantation from outside to inside; the forming of the well region by sequentially performing multiple ion implantations from outside to inside in the substrate includes: performing a first ion implantation in the substrate to form an outermost sub-well region; wherein the ions implanted in the first ion implantation are boron ions, the energy of the ion implantation is between 150Kev and 250Kev, and the doping dose is between 3E13atom / cm 2 -6E13atom / cm 2 ; A second ion implantation is performed in the outermost sub-well region to form a middle sub-well region; wherein the ions implanted in the second ion implantation are boron ions, the energy of the ion implantation is between 90Kev and 110Kev, and the doping dose is between 4E12atom / cm2 -6E12atom / cm 2 ; A third ion implantation is performed in the middle sub-well region to form the innermost sub-well region; wherein the energy of the third ion implantation is between 15Kev and 25Kev, and the doping dose is between 6E12atom / cm 2 -8E12atom / cm 2 .

[0015] A third aspect of the present invention provides a chip, which includes the semiconductor structure described above.

[0016] A fourth aspect of the present invention provides a circuit, which includes the semiconductor structure described above.

[0017] Through the technical solution provided by the present invention, the present invention has at least the following technical effects:

[0018] The semiconductor structure of the present invention includes a substrate, a well region is formed in the substrate, the well region includes a plurality of sub-well regions formed by sequential ion implantation from the outside to the inside, the relative atomic mass of the ions injected into the innermost sub-well region is greater than the relative atomic mass of the ions injected into the other sub-well regions. A gate is formed on the upper surface of the innermost sub-well region of the well region, and side walls are formed on both sides of the gate. The relative atomic mass of the ions injected into the innermost sub-well region is relatively large. When the side walls are formed, the impurities injected into the innermost sub-well region diffuse slowly, thereby reducing the oxidation-enhanced diffusion effect and transient enhancement effect of the impurities in the well region, so that the impurity concentration on the channel surface below the gate does not rise too fast, thereby ensuring the stability of the threshold voltage and saturation current of the device structure, and improving the performance of the semiconductor structure finally formed.

[0019] Other features and advantages of the present invention will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The accompanying drawings are used to provide a further understanding of the embodiments of the present invention and constitute a part of the specification. Together with the following specific implementations, they are used to explain the embodiments of the present invention, but do not constitute a limitation on the embodiments of the present invention. In the accompanying drawings:

[0021] The accompanying drawings are used to provide a further understanding of the embodiments of the present invention and constitute a part of the specification. Together with the following specific implementations, they are used to explain the embodiments of the present invention, but do not constitute a limitation on the embodiments of the present invention. In the accompanying drawings:

[0022] Figure 1 A schematic structural diagram of a substrate formed in a semiconductor structure manufacturing method provided by an embodiment of the present invention;

[0023] Figure 2A schematic diagram of the structure of a well region formed in a method for manufacturing a semiconductor structure provided by an embodiment of the present invention;

[0024] Figure 3 A schematic diagram of the structure of a gate formed in a method for manufacturing a semiconductor structure provided by an embodiment of the present invention;

[0025] Figure 4 A schematic structural diagram of a semiconductor structure formed in a semiconductor structure manufacturing method provided in an embodiment of the present invention;

[0026] Figure 5 A flowchart of a method for manufacturing a semiconductor structure provided by an embodiment of the present invention.

[0027] Description of Reference Numerals

[0028] 100 - substrate; 101 - well region; 101a - outermost sub-well region; 101b - middle sub-well region; 101c - innermost sub-well region; 102 - gate; 103 - spacer; 104 - heavy isolation spacer. DETAILED DESCRIPTION

[0029] The specific implementation of the embodiment of the present invention is described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation described here is only used to illustrate and explain the embodiment of the present invention, and is not used to limit the embodiment of the present invention.

[0030] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0031] In the present invention, unless otherwise specified, directional words such as "up, down, top, bottom" are usually used with reference to the directions shown in the drawings or are used to describe the relative positional relationships of components in the vertical, perpendicular or gravity direction.

[0032] As the background technology, the performance of existing semiconductor devices is relatively poor.

[0033] Please refer to Figure 4 A first aspect of an embodiment of the present invention provides a semiconductor structure, which includes: a substrate 100; a well region 101, formed in the substrate 100; wherein the well region 101 includes a plurality of sub-well regions formed by ion implantation from the outside to the inside, and the relative atomic mass of the ions injected into the innermost sub-well region 101c is greater than the relative atomic mass of the ions injected into the remaining sub-well regions; a gate 102, wherein the gate 102 is formed in a step-like manner on the upper surface of the innermost sub-well region 101c of the well region 101; and sidewalls 103 are formed on both sides of the gate 102.

[0034] Specifically, the semiconductor structure in the embodiment of the present invention can be applied to MOS transistors, LDMOS transistors, or other transistors including gates, well regions and sidewalls. The semiconductor structure includes a substrate 100, in which a well region 101 is formed, and the well region 101 includes a plurality of sub-well regions formed by ion implantation from the outside to the inside. Those skilled in the art can adjust the impurity ion type, injection energy and impurity content of each ion implantation according to needs, and can adjust the threshold voltage of the transistor according to the use needs, which is the critical voltage for turning the transistor on and off. Through the doping concentration and depth of multiple sub-well regions, the threshold voltage can be accurately controlled, a potential barrier can be formed, the leakage of carriers can be reduced, thereby alleviating the short channel effect, reducing static power consumption and improving the reliability of the circuit, and a low doping concentration area can be provided, which helps to improve the mobility of carriers, thereby improving the switching speed and overall performance of the transistor, and increasing the breakdown voltage of the transistor. The relative atomic mass of the ions injected into the innermost sub-well region is greater than the relative atomic mass of the ions injected into the remaining sub-well regions. When forming the sidewalls, the impurities injected into the innermost sub-well region diffuse more slowly, thereby reducing the oxidation-enhanced diffusion effect and transient enhancement effect of the impurities in the well region, so that the impurity concentration on the channel surface below the gate does not rise too quickly, thereby ensuring the stability of the threshold voltage and saturation current of the device structure, and improving the performance of the semiconductor structure finally formed.

[0035] A stepped gate 102 is formed on the upper surface of the innermost sub-well region 101c of the well region 101, and sidewalls 103 are formed on the sidewalls on both sides of the gate 102. The sidewalls 103 can isolate the gate from the source and drain regions to prevent the gate from directly contacting the source and drain regions. The sidewalls can also ensure the structural integrity and electrical isolation of the transistor, help define the boundaries of the source and drain regions, so that the doping of the source and drain regions and subsequent processing steps can be precisely controlled. In advanced process nodes, the channel length of the transistor is very short, which is prone to short channel effects. The sidewalls can increase the distance between the gate and the source and drain regions, thereby reducing the short channel effect, improving the switching characteristics of the device, reducing the parasitic capacitance between the gate and the source and drain regions, reducing the leakage current of the device in the off state, reducing power consumption, and improving the static performance of the circuit.

[0036] The semiconductor structure provided by the present invention can reduce the diffusion rate of impurities injected into the innermost sub-well region when forming the sidewall, thereby reducing the oxidation-enhanced diffusion effect and transient enhancement effect of impurities in the well region, so that the impurity concentration on the channel surface below the gate does not rise too quickly, thereby ensuring the stability of the threshold voltage and saturation current of the device structure, and improving the performance of the semiconductor structure finally formed.

[0037] Further, in the case where the well region 101 is P-type ion implanted, the ions implanted into the innermost sub-well region 101 c include: one or more of fluoroborate ions, indium ions and aluminum ions.

[0038] Specifically, in an embodiment of the present invention, the well region 101 is P-type ion implanted, and the impurities implanted are usually boron ions. The ions implanted into the innermost sub-well region 101c include: one or more of fluoroborate ions, indium ions and aluminum ions. The relative atomic mass of the ions implanted into the innermost sub-well region 101c is greater than the relative atomic mass of the ions implanted into the remaining sub-well regions.

[0039] When N-type ion implantation is performed on the well region 101 , the ions implanted into the innermost sub-well region 101 c include arsenic ions and / or antimony ions.

[0040] Furthermore, the ion implantation energies of the plurality of sub-well regions decrease sequentially from the outside to the inside.

[0041] Furthermore, the ion implantation doses of the plurality of sub-well regions decrease sequentially from the outside to the inside.

[0042] Specifically, in the implementation manner of the present invention, the injection method of multiple sub-well regions forms a progressive well region 101, which can be used to adjust the threshold voltage of the transistor, form a potential barrier, reduce the leakage of carriers, thereby alleviating the short channel effect, reducing the leakage current when the transistor is in the off state, reducing static power consumption and improving the reliability of the circuit, increasing the breakdown voltage of the transistor, modulating the electric field distribution, thereby optimizing the electric field strength of the device, reducing electric field concentration, improving the thermal stability of the device, reducing performance degradation caused by temperature changes, and improving the reliability and life of the device.

[0043] Furthermore, the well region includes three sub-well regions formed by ion implantation from outside to inside; the ions implanted into the outermost sub-well region 101a are boron ions, the energy of the ion implantation is between 150Kev and 250Kev, and the doping dose is between 3E13atom / cm 2 -6E13atom / cm 2 The ions injected into the middle sub-well region 101b are boron ions, the energy of the ion injection is between 90Kev-110Kev, and the doping dose is between 4E12atom / cm 2 -6E12atom / cm 2 The ion implantation energy of the innermost sub-well region 101c is between 15Kev and 25Kev, and the doping dose is between 6E12atom / cm 2 -8E12atom / cm 2 .

[0044] Specifically, in the embodiment of the present invention, the well region 101 includes three sub-well regions, and the ions injected into the outermost sub-well region 101a are boron ions, the energy of the ion injection is between 150Kev and 250Kev, and the doping dose is between 3E13atom / cm2 -6E13atom / cm 2 The ions injected into the middle sub-well region 101b are boron ions, the energy of the ion injection is between 90Kev-110Kev, and the doping dose is between 4E12atom / cm 2 -6E12atom / cm 2 The ions in the innermost sub-well region 101c include: one or more of fluoroborate ions, indium ions and aluminum ions, the energy of ion implantation is between 15Kev-25Kev, and the doping dose is between 6E12atom / cm 2 -8E12atom / cm 2 The depth d of the innermost sub-well region 101c is between

[0045] The outermost sub-well region 101a has the largest ion injection energy, injection dosage, and the deepest injection, which can prevent the latch-up effect of the transistor; the middle sub-well region 101b has medium ion injection energy, injection dosage, and a medium depth, which can prevent the source-drain punch-through of the transistor; the innermost sub-well region 101c has the smallest ion injection energy, injection dosage, and the shallowest injection, which can adjust the threshold voltage on the surface of the transistor.

[0046] Please refer to Figure 1-5 According to a second aspect of the present invention, there is provided a method for manufacturing a semiconductor structure, the method comprising: S101: providing a substrate 100; S102: performing multiple ion implantations in the substrate 100 from the outside to the inside to form a well region 101; wherein the well region 101 comprises a plurality of sub-well regions formed by ion implantations in sequence from the outside to the inside, the relative atomic mass of the ions injected into the innermost sub-well region 101c being greater than the relative atomic mass of the ions injected into the remaining sub-well regions; S103: forming a stepped gate 102 on the upper surface of the innermost sub-well region 101c of the well region 101; S104: forming sidewalls 103 on both sides of the gate 102.

[0047] Specifically, step S101 is first performed: providing a substrate 100,

[0048] like Figure 1 As shown, specifically, in the embodiment of the present invention, the substrate 100 is one of a silicon substrate, a silicon germanium substrate, a silicon-on-insulator substrate, and a germanium-on-insulator substrate. The formed semiconductor structure can be an N-type semiconductor structure or a P-type semiconductor structure. In the following text embodiments, only the N-type semiconductor structure is used as an example for description.

[0049] First, a substrate 100 is provided. The substrate 100 is one of a silicon substrate, a silicon germanium substrate, a silicon-on-insulator substrate, and a germanium-on-insulator substrate. In this embodiment, the substrate is a P-type doped silicon substrate. Those skilled in the art can select the type of substrate according to the performance of the semiconductor device to be formed, so the type of substrate should not excessively limit the protection scope of the present invention.

[0050] Please refer to Figure 2 , then execute step S102: multiple ion implantations are performed in sequence from the outside to the inside in the substrate 100 to form a well region 101; wherein the well region 101 includes multiple sub-well regions formed by ion implantations in sequence from the outside to the inside, and the relative atomic mass of the ions injected into the innermost sub-well region 101c is greater than the relative atomic mass of the ions injected into the remaining sub-well regions.

[0051] Further, in the case where the well region 101 is P-type ion implanted, the ions implanted into the innermost sub-well region 101 c include: one or more of fluoroborate ions, indium ions and aluminum ions.

[0052] Furthermore, the ion implantation energies of the plurality of sub-well regions decrease sequentially from the outside to the inside.

[0053] Furthermore, the ion implantation doses of the plurality of sub-well regions decrease sequentially from the outside to the inside.

[0054] Further, the well region 101 includes three sub-well regions formed by sequential ion implantation from outside to inside; the forming of the well region 101 by sequentially performing multiple ion implantations from outside to inside in the substrate 100 includes: performing a first ion implantation in the substrate 100 to form an outermost sub-well region 101a; wherein the ions implanted in the first ion implantation are boron ions, the ion implantation energy is between 150Kev and 250Kev, and the doping dose is between 3E13atom / cm 2 -6E13atom / cm 2 ; A second ion implantation is performed in the outermost sub-well region 101a to form a middle sub-well region 101b; wherein the ions implanted in the second ion implantation are boron ions, the energy of the ion implantation is between 90Kev-110Kev, and the doping dose is between 4E12atom / cm 2 -6E12atom / cm 2 ; A third ion implantation is performed in the middle sub-well region 101b to form the innermost sub-well region 101c; wherein the energy of the third ion implantation is between 15Kev-25Kev, and the doping dose is between 6E12atom / cm 2 -8E12atom / cm 2 .

[0055] Specifically, in the embodiment of the present invention, the first ion implantation is performed in the substrate 100 to form the outermost sub-well region 101a. The implanted ions are boron ions. The energy of the ion implantation is between 150Kev and 250Kev. The doping dose is between 3E13atom / cm 2 -6E13atom / cm 2 Next, a second ion implantation is performed in the outermost sub-well region 101a to form a middle sub-well region 101b. The ions implanted in the second ion implantation are boron ions. The energy of the ion implantation is between 90 KeV and 110 KeV, and the doping dose is between 4E12 atom / cm 2 -6E12atom / cm 2 Finally, a third ion implantation is performed in the middle sub-well region 101b to form the innermost sub-well region 101c. The implantation energy is between 15Kev and 25Kev, and the doping dose is between 6E12atom / cm 2 -8E12atom / cm 2 .

[0056] Then, the substrate 100 is annealed at a temperature between 1000° C. and 1100° C. for a time between 5 and 60 seconds. Rapid thermal annealing helps to activate the doping impurities in the well region 101 and inhibit the diffusion of the doping impurities.

[0057] The outermost sub-well region 101a has the largest ion injection energy, injection dose, and the deepest injection, which can prevent the latch effect of the transistor; the middle sub-well region 101b has medium ion injection energy, injection dose, and depth, which can prevent the source-drain punch-through of the transistor; the innermost sub-well region 101c has the smallest ion injection energy, injection dose, and the shallowest injection, and the depth d of the innermost sub-well region 101c is between Ability to adjust the threshold voltage of the transistor surface.

[0058] Please refer to Figure 3 Then, step S103 is performed: a stepped gate 102 is formed on the upper surface of the innermost sub-well region 101 c of the well region 101 .

[0059] Specifically, in the embodiment of the present invention, a thin gate oxide layer (not shown in the figure) is formed on the surface of the substrate 100, a polysilicon layer is formed on the surface of the gate oxide layer, the polysilicon layer is patterned using an etching process, and a stepped gate 102 is formed on the upper surface of the innermost sub-well region 101c of the well region 101.

[0060] Please refer to Figure 4 Finally, step S104 is performed: forming sidewall spacers 103 on both sides of the gate 102 .

[0061] Specifically, in the embodiment of the present invention, a high temperature oxidation treatment is performed on the semiconductor structure to form silicon nitride sidewalls 103 on both sides of the gate 102, and at the same time, damage caused by etching during the formation of the gate 102 is repaired to improve the formation quality of the gate 102. The gas used in the high temperature oxidation treatment includes oxygen, and the treatment temperature is between 900-1100°C.

[0062] During the high-temperature oxidation process, since the relative atomic mass of the ions injected into the innermost sub-well region 101c is greater than the relative atomic mass of the ions injected into the other sub-well regions, the diffusion ability of the doped ions is poor, thereby avoiding the oxidation enhanced diffusion effect and the transient enhancement effect caused by the oxidation enhanced diffusion effect of the doped ions in the well region 101 due to the high-temperature oxygen environment, so that the impurity concentration on the channel surface under the gate 102 will not rise too quickly, thereby ensuring the stability of the threshold voltage and saturation current of the device structure and improving the performance of the semiconductor structure finally formed.

[0063] Then, a lightly doped ion implantation process is performed on the substrate 100 at the bottom of the gate 102 to form a heavy isolation spacer 104 on the sidewall of the spacer 103. In this embodiment, the heavy isolation spacer 104 adopts a stacked structure, including a silicon oxide layer formed outside the spacer 103 and a silicon nitride layer formed outside the silicon oxide layer. After the heavy isolation spacer 104 is formed, the substrate 100 on both sides of the heavy isolation spacer is heavily doped to form a source and drain.

[0064] A third aspect of the present invention provides a chip, which includes the semiconductor structure described above.

[0065] A fourth aspect of the present invention provides a circuit, which includes the semiconductor structure described above.

[0066] The preferred embodiments of the present invention are described in detail above in conjunction with the accompanying drawings. However, the present invention is not limited to the specific details in the above embodiments. Within the technical concept of the present invention, a variety of simple modifications can be made to the technical solution of the present invention, and these simple modifications all belong to the protection scope of the present invention.

[0067] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present invention will not further describe various possible combinations.

[0068] In addition, various embodiments of the present invention may be arbitrarily combined, and as long as they do not violate the concept of the present invention, they should also be regarded as the contents disclosed by the present invention.

Claims

1. A semiconductor structure, characterized in that: The semiconductor structure comprises: substrate; A well region is formed in the substrate; wherein the well region includes a plurality of sub-well regions formed by ion implantation from the outside to the inside, and the relative atomic mass of the ions implanted in the innermost sub-well region is greater than the relative atomic mass of the ions implanted in the remaining sub-well regions; A gate, the gate being formed in a step-like manner on an upper surface of the innermost sub-well region of the well region; Sidewall spacers are formed on both sides of the gate.

2. The semiconductor structure according to claim 1, characterized in that: In the case where the well region is P-type ion implanted, the ions implanted into the innermost sub-well region include: one or more of fluoroborate ions, indium ions and aluminum ions.

3. The semiconductor structure according to claim 2, characterized in that: The ion implantation energies of the plurality of sub-well regions decrease from the outside to the inside.

4. The semiconductor structure according to claim 3, characterized in that: The ion implantation doses of the plurality of sub-well regions decrease sequentially from the outside to the inside.

5. The semiconductor structure according to claim 4, characterized in that: The well region includes three sub-well regions formed by ion implantation from outside to inside in sequence; The ions injected into the outermost sub-well region are boron ions. The energy of ion injection is between 150Kev and 250Kev, and the doping dose is between 3E13atom / cm 2 -6E13atom / cm 2 ; The ions injected into the middle sub-well are boron ions, with an ion injection energy of 90Kev-110Kev and a doping dose of 4E12atom / cm 2 -6E12atom / cm 2 ; The ion implantation energy of the innermost sub-well region is between 15Kev and 25Kev, and the doping dose is between 6E12atom / cm 2 -8E12atom / cm 2 .

6. A method for manufacturing a semiconductor structure, characterized in that: The semiconductor structure manufacturing method comprises: providing a substrate; Performing multiple ion implantations in sequence from the outside to the inside of the substrate to form a well region; wherein the well region includes a plurality of sub-well regions formed by sequential ion implantations from the outside to the inside, and the relative atomic mass of the ions implanted into the innermost sub-well region is greater than the relative atomic mass of the ions implanted into the remaining sub-well regions; forming a stepped gate on the upper surface of the innermost sub-well region of the well region; A sidewall spacer is formed on both sides of the gate.

7. The method for manufacturing a semiconductor structure according to claim 6, wherein: In the case where the well region is P-type ion implanted, the ions implanted into the innermost sub-well region include: one or more of fluoroborate ions, indium ions and aluminum ions.

8. The method for manufacturing a semiconductor structure according to claim 7, characterized in that: The ion implantation energies of the plurality of sub-well regions decrease from the outside to the inside.

9. The method for manufacturing a semiconductor structure according to claim 8, characterized in that: The ion implantation doses of the plurality of sub-well regions decrease sequentially from the outside to the inside.

10. The method for manufacturing a semiconductor structure according to claim 9, characterized in that: The well region includes three sub-well regions formed by ion implantation from outside to inside in sequence; The step of performing multiple ion implantations from outside to inside of the substrate to form a well region comprises: The first ion implantation is performed in the substrate to form the outermost sub-well region; wherein the ions implanted in the first ion implantation are boron ions, the energy of the ion implantation is between 150Kev and 250Kev, and the doping dose is between 3E13atom / cm 2 -6E13atom / cm 2 ; A second ion implantation is performed in the outermost sub-well region to form a middle sub-well region; wherein the ions implanted in the second ion implantation are boron ions, the energy of the ion implantation is between 90 KeV and 110 KeV, and the doping dose is between 4E12 atom / cm 2 -6E12atom / cm 2 ; The third ion implantation is performed in the middle sub-well region to form the innermost sub-well region; wherein the energy of the third ion implantation is between 15Kev and 25Kev, and the doping dose is between 6E12atom / cm 2 -8E12atom / cm 2 .

11. A chip, characterized in that: The chip comprises the semiconductor structure according to any one of claims 1 to 5.

12. A circuit, characterized in that: The circuit comprises the semiconductor structure according to any one of claims 1 to 5.

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