Semiconductor low-resistivity ohmic contact structure and preparation method thereof

Abstract

The invention provides a semiconductor low-resistivity ohmic contact structure and a preparation method thereof, the semiconductor low-resistivity ohmic contact structure comprises a semiconductor surface layer and a metal contact layer formed on the semiconductor surface layer, and the metal contact layer comprises a first metal layer, a second metal layer, a third metal layer and a fourth metal layer which are stacked in sequence; the first metal layer goes deep into the surface of the semiconductor surface layer to form low-resistance contact; the second metal layer is used as an accelerant for alloy formation and is used for improving adhesive force; the third metal layer is used as a barrier layer between inner and outer layers; and the fourth metal layer is used for protecting the inner-layer metal and providing a low-resistance contact point for the lead.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor low-resistivity ohmic contact structure and a preparation method thereof. Background Art

[0002] Low-resistance ohmic contact is of great significance in a variety of semiconductor optoelectronic devices and microelectronic devices. Realizing low-resistance ohmic contact helps reduce device operating power consumption and optimize device electrical performance. As a narrow-bandgap semiconductor material, InGaAs material can be used as a semiconductor surface layer for good metal-semiconductor contact after heavy doping. However, the ohmic contact formed by the existing metal system on the surface of n-type InGaAs semiconductor has a specific contact resistivity of more than 10 -5 ~10 -6 Magnitude (unit: Ω·cm 2 , the same below), a few are close to 10 -7 Large-scale contact systems often require the use of molecular beam epitaxy equipment, in-situ growth of metal deposition and other harsh laboratory conditions, which is not conducive to large-scale industrial production; and in existing alloy metal systems, higher alloy temperatures often damage other properties of semiconductor devices that require low-resistance ohmic contact. Summary of the invention

[0003] In view of the above problems, the present invention provides a semiconductor low-resistivity ohmic contact structure and a preparation method thereof, a contact layer structure for realizing low-resistance ohmic contact on the semiconductor surface and a corresponding manufacturing process, the process condition window is wide, and the process preparation method has good repeatability and stability.

[0004] According to the first aspect of an embodiment of the present invention, a semiconductor low-resistivity ohmic contact structure is provided, comprising: a semiconductor surface layer and a metal contact layer formed on the semiconductor surface layer, the metal contact layer comprising a first metal layer, a second metal layer, a third metal layer and a fourth metal layer stacked in sequence; the first metal layer penetrates into the surface of the semiconductor surface layer to form a low-resistance contact; the second metal layer is used as a promoter for alloy formation and to improve adhesion; the third metal layer is used as a barrier layer between inner and outer layers; the fourth metal layer is used to protect the inner metal layer and provide a low-resistance contact point for the lead.

[0005] According to an embodiment of the present disclosure, the semiconductor surface layer includes an n-type semiconductor surface layer of Si-doped InGaAs.

[0006] According to an embodiment of the present disclosure, the material of the first metal layer includes Ti, the material of the second metal layer includes Al, the material of the third metal layer includes Ni, and the material of the fourth metal layer includes Au.

[0007] According to an embodiment of the present disclosure, the thickness of the first metal layer is 25nm~40nm, the thickness of the second metal layer is 200nm~400nm, the thickness of the third metal layer is 30nm~50nm, and the thickness of the fourth metal layer is 30nm~60nm.

[0008] According to a second aspect of an embodiment of the present invention, a preparation method is provided for preparing the above-mentioned semiconductor low-resistivity ohmic contact structure, comprising: sequentially preparing a stacked first metal layer, a second metal layer, a third metal layer and a fourth metal layer on the semiconductor surface layer to obtain a metal contact layer; and performing a staged heating and cooling annealing treatment on the semiconductor surface layer having the metal contact layer formed on the surface to obtain a semiconductor low-resistivity ohmic contact structure.

[0009] According to an embodiment of the present disclosure, before sequentially preparing a stacked first metal layer, a second metal layer, a third metal layer and a fourth metal layer on the semiconductor surface layer, it also includes: using acetone, ethanol and water to clean the surface of the semiconductor surface layer, and using N2 gas to blow dry the water vapor; bombarding the surface of the semiconductor surface layer with plasma formed by O2 in an N2 atmosphere to remove residual dirt and oxide layer on the surface.

[0010] According to an embodiment of the present disclosure, a semiconductor surface layer having a metal contact layer formed on the surface is subjected to a staged heating and cooling annealing treatment, including: placing the semiconductor surface layer having the metal contact layer in an annealing furnace, heating the temperature from a first temperature to a second temperature at a first heating rate, and maintaining the temperature for a first preset time period; heating the temperature from the second temperature to a third temperature at a second heating rate, and maintaining the temperature for a second preset time period; and cooling the temperature from the third temperature to the first temperature at a first cooling rate.

[0011] According to an embodiment of the present disclosure, the second temperature is 200°C, the third temperature is 250°C-350°C, the first heating rate is 10°C / s, the second heating rate is 10°C / s, and the first cooling rate is 10°C / s.

[0012] According to an embodiment of the present disclosure, the first preset time period is 60s to 120s, and the second preset time period is 30s to 120s.

[0013] The semiconductor low-resistivity ohmic contact structure and the preparation method thereof provided by the present invention have at least the following technical effects:

[0014] By preparing a stacked multi-layer metal layer on the semiconductor surface layer, the first metal layer penetrates into the surface of the semiconductor surface layer to form a low-resistance contact, the second metal layer is used as a promoter for alloy formation and to improve adhesion, and the third metal layer is used as a barrier layer between the inner and outer layers. This can reduce the temperature of alloy formation, improve the stability of the ohmic contact layer, reduce the specific contact resistivity of the ohmic contact layer, and reduce the requirements of the contact structure on production conditions.

[0015] The use of staged rapid annealing treatment with rising and falling temperatures can form a stable low-resistance ohmic contact on n-type InGaAs under relatively loose process conditions such as electron beam evaporation coating and non-in-situ growth process, and reduce the possible damage to semiconductor devices requiring low-resistance ohmic contact. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above contents and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0017] Figure 1 A schematic diagram showing a structure of a semiconductor low-resistivity ohmic contact structure according to an embodiment of the present invention;

[0018] Figure 2 A cross-sectional view schematically shows a semiconductor low-resistivity ohmic contact structure according to an embodiment of the present invention;

[0019] Figure 3 A flow chart of a preparation method according to an embodiment of the present invention is schematically shown;

[0020] Figure 4 An example diagram of an IV curve obtained by a circular transmission line method according to an embodiment of the present invention is schematically shown.

[0021] Figure numerals: 1 - semiconductor surface layer; 2 - metal contact layer; 21 - first metal layer; 22 - second metal layer; 23 - third metal layer; 24 - fourth metal layer; 3 - substrate. DETAILED DESCRIPTION

[0022] Below, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present invention. In the following detailed description, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of embodiments of the present invention. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessary confusion of concepts of the present invention.

[0023] The terms used herein are only for describing specific embodiments and are not intended to limit the present invention. The terms "comprise", "include", etc. used herein indicate the existence of the features, steps, operations and / or components, but do not exclude the existence or addition of one or more other features, steps, operations or components.

[0024] All terms (including technical and scientific terms) used herein have the meanings commonly understood by those skilled in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0025] When using expressions such as "at least one of A, B, and C, etc.", they should generally be interpreted according to the meaning of the expression commonly understood by those skilled in the art (for example, "a system having at least one of A, B, and C" should include but is not limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc.).

[0026] Figure 1 The structure diagram of the semiconductor low-resistivity ohmic contact structure according to an embodiment of the present invention is schematically shown. Figure 2 The cross-sectional view of a semiconductor low-resistivity ohmic contact structure according to an embodiment of the present invention is schematically shown.

[0027] like Figure 1 and Figure 2 As shown, the semiconductor low resistivity ohmic contact structure may include:

[0028] A semiconductor surface layer 1 and a metal contact layer 2 formed on the semiconductor surface layer, wherein the metal contact layer 2 comprises a first metal layer 21, a second metal layer 22, a third metal layer 23 and a fourth metal layer 24 which are stacked in sequence.

[0029] The first metal layer 21 penetrates into the surface of the semiconductor surface layer 1 to form a low resistance contact.

[0030] The second metal layer 22 serves as an accelerator for alloy formation and improves adhesion.

[0031] The third metal layer 23 is used as a barrier layer between the inner and outer layers.

[0032] The fourth metal layer 24 is used to protect the inner metal layer and provide a low-resistance contact point for the lead.

[0033] In some embodiments of the present disclosure, the semiconductor surface layer 1 may include an n-type semiconductor surface layer of Si-doped InGaAs.

[0034] In some embodiments of the present disclosure, the material of the first metal layer may include Ti, the material of the second metal layer may include Al, the material of the third metal layer may include Ni, and the material of the fourth metal layer may include Au.

[0035] In some embodiments of the present disclosure, the thickness of the first metal layer is 25nm~40nm, the thickness of the second metal layer is 200nm~400nm, the thickness of the third metal layer is 30nm~50nm, and the thickness of the fourth metal layer is 30nm~60nm.

[0036] In some embodiments of the present disclosure, the semiconductor low-resistivity ohmic contact structure further includes a substrate 3 , and the semiconductor surface layer 1 is formed on the substrate 3 .

[0037] The embodiments of the present disclosure also provide a preparation method for preparing the above-mentioned semiconductor low-resistivity ohmic contact structure.

[0038] Figure 3 The flowchart of the preparation method according to the embodiment of the present invention is schematically shown.

[0039] like Figure 3 As shown, the preparation method may include operations S310 to S320.

[0040] In operation S310, a first metal layer, a second metal layer, a third metal layer and a fourth metal layer are sequentially stacked on a semiconductor surface layer to obtain a metal contact layer.

[0041] In operation S320, a semiconductor surface layer having a metal contact layer formed on the surface is subjected to a stepwise heating and cooling annealing process to obtain a semiconductor low-resistivity ohmic contact structure.

[0042] On the basis of the above embodiment, before sequentially preparing the stacked first metal layer, the second metal layer, the third metal layer and the fourth metal layer on the semiconductor surface layer, the method may further include:

[0043] The surface of the semiconductor surface layer is cleaned with acetone, ethanol and water, and the water vapor is blown away with N2 gas. The surface of the semiconductor surface layer is bombarded with plasma formed by O2 in the N2 atmosphere to remove residual dirt and oxide layer on the surface.

[0044] On the basis of the above-mentioned embodiment, a semiconductor surface layer having a metal contact layer formed on the surface is subjected to a staged heating and cooling annealing process, including:

[0045] The semiconductor surface layer formed with the metal contact layer is placed in an annealing furnace, and the temperature is increased from the first temperature to the second temperature at a first heating rate, and maintained for a first preset time period; the temperature is increased from the second temperature to the third temperature at a second heating rate, and maintained for a second preset time period; and the temperature is cooled from the third temperature to the first temperature at a first cooling rate.

[0046] In some embodiments, the second temperature may be 200°C, the third temperature may be 250°C-350°C, the first heating rate may be 10°C / s, the second heating rate may be 10°C / s, and the first cooling rate may be 10°C / s.

[0047] In some embodiments, the first preset time period may be 60s to 120s, and the second preset time period may be 30s to 120s.

[0048] The following is an explanation using a specific example.

[0049] Step 1: Clean the semiconductor material; clean the semiconductor material sample with an n-type InGaAs surface layer with acetone, ethanol, and water in sequence, and use N2 gas to blow off the water vapor.

[0050] Step 2: Plasma cleaning: The surface is bombarded with O2 plasma under N2 protection, with a plasma power of 300W.

[0051] Step 3: Evaporation of Ti / Al / Ni / Au multilayer metals; evaporation of Ti / Al / Ni / Au metals with a thickness of 30 / 400 / 40 / 50 nm on the n-type InGaAs surface layer.

[0052] Step 4: Place the semiconductor material sample after evaporating the metal layer into an annealing furnace; place the substrate after metal evaporation into the annealing furnace and anneal using N2 atmosphere.

[0053] Step 5: Heat to 200 degrees; Heat from room temperature to 200 degrees Celsius, the experience time is 18 seconds, and the heating rate is 10°C / s.

[0054] Step 6: Maintain at 200 degrees for 1 minute; after the temperature reaches 200 degrees, maintain for 1 minute.

[0055] Step 7: Continue to heat up to 300 degrees; heat up from 200 degrees Celsius to 300 degrees Celsius, with a heating rate of 10°C / s and a duration of 10 seconds.

[0056] Step 8: Maintain at 300 degrees for 1 minute; after the temperature reaches 300 degrees Celsius, maintain for 1 minute.

[0057] Step 9: Cool down to room temperature and then take out; cool down from 300 degrees Celsius to room temperature at a set temperature of 10 degrees Celsius / s for 28 seconds and then take out.

[0058] Figure 4 An example diagram of an IV curve obtained by a circular transmission line method according to an embodiment of the present invention is schematically shown.

[0059] like Figure 4As shown, the semiconductor low-resistivity ohmic contact structure provided by the embodiment of the present disclosure has good linearity, indicating that the ohmic contact is stable.

[0060] Based on the semiconductor low-resistivity ohmic contact structure provided by the embodiment of the present disclosure, the evaporated metal is transformed from Schottky contact to ohmic contact after annealing, and the ohmic contact resistivity reaches 1.6×10 -6 Ω·cm 2 .

[0061] In summary, the semiconductor low-resistivity ohmic contact structure provided by the embodiments of the present disclosure reduces the temperature for forming the alloy, improves the stability of the ohmic contact layer, reduces the specific contact resistivity of the ohmic contact layer, and reduces the requirements of the contact structure on production conditions.

[0062] The flowcharts and block diagrams in the accompanying drawings illustrate the possible implementation architecture, functions and operations of the systems and methods according to various embodiments of the present invention. In this regard, each box in the flowchart or block diagram may represent a module, a program segment or a part of a code, and the above-mentioned module, a program segment or a part of a code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box may also occur in an order different from that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flowchart, and the combination of boxes in the block diagram or flowchart, can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0063] It will be appreciated by those skilled in the art that the features described in the various embodiments and / or claims of the present invention may be combined and / or combined in various ways, even if such combinations and / or combinations are not explicitly described in the present invention. In particular, the features described in the various embodiments and / or claims of the present invention may be combined and / or combined in various ways without departing from the spirit and teachings of the present invention. All of these combinations and / or combinations fall within the scope of the present invention.

[0064] The embodiments of the present invention are described above. However, these embodiments are only for the purpose of illustration, and are not intended to limit the scope of the present invention. Although each embodiment is described above, it does not mean that the measures in each embodiment cannot be used in combination. The scope of the present invention is defined by the attached claims and their equivalents. Without departing from the scope of the present invention, those skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present invention.

Claims

1. A semiconductor low resistivity ohmic contact structure, characterized in that: include: A semiconductor surface layer and a metal contact layer formed on the semiconductor surface layer, wherein the metal contact layer comprises a first metal layer, a second metal layer, a third metal layer and a fourth metal layer stacked in sequence; The first metal layer penetrates into the surface of the semiconductor surface layer to form a low resistance contact; The second metal layer is used as a promoter for alloy formation and to improve adhesion; The third metal layer is used as a barrier layer between the inner and outer layers; The fourth metal layer is used to protect the inner metal layer and provide a low-resistance contact point for the lead.

2. The semiconductor low-resistivity ohmic contact structure according to claim 1, characterized in that: The semiconductor surface layer includes an n-type semiconductor surface layer of Si-doped InGaAs.

3. The semiconductor low-resistivity ohmic contact structure according to claim 1, characterized in that: The material of the first metal layer includes Ti, the material of the second metal layer includes Al, the material of the third metal layer includes Ni, and the material of the fourth metal layer includes Au.

4. The semiconductor low-resistivity ohmic contact structure according to claim 1 or 3, characterized in that: The thickness of the first metal layer is 25nm-40nm, the thickness of the second metal layer is 200nm-400nm, the thickness of the third metal layer is 30nm-50nm, and the thickness of the fourth metal layer is 30nm-60nm.

5. A preparation method for preparing the semiconductor low-resistivity ohmic contact structure according to any one of claims 1 to 4, characterized in that: include: A first metal layer, a second metal layer, a third metal layer and a fourth metal layer are sequentially prepared on the semiconductor surface layer to obtain a metal contact layer. The semiconductor surface layer with a metal contact layer formed on the surface is subjected to stage-by-stage heating and cooling annealing treatment to obtain a semiconductor low-resistivity ohmic contact structure.

6. The preparation method according to claim 5, characterized in that: Before sequentially preparing a stacked first metal layer, a second metal layer, a third metal layer and a fourth metal layer on the semiconductor surface layer, the method further includes: The surface of the semiconductor surface layer is cleaned using acetone, ethanol and water, and the water vapor is blown away using N2 gas; The surface of the semiconductor surface layer is bombarded with plasma formed by O2 in an N2 atmosphere to remove residual dirt and an oxide layer on the surface.

7. The preparation method according to claim 5 or 6, characterized in that: The stepwise heating and cooling annealing treatment of the semiconductor surface layer having the metal contact layer formed on the surface comprises: Placing the semiconductor surface layer formed with the metal contact layer in an annealing furnace, heating the temperature from a first temperature to a second temperature at a first heating rate, and maintaining the temperature for a first preset time period; Raising the temperature from the second temperature to the third temperature at a second heating rate and maintaining the temperature for a second preset time period; The temperature is lowered from the third temperature to the first temperature at a first cooling rate.

8. The preparation method according to claim 7, characterized in that: The second temperature is 200°C, the third temperature is 250°C-350°C, the first heating rate is 10°C / s, the second heating rate is 10°C / s, and the first cooling rate is 10°C / s.

9. The preparation method according to claim 7, characterized in that: The first preset time period is 60s to 120s, and the second preset time period is 30s to 120s.

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