Method of forming a semiconductor structure

Abstract

The application relates to a method for forming a semiconductor structure. In the method, after a hard mask layer covering a gate structure and a substrate is formed, a patterned mask is used to protect an NMOS forming area, and a first non-isotropic etching is performed to expose the substrate on both sides of the gate structure of a PMOS forming area; then the patterned mask is removed, and a second non-isotropic etching is performed to form a source-drain groove in the PMOS forming area and remove part of a nitride film in the hard mask layer of the NMOS forming area; then an oxide film in the hard mask layer is used to protect the substrate of the NMOS forming area, a ∑-shaped groove is formed in the PMOS forming area, and hetero-epitaxy is performed; finally, a maskless process is used to remove the remaining hard mask layer, a gate upper oxide layer and a gate upper nitride layer in the gate structure. The above method uses a photomask process only once when the patterned mask is formed, which helps to reduce the cost of a CMOS process, reduces the damage to the substrate, and helps to improve the device performance.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit manufacturing, and in particular to a method for forming a semiconductor structure. Background Art

[0002] In MOS transistors, carrier mobility affects the channel current, which in turn affects device performance. For example, low carrier mobility reduces the device's operating saturation current and response speed. Therefore, in CMOS processes, the source / drain regions of PMOS transistors (hereinafter referred to as PMOS) and NMOS transistors (hereinafter referred to as NMOS) are often processed separately. In the PMOS formation area, grooves with ∑-shaped sidewalls (hereinafter referred to as ∑-shaped grooves) are formed in the substrate on both sides of the gate, and silicon germanium (SiGe) is epitaxially grown in the ∑-shaped grooves to serve as the source / drain regions of the PMOS.

[0003] In a conventional CMOS process, corresponding gate structures are formed in the NMOS formation region and the PMOS formation region on the substrate surface. A hard mask layer is then formed along the surfaces of the substrate and gate structures. The hard mask layer in the PMOS formation region is then anisotropically etched back, and the substrate is further etched to form grooves for epitaxially growing silicon germanium. To prevent damage to the gates during the etching process, each gate structure includes a gate nitride layer covering the gate top surface and sidewalls covering the gate sides. During the groove etching process, a mask layer is used to protect the NMOS formation region. After the silicon germanium epitaxy in the PMOS formation region is completed, another mask layer is used to protect the PMOS formation region, exposing the NMOS formation region. The portion of the hard mask layer covering the NMOS formation region is removed, exposing the gate nitride layer covering the gate top surface. The other mask layer is then removed, and the remaining hard mask layer and gate nitride layer in the PMOS and NMOS formation regions are removed.

[0004] In the above-mentioned CMOS process, at least two photomask processes are required to form a groove in the PMOS formation area, perform a silicon germanium epitaxial process, and remove the hard mask layers in the PMOS formation area and the NMOS formation area, as well as the nitride layer on the gate, resulting in high costs. Moreover, when the above-mentioned other mask layer is used to protect the PMOS formation area and expose the NMOS formation area and part of the hard mask layer in the NMOS formation area is etched, the substrate in the NMOS formation area is easily etched back (recessed) due to over-etching during the etching process, which is detrimental to the performance of the NMOS. Summary of the Invention

[0005] In order to reduce the manufacturing cost of CMOS technology and improve device performance, the present invention provides a method for forming a semiconductor structure.

[0006] The method for forming a semiconductor structure provided by the present invention includes:

[0007] Providing a substrate, wherein the substrate is provided with a PMOS formation region and an NMOS formation region;

[0008] A first gate structure and a second gate structure are formed in the PMOS formation region and the NMOS formation region, respectively, wherein the first gate structure and the second gate structure each include at least a gate dielectric layer, a gate, an oxide layer on the gate, a nitride layer on the gate, and sidewalls formed on the sides of the gate;

[0009] Conformally forming a hard mask stack along surfaces of the substrate, the first gate structure, and the second gate structure, the hard mask stack comprising an oxide film and a nitride film stacked on the oxide film;

[0010] forming a patterned mask to cover the NMOS formation region and expose the PMOS formation region;

[0011] Performing a first anisotropic etching to expose the gate nitride layer in the first gate structure and the substrate surface where the PMOS formation region is located on both sides of the first gate structure;

[0012] removing the patterned mask to expose the hard mask stack in the NMOS formation region;

[0013] Performing a second anisotropic etching to form source-drain grooves in the substrate located on both sides of the first gate structure in the PMOS formation region, and simultaneously etching the nitride film in the hard mask stack in the NMOS formation region to expose the oxide film located on the top surface of the second gate structure and the top surface of the substrate;

[0014] The inner walls of the source / drain grooves are etched to transform the source / drain grooves into Σ-shaped grooves, and epitaxial growth is performed in the Σ-shaped grooves to form a heteroepitaxial layer; and the remaining hard mask stack, the nitride layer on the gate, and the oxide layer on the gate in the PMOS formation region and the NMOS formation region are removed using a maskless process.

[0015] Optionally, removing at least the remaining hard mask stack, the nitride layer on the gate, and the oxide layer on the gate in the PMOS formation region and the NMOS formation region by using a maskless process includes:

[0016] removing the oxide film exposed in the NMOS formation region to expose the nitride layer on the gate in the second gate structure and the substrate in the NMOS formation region;

[0017] removing the nitride film in the hard mask stack covering the sides of the first gate structure and the second gate structure, and removing the nitride layer on the gate in the first gate structure and the second gate structure; and

[0018] The oxide film and the gate oxide layer in the hard mask layer covering the sides of the first gate structure and the second gate structure are removed.

[0019] Optionally, the first anisotropic etching and the second anisotropic etching are performed by dry etching.

[0020] Optionally, wet etching is used to remove the remaining hard mask stack, the nitride layer on the gate, and the oxide layer on the gate in the PMOS formation region and the NMOS formation region.

[0021] Optionally, the nitride layer on the gate and the nitride film in the hard mask stack are both made of silicon nitride, and the nitride film and the nitride layer on the gate are removed by the same wet etching process.

[0022] Optionally, in the first gate structure and the second gate structure, the sidewall spacer includes a side oxide layer formed on a side of the gate and a side nitride layer formed on a side of the side oxide layer away from the gate.

[0023] Optionally, the patterned mask at least includes a bottom anti-reflection layer and a photoresist layer formed on the bottom anti-reflection layer.

[0024] Optionally, when performing the second anisotropic etching, an etching selectivity ratio between the substrate and the nitride film ranges from 2 to 8.

[0025] Optionally, in the hard mask stack, the thickness of the oxide film is The thickness of the nitride film is

[0026] Optionally, at least two second gate structures are formed in the PMOS formation region, wherein one Σ-shaped groove is formed between two adjacent second gate structures.

[0027] In the method for forming a semiconductor structure provided by the present invention, after forming a hard mask stack, a patterned mask is used to protect the NMOS formation region, and a first anisotropic etching is performed to expose the substrate on both sides of the first gate structure. The patterned mask is then removed, and a second anisotropic etching is performed, so that while forming source and drain grooves in the PMOS formation region, the oxide film covering the top surface of the second gate structure and the top surface of the substrate in the hard mask stack in the NMOS formation region is exposed. Thereafter, the oxide film is used to protect the substrate in the NMOS formation region, a Σ-shaped groove is formed in the PMOS formation region, and a heteroepitaxial layer is epitaxially grown. Finally, a maskless process is used to remove the remaining hard mask stack, the gate oxide layer, and the gate nitride layer in the PMOS formation region and the NMOS formation region. The above method only uses a single photomask process when forming the patterned mask, which helps to reduce the cost of the CMOS process.

[0028] In addition, in the method for forming a semiconductor structure provided by the present invention, in the hard mask stack covering the surface of the substrate in the NMOS formation area, the nitride film is first removed and the oxide film is retained. After a ∑-shaped groove is formed in the PMOS formation area and a heteroepitaxial layer is epitaxially grown, the remaining oxide film in the NMOS formation area can be removed by wet etching. Over-etching is easy to control and causes little damage to the substrate, which helps to improve device performance compared to the existing technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figures 1A to 1J It is a cross-sectional schematic diagram of a CMOS process at multiple steps.

[0030] Figure 2 It is a schematic flow chart of a method for forming a semiconductor structure according to an embodiment of the present invention.

[0031] Figures 3A to 3K is a schematic cross-sectional view of a method for forming a semiconductor structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0032] The following is a further detailed description of the method for forming a semiconductor structure of the present invention in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will become clearer. It should be understood that the drawings in the specification are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in illustrating the purpose of the embodiments of the present invention. It should be noted that the order of the steps in the method presented herein is not necessarily the only order for performing these steps, and some of the steps described may be omitted and / or some other steps not described herein may be added to the method. It should be understood that spatially relative terms are intended to include different orientations in use or operation in addition to the orientation of the device described in the figure. For example, if the structure in the drawing is inverted or positioned in other different ways (such as rotated), the exemplary term "on..." may also include "under..." and other orientation relationships.

[0033] In order to understand the embodiments of the present invention more clearly, the following Figures 1A to 1J A CMOS process that needs to be improved is introduced. The CMOS process includes the following processes:

[0034] First, refer to Figure 1A , providing a substrate 100 (such as a silicon substrate), the substrate 100 including a PMOS formation region A1 and an NMOS formation region A2 separated by shallow trench isolation (STI), gate structures for manufacturing PMOS and NMOS (as shown in the dotted box area) are respectively formed on the substrate 100 in the PMOS formation region A1 and the NMOS formation region A2, the gate structures each including a gate dielectric layer 101, a gate 102, an oxide layer 103 on the gate, and a nitride layer 104 on the gate stacked on the substrate 100, and sidewalls SP formed on the side of the gate 102;

[0035] Next, refer to Figure 1B , forming a hard mask stack HM along the substrate 100 and the surface of each gate structure, wherein the hard mask stack HM includes an oxide film 105 and a nitride film 106 stacked on the oxide film 105;

[0036] Afterwards, refer to Figure 1C , forming a patterned first mask layer M1, wherein the first mask layer M1 covers the NMOS formation area A2 and exposes the PMOS formation area A1;

[0037] Next, refer to Figure 1D, performing a first anisotropic etching to remove the hard mask layer HM covering the top surface of the gate structure in the PMOS formation region A1 and the hard mask layer HM covering the surface of the substrate 100, and further etching the substrate 100 to form a source-drain groove T1 in the PMOS formation region A1, exposing the gate nitride layer 104 in the gate structure. During this etching process, the gate nitride layer 104 can protect the gate 102, and the first mask layer M1 can protect the hard mask stack HM in the NMOS formation region A2 and the substrate 100 from being etched;

[0038] Afterwards, refer to Figure 1E , removing the first mask layer M1, at this time, the hard mask stack HM conformally covering the NMOS formation area A2 is exposed;

[0039] Next, refer to Figure 1F , using the hard mask stack HM to protect the NMOS formation area A2, etching the inner wall of the source / drain groove T1 to transform the source / drain groove T1 into a Σ-shaped groove T2, and performing epitaxial growth in the Σ-shaped groove T2 to form a germanium silicon layer 107;

[0040] Afterwards, refer to Figure 1G , forming a patterned second mask layer M2, wherein the second mask layer M2 covers the PMOS forming region A1 and exposes the NMOS forming region A2;

[0041] Next, refer to Figure 1H , performing a second anisotropic etching to remove the hard mask stack HM covering the top surface of the gate structure in the NMOS formation region A2 and the hard mask stack HM covering the surface of the substrate 100 , so as to expose the gate nitride layer 104 located on the top surface of the gate 102 ;

[0042] Afterwards, refer to Figure 1I , removing the second mask layer M2;

[0043] Next, referring to Figure 1J, since the gate nitride layer 104 and the hard mask stack HM located on the sides of each gate structure are already exposed, the gate nitride layer 104 and the hard mask stack HM located on the sides of each gate structure can be removed uniformly and stepwise. The resulting semiconductor structure includes a substrate 100, the gate structure formed on the substrate 100, and a PMOS source and drain region formed in the substrate 100 in the PMOS formation area A1. The gate structure includes a gate dielectric layer 101, a gate 102, and sidewalls SP covering the sides of the gate 102. The PMOS source and drain regions include a Σ-shaped groove T2 formed on both sides of the gate structure in the PMOS formation area A1, and a silicon germanium layer 107 filling the Σ-shaped groove T2.

[0044] In this CMOS process, at least two mask processes are required to form the Σ-shaped groove T2 in the PMOS forming region A1, perform the SiGe epitaxial process, and remove the hard mask stack HM in the PMOS forming region A1 and the NMOS forming region A2, as well as the nitride layer 104 on the gate, resulting in high costs. In addition, when the second mask layer M2 is used to protect the PMOS forming region A1 and expose the NMOS forming region A2 and a portion of the hard mask stack HM in the NMOS forming region A2 is etched (see FIG. Figure 1H ), the substrate 100 in the NMOS formation region A2 is easily etched back (recess) due to over-etching during the etching process, which is detrimental to the performance of the NMOS.

[0045] The following combination Figure 2 and Figures 3A to 3K A method for forming a semiconductor structure according to an embodiment of the present invention is introduced.

[0046] Reference Figure 2 and Figure 3A , performing step S1 to provide a substrate 100, wherein the substrate 100 is provided with a PMOS formation region A1 and an NMOS formation region A2. The PMOS formation region A1 and the NMOS formation region A2 respectively represent different ranges within a plane parallel to the surface of the substrate 100. The substrate 100 can be a silicon substrate, a silicon germanium substrate, a silicon carbide substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator substrate, a silicon-germanium-on-insulator substrate, or a Group III-V compound substrate (e.g., a gallium nitride substrate or a gallium arsenide substrate), and doped regions and / or isolation structures can be formed in the substrate 100. The PMOS formation region A1 and the NMOS formation region A2 are isolated from each other, for example, by shallow trench isolation (STI).

[0047] In the PMOS formation region A1, the substrate 100 can be formed with Σ-shaped grooves on both sides of the gate structure and epitaxially grown with a heterogeneous material capable of improving hole mobility in the channel region in the Σ-shaped grooves to serve as the source and drain regions of the PMOS. In this embodiment, the substrate 100 is, for example, a silicon substrate. In the PMOS formation region A1, Σ-shaped grooves are subsequently formed on both sides of the gate structure and epitaxially grown with a silicon germanium layer to serve as the source and drain regions of the PMOS.

[0048] Continue to refer to Figure 3A , performing step S2 to form a first gate structure 10 and a second gate structure 20 in the PMOS forming region A1 and the NMOS forming region A2 respectively.

[0049] like Figure 3AAs shown, the PMOS formation region A1 is formed with at least one first gate structure 10. As an example, the PMOS formation region A1 is formed with two or more first gate structures 10. The NMOS formation region A2 is formed with at least one second gate structure 20. As an example, the NMOS formation region A2 is formed with two or more second gate structures 20. The first gate structure 10 and the second gate structure 20 can be formed simultaneously on the substrate 100 and thus can have the same or similar materials and structures. In this embodiment, the first gate structure 10 and the second gate structure 20 each include at least a gate dielectric layer 101 stacked on the substrate 100, a gate 102, a gate oxide layer 103, a gate nitride layer 104, and sidewall spacers SP formed on the sides of the gate 102. The gate dielectric layer 101 is, for example, silicon oxide. The gate 102 is, for example, a doped polysilicon gate, a metal gate, or a multi-layer composite structure gate. The gate oxide layer 103 is, for example, silicon oxide. The gate nitride layer 104 is, for example, silicon nitride. The nitride layer 104 on the gate can protect the gate 102 during the subsequent process of etching a groove in the substrate 100. The sidewall spacer SP is, for example, a composite sidewall spacer, which includes a side oxide layer SP1 formed on the side of the gate 102 and a side nitride layer SP2 formed on the side of the side oxide layer SP1 away from the gate 102. The sidewall spacer SP covers the side surfaces of the gate dielectric layer 101, the gate 102, the gate oxide layer 103, and the gate nitride layer 104.

[0050] Reference Figure 2 and Figure 3B , perform step S3, conformally form a hard mask stack HM along the surface of the substrate 100, the first gate structure 10 and the second gate structure 20, the hard mask stack HM includes an oxide film 105 (for example, silicon oxide) and a nitride film 106 (for example, silicon nitride) stacked on the oxide film 105. In the subsequent etching process for forming source and drain grooves in the PMOS formation area A1, the hard mask stack HM is first etched and the substrate 100 is further etched to facilitate the control of etching accuracy. The hard mask stack HM can also protect the NMOS formation area A2 when the semiconductor process is performed in the PMOS formation area A1. As an example, in the hard mask stack HM, the thickness of the oxide film 105 is The thickness of the nitride film 106 is

[0051] Reference Figure 2 and Figure 3C, step S4 is performed to form a patterned mask 110. The patterned mask 110 covers the NMOS formation area A2 and exposes the PMOS formation area A1. The patterned mask 110 is used to protect the hard mask stack HM in the NMOS formation area A2 when the hard mask stack HM in the PMOS formation area A1 is subsequently etched. The patterned mask 110 may include a photoresist layer (PR). In this embodiment, the patterned mask 110 includes at least a bottom anti-reflective layer (BARC) (not shown) and a photoresist layer formed on the bottom anti-reflective layer.

[0052] Reference Figure 2 and Figure 3D , step S5 is executed to perform a first anisotropic etching to expose the gate nitride layer 104 in the first gate structure 10 and the surface of the substrate 100 on both sides of the PMOS formation area A1. The first anisotropic etching is performed, for example, by dry etching, and its etching direction is, for example, along the normal direction of the substrate 100 (i.e., the direction perpendicular to the top surface of the substrate 100). After etching, the lateral extension portion of the hard mask stack HM located above the top surface of the first gate structure 10 and the lateral extension portion located on the surface of the substrate 100 are removed. During the etching process, a silicon nitride etching process can be first used to etch the nitride film 106 in the hard mask stack HM to expose the oxide film 105, and then a silicon oxide etching process can be used to etch the oxide film 105, thereby exposing the gate nitride layer 104 in the first gate structure 10 and the surface of the substrate 100 on both sides of the first gate structure 10. During the etching process, the gate nitride layer 104 can protect the gate 102 , and the patterned mask 110 can protect the hard mask stack HM in the NMOS formation region A2 and the substrate 100 from being etched.

[0053] Reference Figure 2 and Figure 3E , executing step S6, removing the patterned mask 110 to expose the hard mask stack HM in the NMOS formation region A2.

[0054] Reference Figure 2 and Figure 3F Then, step S7 is performed to perform a second anisotropic etching to form source / drain grooves T1 in the substrate 100 on both sides of the first gate structure 10 in the PMOS formation region A1. Due to the protection of the hard mask stack HM, the substrate 100 in the NMOS formation region A2 will not be etched.

[0055] The longitudinal cross-section of the source / drain recess T1 is, for example, U-shaped. In this embodiment, by adjusting the etching process, the nitride film 106 in the hard mask stack HM in the NMOS formation region A2 can be simultaneously etched during the second anisotropic etching. More specifically, the lateral extension of the nitride film 106 in the hard mask stack HM above the top surface of the second gate structure 20 and the lateral extension of the nitride film 106 on the surface of the substrate 100 are removed, thereby exposing the oxide film 105 located on the top surface of the second gate structure 20 and the top surface of the substrate 100 in the NMOS formation region A2. The second anisotropic etching is, for example, dry etching. Optionally, during the second anisotropic etching, the etching selectivity between the substrate 100 and the nitride film 106 in the hard mask stack HM ranges from 2 to 8, more specifically, 5. The specific etching process parameters and etching selectivity can be adjusted according to the thickness of the nitride film 106.

[0056] Reference Figure 2 、 Figure 3G and Figure 3H Then, step S8 is performed to etch the inner wall of the source / drain groove T1 to transform the source / drain groove T1 into a Σ-shaped groove T2, and perform epitaxial growth in the Σ-shaped groove T2 to form a heteroepitaxial layer. In this embodiment, the heteroepitaxial layer is a silicon germanium layer 107.

[0057] like Figure 3G As shown, the inner wall of the source / drain groove T1 is first etched to transform the source / drain groove T1 into a Σ-shaped groove T2. During this process, since the substrate 100 in the NMOS formation region A2 is covered by the oxide film 105 in the hard mask stack HM, by retaining an appropriate thickness of the oxide film 105 and selecting an etching process with high etch selectivity for the substrate 100 and silicon oxide, the Σ-shaped groove T2 can be formed in the PMOS formation region A1 while the substrate 100 in the NMOS formation region A2 is not etched. In this embodiment, for example, tetramethylammonium hydroxide (TMAH) is used as an etchant to etch the inner wall of the source / drain groove T1 to transform the source / drain groove T1 into a Σ-shaped groove T2. The sidewalls of the Σ-shaped groove T2 have a concave angle extending below the first gate structure 10. The concave angle facilitates the subsequently formed source or drain region to generate stress in the substrate 100 in the channel region, thereby improving carrier mobility. As an example, at least two first gate structures 10 are formed in the PMOS forming region A1 , wherein a Σ-shaped groove T2 is formed between two adjacent first gate structures 10 , and the Σ-shaped groove T2 is shared by the two adjacent first gate structures 10 .

[0058] like Figure 3HAs shown, epitaxial growth is performed within the Σ-shaped recess T2 to form a silicon-germanium layer 107 using an epitaxial growth process. Specifically, a silicon-germanium seed layer can be first formed on the inner wall of the Σ-shaped recess T2, and then a selective epitaxial process can be performed to form the silicon-germanium layer 107. During the epitaxial process, P-type dopant ions (such as boron) can be added to the silicon-germanium layer 107 to improve conductivity. After the silicon-germanium layer 107 is formed, a silicon layer can be formed on the surface of the silicon-germanium layer 107 using an epitaxial process. During the epitaxial process, since the substrate 100 in the NMOS formation region A2 is covered by the oxide film 105 in the hard mask stack HM, epitaxial growth can be avoided on the surface of the substrate 100 in the NMOS formation region A2.

[0059] Reference Figure 2 , performing step S9, using a maskless process to remove at least the remaining hard mask stack HM, the gate oxide layer 103, and the gate nitride layer 104 in the PMOS formation region A1 and the NMOS formation region A2.

[0060] Specifically, refer to Figure 3I First, the oxide film 105 exposed in the NMOS formation region A2 is removed, exposing the gate nitride layer 104 in the second gate structure 20 and the substrate 100 in the NMOS formation region A2. As an example, the etching selectivity between the oxide film 105 and other materials exposed on the substrate 100 can be utilized to select a corresponding etching process to remove the oxide film 105 without the need for a mask. Specifically, wet etching can be used, more specifically, using a dilute hydrofluoric acid (DHF) solution. Since the thickness of the oxide film 105 is set to be relatively thin, the etching time can be controlled to remove the oxide film 105 without damaging the substrate 100. For example, using a DHF solution with a ratio of 1:100, the etching time is approximately 30 seconds to 90 seconds.

[0061] Reference Figure 3J Then, the nitride film 106 in the hard mask stack M2 covering the sides of the first gate structure 10 and the second gate structure 20 is removed, and the gate nitride layer 104 in the first gate structure 10 and the second gate structure 20 is removed.

[0062] By removing the oxide film 105 exposed in the NMOS formation region A2, the gate nitride layer 104 in the second gate structure 20 is exposed, and the gate nitride layer 104 in the first gate structure 10 has already been exposed in step S5. Therefore, the gate nitride layer 104 in the first gate structure 10 and the second gate structure 20 can be removed by the same etching process. In this embodiment, the gate nitride layer 104 and the nitride film 106 in the hard mask stack HM are both made of silicon nitride. Therefore, the gate nitride layer 104 and the nitride film 106 in the hard mask stack HM covering the sides of the first gate structure 10 and the second gate structure 20 can be removed by the same etching process. In addition, by utilizing the etching selectivity of silicon nitride to other materials exposed on the substrate 100, the corresponding etching process is selected to remove the nitride film 106 and the gate nitride layer 104 without the need for a mask. As an example, the nitride film 106 and the nitride layer 104 on the gate are removed by wet etching, for example, using a phosphoric acid solution with a ratio of 85%, and the etching time is about 200s to 600s.

[0063] Afterwards, if Figure 3K As shown, the oxide film 105 in the hard mask stack HM covering the sides of the first gate structure 10 and the second gate structure 20 is removed. During this process, the gate oxide layer 103 exposed on the top of the first gate structure 10 and the second gate structure 20 is also removed. In this embodiment, the oxide film 105 and the gate oxide layer 103 are both silicon oxide. Therefore, by utilizing the etching selectivity of silicon oxide and other materials exposed on the substrate 100, a corresponding etching process can be selected to remove the oxide film 105 and the gate oxide layer 103 without the need for a mask. For example, wet etching can be used. Specifically, a DHF solution with a ratio of 1:100 can be used, and the etching time is about 30 seconds to 90 seconds.

[0064] In the method for forming the semiconductor structure described in the above embodiment, after forming the hard mask stack HM covering the first gate structure 10, the second gate structure 20 and the substrate 100, a patterned mask 110 is used to protect the NMOS formation region A2, and the hard mask stack HM of the PMOS formation region A1 is etched by a first anisotropic etching to expose the substrate 100 on both sides of the first gate structure 10 of the PMOS formation region A1; then, the patterned mask 110 is removed, and a second anisotropic etching is performed to form source and drain grooves T1 in the substrate 100 on both sides of the first gate structure 10 of the PMOS formation region A1, and simultaneously expose the source and drain grooves T2. The oxide film 105 covering the top surface of the second gate structure 20 and the top surface of the substrate 100 in the hard mask stack HM in the NMOS formation region A2 is removed. The oxide film 105 in the NMOS formation region A2 is then used to protect the substrate 100 in the NMOS formation region A2. A Σ-shaped recess T2 is formed in the PMOS formation region A1, and a silicon germanium layer 107 is epitaxially grown within the Σ-shaped recess T2. Finally, a maskless process is used to remove the remaining hard mask stack HM in the PMOS formation region A1 and the NMOS formation region A2, as well as the upper gate oxide layer 103 and the upper gate nitride layer 104 in the first gate structure 10 and the second gate structure 20. The above method only uses a single photomask process to form the patterned mask 110, which helps reduce the cost of the CMOS process.

[0065] In addition, in the method for forming the semiconductor structure described in the above embodiment, in the hard mask stack HM covering the surface of the substrate 100 in the NMOS formation region A2, the nitride film 106 is first removed and the oxide film 105 is retained. After the Σ-shaped groove T2 is formed in the PMOS formation region A1 and the germanium silicon layer 107 is epitaxially grown, the remaining oxide film 105 in the NMOS formation region A2 can be removed by wet etching. Over-etching is easy to control, and the damage to the substrate 100 is small, which reduces the risk of the substrate 100 being etched back, and helps to improve device performance.

[0066] The above description is only a description of the preferred embodiment of the present invention, and does not limit the scope of the rights of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the scope of protection of the technical solution of the present invention.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, wherein the substrate is provided with a PMOS formation region and an NMOS formation region; A first gate structure and a second gate structure are formed in the PMOS formation region and the NMOS formation region, respectively, wherein the first gate structure and the second gate structure each include at least a gate dielectric layer, a gate, an oxide layer on the gate, a nitride layer on the gate, and sidewalls formed on the sides of the gate; Conformally forming a hard mask stack along surfaces of the substrate, the first gate structure, and the second gate structure, the hard mask stack comprising an oxide film and a nitride film stacked on the oxide film; forming a patterned mask to cover the NMOS formation region and expose the PMOS formation region; Performing a first anisotropic etching to expose the gate nitride layer in the first gate structure and the substrate surface where the PMOS formation region is located on both sides of the first gate structure; removing the patterned mask to expose the hard mask stack in the NMOS formation region; Performing a second anisotropic etching to form source-drain grooves in the substrate located on both sides of the first gate structure in the PMOS formation region, and simultaneously etching the nitride film in the hard mask stack in the NMOS formation region to expose the oxide film located on the top surface of the second gate structure and the top surface of the substrate; The inner walls of the source / drain grooves are etched to transform the source / drain grooves into Σ-shaped grooves, and epitaxial growth is performed in the Σ-shaped grooves to form a heteroepitaxial layer; and the remaining hard mask stack, the nitride layer on the gate, and the oxide layer on the gate in the PMOS formation region and the NMOS formation region are removed using a maskless process.

2. The forming method according to claim 1, wherein: Removing at least the remaining hard mask stack, the nitride layer on the gate, and the oxide layer on the gate in the PMOS formation region and the NMOS formation region using a maskless process includes: removing the oxide film exposed in the NMOS formation region to expose the nitride layer on the gate in the second gate structure and the substrate in the NMOS formation region; removing the nitride film in the hard mask stack covering the sides of the first gate structure and the second gate structure, and removing the nitride layer on the gate in the first gate structure and the second gate structure; and The oxide film and the gate oxide layer in the hard mask stack covering the sides of the first gate structure and the second gate structure are removed.

3. The forming method according to claim 1, wherein: The first anisotropic etching and the second anisotropic etching are performed by dry etching.

4. The forming method according to claim 1, wherein: The remaining hard mask stack, the nitride layer on the gate, and the oxide layer on the gate in the PMOS formation region and the NMOS formation region are removed by wet etching.

5. The forming method according to claim 4, wherein: The nitride layer on the gate and the nitride film in the hard mask stack are both made of silicon nitride, and the nitride film and the nitride layer on the gate are removed by the same wet etching process.

6. The forming method according to claim 1, wherein: In the first gate structure and the second gate structure, the sidewall spacer includes a side oxide layer formed on a side of the gate and a side nitride layer formed on a side of the side oxide layer away from the gate.

7. The forming method according to claim 1, wherein: The patterned mask at least includes a bottom anti-reflection layer and a photoresist layer formed on the bottom anti-reflection layer.

8. The forming method according to any one of claims 1 to 7, wherein: When performing the second anisotropic etching, the etching selectivity ratio between the substrate and the nitride film ranges from 2 to 8.

9. The forming method according to any one of claims 1 to 7, wherein: In the hard mask stack, the thickness of the oxide film is The thickness of the nitride film is 10. The forming method according to any one of claims 1 to 7, wherein: At least two second gate structures are formed in the PMOS forming region, wherein one Σ-shaped groove is formed between two adjacent second gate structures.

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