Integrated circuit device with replica and fill cells for reducing local layout effects

Abstract

The IC device may include a functional region and copy and fill cells that may reduce local layout effects in the IC device. The functional region includes functional cells, such as logic cells or memory cells. The white space may be between the first functional region and the second functional region. A first portion of the empty space may be filled with replica cells, each replica cell being a replica of a cell in the first functional region. A second portion of the empty space may be filled with a non-functional filling unit. The first functional region is closer to the copy unit than to the fill unit. A third portion of the empty space may be filled with replica cells, each replica cell being a replica of a cell in the second functional region. The second portion is between the first portion and the third portion.

Description

Background Art

[0001] Local layout effects or layout-related effects are environmental effects that negatively affect the electrical characteristics of a semiconductor device due to its physical layout and proximity to other features on an integrated circuit. The physical environment in which a semiconductor device resides can change its characteristics. For example, the threshold voltage shift of a given device (e.g., a transistor) can change based on its neighborhood. Local layout effects can be caused by parasitic capacitance, parasitic resistance, or parasitic inductance that exist between different components in the circuit layout. Additionally or alternatively, local layout effects can be caused by mechanical stress introduced by nearby structures. Local layout effects may introduce unnecessary coupling, delays, signal distortion, resulting in performance degradation or even functional failure. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] The embodiments will be easily understood by the following detailed description in conjunction with the accompanying drawings. For ease of description, similar reference numerals represent similar structural elements. The embodiments are illustrated in the figures of the accompanying drawings by way of example, not by way of limitation.

[0003] Figure 1 An integrated circuit (IC) device having a replica cell and a filler cell according to some embodiments of the present disclosure is shown.

[0004] Figure 2A-2E A process of forming an IC device layout including replica cells and fill cells according to some embodiments of the present disclosure is shown.

[0005] Figures 3A-3E Another process of forming an IC device layout including replica cells and fill cells according to some embodiments of the present disclosure is shown.

[0006] Figure 4 Example units according to some embodiments of the present disclosure are shown.

[0007] Figure 5A and 5B Another example unit according to some embodiments of the present disclosure is shown.

[0008] Fig. 6A and 6B is a top view of a wafer and die that may include one or more IC devices with duplicate cells and filler cells according to some embodiments of the present disclosure.

[0009] Figure 7 is a side cross-sectional view of an example IC package that may include one or more IC devices having duplicate cells and filler cells according to some embodiments of the present disclosure.

[0010] Figure 8is a cross-sectional side view of an IC device assembly that may include components having one or more IC devices having a duplicate cell and a filler cell according to some embodiments of the present disclosure.

[0011] Fig. 9 is a block diagram of an example computing device that may include one or more components having one or more IC devices having a copy unit and a padding unit according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0012] The systems, methods, and devices of the present disclosure each have several innovative aspects, no single one of which is solely responsible for all of the desirable attributes disclosed herein.The details of one or more implementations of the subject matter described in this specification are set forth in the following description and the accompanying drawings.

[0013] Automatic placement and routing (APR) tools are typically used to place design blocks in chip areas for forming IC devices. Design blocks can be blocks of functional units, such as logic units, memory units, etc. Logic units can have one or more logic functions. Memory units can have one or more storage functions. There may be gaps between design blocks. Such gaps are referred to as "white spaces". White spaces are typically required to be filled for various purposes, such as to meet one or more density requirements, to establish power continuity (e.g., power supply, VDD or VSS continuity), to establish N-well or P-well continuity, etc. Functional units in a design block may cause local layout effects in its adjacent design blocks. It is usually difficult to accurately predict the impact of local layout effects, so minimizing local layout effects may be beneficial to achieving the desired performance of the IC device.

[0014] Embodiments of the present disclosure provide an IC device having a replica cell and a fill cell for reducing local layout effects. The replica cell is formed by cloning or duplicating a functional cell (e.g., a cell having a logic or storage function) in a design block, but is placed outside the design block. For example, the replica cell may be adjacent to the edge of the design block. Using the replica cell, local layout effects can be pushed to an area farther from the design block. The area may be at least partially filled with a fill cell. A fill cell is a non-functional cell, which may have no logic or storage function. The replica cell and the fill cell may be designed and formed based on a combination of a design block integration method and a blank space filling method to provide additional protection against local layout effects.

[0015] In various embodiments of the present disclosure, the IC device includes multiple functional areas, each of which may include one or more logic units, memory units, other types of functional units, or combinations thereof. Functional areas may also be referred to as functional blocks, active areas, or active blocks. One or more near areas between two or more functional areas may be identified. Each near area may be adjacent to a functional area and include one or more replica units, each replica unit being a replica of a unit in a functional area. The near area may include replicas of one or more rows of units in a functional area. In some embodiments, the height of the near area may not exceed 2 microns. In an example, the near area may have a height that is the same as or substantially similar to the height of the unit in the functional area. In addition to one or more near areas, one or more far areas between the functional areas may also be identified. Each functional group is closer to the near area than to the far area. Each far area may include one or more filling units. A filling unit may include one or more dummy devices that do not have a logic or storage function.

[0016] Functional areas may correspond to design blocks placed in a design area, for example, by using an APR tool. Near and far areas may be in the blank space between design blocks. Near and far areas may be identified using a grid placed on the design area. The grid may include components arranged in rows and columns. The components may have predetermined sizes, such as predetermined heights, predetermined widths, etc. In an example, the smallest halo area that shares one or more components with a functional area may be identified as a near area of ​​a functional area. An area that does not share any components with any functional area may be identified as a far area. The size of each component may affect the size of a near or far area. In some embodiments, the size of each component may be determined based on a design block (e.g., the type of design block, the components in the design block, the shape of the design block, the size of the design block, etc.). For example, the height or width of each component may be equal to the height of an individual unit in a functional group. In some embodiments, the height or width of each component may be in the range of from approximately 100 nanometers to approximately 900 nanometers, for example, in the range of from approximately 200 nanometers to approximately 500 nanometers.

[0017] The present disclosure provides a blank space filling method based on cloning reference lines around active circuit systems through a predetermined number of cell rows, which can push local layout effects away from the adjacent blank space / design block boundaries. The cloning information can be shared with the upstream extraction flow in the process design tool kit (PDK), enabling designers to predict and understand what will be adjacent to the cells drawn by the designer. The blank space filling method can enable protection of a predetermined number of cell rows against local layout effects and density fluctuations. Cloning functional cells can allow for an almost seamless transition between design blocks and blank spaces. Design area can be saved by ensuring edge conditions. In addition, consistent boundary conditions can be provided for block-level design rules and blank space filling flows. The blank space filling method can also design block design rule cleanliness independently of context. Compared with currently available technologies, the blank space filling method in the present disclosure can promote faster design closure and ease of use.

[0018] It should be noted that in certain settings, the term "nanoribbon" has been used to describe an elongated semiconductor structure having a substantially rectangular transverse cross-section (e.g., a cross-section in a plane perpendicular to the longitudinal axis of the structure), while the term "nanowire" has been used to describe a similar structure, but having a substantially circular or square transverse cross-section. In the following, the single term "nanoribbon" is used to describe an elongated semiconductor structure regardless of the shape of the transverse cross-section. Thus, as used herein, the term "nanoribbon" is used to cover elongated semiconductor structures having a substantially rectangular transverse cross-section (possibly with rounded corners), elongated semiconductor structures having a substantially square transverse cross-section (possibly with rounded corners), elongated semiconductor structures having a substantially circular or elliptical / oval transverse cross-section, and elongated semiconductor structures having any polygonal transverse cross-section. The longitudinal axis of a structure refers to a line (e.g., an imaginary line) extending down the center of the structure in a direction perpendicular to the transverse cross-section of the structure.

[0019] In the following, some descriptions may refer to a specific source or drain (S / D) region or contact as a source region / contact or a drain region / contact. However, unless otherwise specified, it does not matter which region / contact of a transistor or diode is considered to be a source region / contact and which region / contact is considered to be a drain region / contact, because, as is common in the field of field effect transistors (FETs), the designation of source and drain is generally interchangeable. Therefore, the description of some illustrative embodiments of source and drain regions / contacts provided herein is applicable to embodiments in which the designation of source and drain electrode regions / contacts can be reversed.

[0020] As used herein, the term "metal layer" may refer to a layer above a substrate that includes conductive interconnect structures for providing electrical connections between different IC components. The metal layers described herein may also be referred to as "interconnect layers" to clearly indicate that these layers include conductive interconnect structures that may be metal, but need not be metal.

[0021] The systems, methods, and devices of the present disclosure each have several innovative aspects, no single one of which is solely responsible for all of the desirable attributes disclosed herein.The details of one or more implementations of the subject matter described in this specification are set forth in the following description and the accompanying drawings.

[0022] In the following detailed description, various aspects of the illustrative embodiments may be described using terms commonly used by those skilled in the art to convey the essence of their work to others skilled in the art. For example, the term "connected" refers to a direct electrical or magnetic connection between connected things without any intervening devices, while the term "coupled" refers to a direct electrical or magnetic connection between connected things or an indirect connection through one or more passive or active intervening devices. The term "circuit" refers to one or more passive and / or active components that are arranged to cooperate with each other to provide a desired function. If used, the terms "oxide", "carbide", "nitride", etc. refer to compounds containing oxygen, carbon, nitrogen, etc., respectively, the term "high-k dielectric" refers to a material having a higher dielectric constant (k) than silicon oxide, and the term "low-k dielectric" refers to a material having a lower k than silicon oxide. The terms "substantially", "close", "approximately", "near", and "about" generally refer to within + / -20% of a target value based on the context of a specific value described herein or known in the art. Similarly, terms indicating the orientation of various elements, such as "coplanar," "perpendicular," "orthogonal," "parallel," or any other angle between elements, generally refer to within + / - 5%-20% of the target value based on the context of the specific value described herein or known in the art.

[0023] As used herein, the terms "above," "below," "between," and "on" refer to the relative position of one material layer or component with respect to other layers or components. For example, a layer disposed above or below another layer may be in direct contact with the other layer, or may have one or more intervening layers. Additionally, a layer disposed between two layers may be in direct contact with the two layers, or may have one or more intervening layers. Conversely, a first layer over a second layer is in direct contact with the second layer. Similarly, unless expressly stated otherwise, a feature disposed between two features may be in direct contact with the adjacent feature, or may have one or more intervening layers.

[0024] For purposes of this disclosure, the term "or" means an inclusive "or" rather than an exclusive "or". The phrase "A and / or B" or the phrase "A or B" means (A), (B), or (A and B). For purposes of this disclosure, the phrase "A, B and / or C" or the phrase "A, B or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C). When used with reference to a measurement range, the term "between..." includes the ends of the measurement range. As used herein, the notation "A / B / C" means (A), (B), and / or (C).

[0025] The description may use the phrases "in an embodiment" or "in multiple embodiments," each of which may refer to one or more of the same or different embodiments. In addition, as used with respect to the embodiments of the present disclosure, the terms "including," "comprising," "having," and the like are synonymous. The present disclosure may use perspective-based descriptions, such as "above," "below," "top," "bottom," and "side"; such descriptions are used to facilitate discussion and are not intended to limit the application of the disclosed embodiments. The drawings are not necessarily drawn to scale. Unless otherwise specified, the use of ordinal adjectives "first," "second," and "third," etc. to describe common objects merely indicates that different instances of similar objects are mentioned, and is not intended to imply that the objects described must be in a given sequence, whether in time, space, ranking, or in any other manner.

[0026] In the following detailed description, reference is made to the accompanying drawings which form a part hereof and in which are shown by way of example embodiments that may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description should not be taken in a limiting sense. For convenience, if there is a collection of figures designated with different letters, for example, Fig. 6A and 6B , then the set may be referred to herein without the letters, for example as “FIG. 6”.

[0027] In the accompanying drawings, some schematic examples of exemplary structures of various devices and components described herein may be shown with exact right angles and straight lines, but it should be understood that when any structure described herein is examined using, for example, scanning electron microscope (SEM) images or transmission electron microscope (TEM) images, these schematic examples may not reflect real-life process limitations that may cause features to appear less than "ideal." In such images of real structures, possible processing defects may also be visible, such as imperfectly straight edges of material, tapered vias or other openings, unintentional rounding of corners or thickness variations of different material layers, occasional spiral, edge or combined dislocations within a crystal region, and / or occasional dislocation defects of single atoms or clusters of atoms. Other defects that are not listed here but are common in the field of device manufacturing may exist. Examining layout and mask data using, for example, an optical microscope, TEM or SEM and reverse engineering portions of the device to reconstruct the circuit, and / or examining cross-sections of the device using, for example, physical failure analysis (PFA) to detect the shape and position of various device elements described herein will allow the presence of duplicate cells and filler cells described herein to be determined.

[0028] Various operations may be described in turn as multiple discrete actions or operations in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be interpreted as implying that these operations are necessarily dependent on the order. In particular, these operations may not be performed in the order presented. The described operations may be performed in an order different from the described embodiments. Various additional operations may be performed, and / or the described operations may be omitted in additional embodiments.

[0029] The various replication units and filler units described herein may be implemented in or in association with one or more components associated with an IC, or / and may be implemented between various such components. In various embodiments, the components associated with the IC include, for example, transistors, diodes, power supplies, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, etc. The components associated with the IC may include components mounted on the IC or components connected to the IC. The IC may be analog or digital and may be used in a variety of applications, such as microprocessors, optoelectronic devices, logic blocks, audio amplifiers, etc., depending on the components associated with the IC. The IC may be used as part of a chipset for performing one or more related functions in a computer.

[0030] Figure 1An IC device 100 with replica units and filling units according to some embodiments of the present disclosure is shown. The IC device 100 also includes functional units, which constitute four independent functional areas 110A-110D (collectively referred to as "functional areas 110" (single or multiple)). The replica units constitute multiple replica areas 115A-115D (collectively referred to as "replica areas 115" (single or multiple)). The filling units constitute a non-functional area 120. In other embodiments, the IC device 100 may include fewer, more, or different components. For example, the IC device 100 may include different numbers of functional units, replica units, or filling units. The IC device 100 can be formed by a process including design block integration and blank space filling, which is a process such as Figure 2A-2E The process shown in Figures 3A-3E The process described in .

[0031] Each functional area 110 can be effective in the operation of the IC device 100. The functional area 110 can have one or more logic functions, data storage functions, or some combination thereof. The functional area 110 can be a logic circuit or a memory array, or can be part thereof. In some embodiments, the four functional areas 110 can have different logic or storage functions. In an example, the functional area 110 can be a memory array, and another functional area 110 can be a control circuit that can control the operation of the memory array. In some embodiments, multiple functional areas 110 can have the same function. For example, multiple functional areas 110 can all be memory arrays.

[0032] like Figure 1 As shown, each functional area 110 includes functional units arranged in rows and columns. Functional area 110A includes three rows and 10 columns of functional units. Functional area 110B includes five rows and four columns of functional units. Functional area 110C includes four rows and six columns of functional units. Functional area 110D includes two rows and six columns of functional units. In other embodiments, the functional area 110 may include a different number of rows or columns. A functional unit is a unit component of the corresponding functional area 110. A functional unit may be a logic unit in a logic circuit or a memory unit in a memory array. Examples of functional units 110A-110D include Figure 4 Unit 400 and Figure 5A and 5B Unit 500 in.

[0033] The duplicate area 115 is a duplicate of a portion of the functional area 110. Figure 1In the embodiment of the present invention, a portion of the functional area 110A is cloned to form one replication area 115A, two portions of the functional area 110B are cloned to form two independent replication areas 115B (one replication area 115B is at the top of the functional area 110B, and the other replication area 115B is at the left side of the functional area 110B), three portions of the functional area 110C are cloned to form three independent replication areas 115C (one replication area 115C is at the top of the functional area 110C, another replication area 115C is at the right side of the functional area 110C, and another replication area 115C is at the left side of the functional area 110C), and a portion of the functional area 110D is cloned to form one replication area 115D. In other embodiments, the functional area 110 can be used to form a different number of replication areas.

[0034] Each replication region 115 is adjacent to the functional region 110 on which the replication region 115 is formed. A replication region 115 may be adjacent to another replication region 115. For example, a replication region 115B at the left side of a functional region 110B is also adjacent to a replication region 115C at the right side of a functional region 110C. A replication region 115 is also adjacent to a non-functional region 120. Figure 1 As shown, the duplicate area 115 may be between the functional area 110 and the non-functional area 120. The duplicate unit may be a unit component of the duplicate area 115. The duplicate unit is a duplicate of the functional unit. The duplicate unit may include the same components as the functional unit and have the same functions and sizes as the functional unit. In some embodiments, the functional unit or the duplicate unit may be a standard unit.

[0035] like Figure 1 As shown, the replication area may include one or more rows (or one or more columns) of replication units. For example, replication area 115A includes two rows of replication units. Replication area 115B on the top of functional area 110B includes two rows and four columns of replication units. Replication area 115C on the top of functional area 110C and replication area 115D each include a row of replication units. Replication area 115 may be formed by replicating rows (single or multiple) or columns (single or multiple) of functional units at the border of the corresponding functional area 110. For example, replication area 115A may be formed by replicating two rows of functional units in functional area 110A. The two rows of functional units in functional area 110A may be two rows at the bottom of functional area 110A, that is, two rows closest to the border where functional area 110A adjoins replication area 115A. Similarly, the duplicate region 115D may be formed by duplicating the top row of the functional cells in the functional region 110D, ie, the row at the boundary where the functional region 110D adjoins the duplicate region 115D.

[0036] Each replication region 115 may have a height along the X-axis. Alternatively, the height of the replication region may be along the Y-axis. The height of the replication region 115 may depend on the number of rows of replication units in the replication region. For example, the height of the replication region 115A may be approximately twice the height of the functional unit in the functional region 110A, and the height of the replication region 115D may be approximately the height of the functional unit in the functional region 110D. In some embodiments, the height of the replication region 115 may be in a range from approximately 100 nanometers to approximately 900 nanometers, for example, in a range from approximately 200 nanometers to approximately 500 nanometers.

[0037] The non-functional region 120 may not play a role in the operation of the IC device 100. Each fill cell in the non-functional region 120 does not implement any logic or storage function. Figure 1 As shown, the non-functional region 120 is between some of the duplicate regions 115. The non-functional region 120 is farther from each functional region 110 than the duplicate region 115 (single or multiple) of the functional region 110. The non-functional region 120 together with the duplicate region 115 can reduce the local layout impact on the functional region 110. In addition, the non-functional region 120 can be used for one or more other purposes, such as voltage stability, power rail continuity, N-well continuity, P-well continuity, heat dissipation, isolation, etc.

[0038] In some embodiments, the functional area 110 may be formed based on a design block in a design area provided by an IC designer. The design block may specify the function of the design block, the number of cells in the design block, the type of cells in the design block, etc. The copy area 115 and the non-functional area 120 may be formed based on the blank space in the design area. The blank space may be divided into a near blank space and a far blank space. The copy area 115 may be formed based on the near blank space, and the non-functional area 120 may be formed based on the far blank space. Figure 2A-2E and Figures 3A-3E To describe more details about forming functional cells, replication cells, and padding cells.

[0039] The IC device 100 (e.g., the functional area 110 in the IC device 100) can be manufactured by using one or more complementary metal oxide semiconductor (CMOS) processes, in which metal oxide semiconductor field effect transistors (MOSFETs) (such as symmetrical pairs of P-type and N-type MOSFETs) can be manufactured. In addition, metal layers can be implemented above the transistors. In some embodiments, the manufacture of the IC device 100 (or a portion of the IC device 100) can include two stages. The first stage is called the front end process (FEOL). The second stage is called the back end process (BEOL). In the FEOL, individual semiconductor device components (e.g., transistors, capacitors, resistors, etc.) can be patterned on a wafer. The FEOL stage can include a CMOS process, in which metal oxide semiconductor field effect transistors (MOSFETs) (such as symmetrical pairs of P-type and N-type MOSFETs) can be manufactured. In the BEOL, metal layers, vias, and insulating layers can be formed to interconnect individual components. The BEOL typically starts with forming a first metal layer on a wafer. The first metal layer is typically referred to as M0. More metal layers can be formed on top of M0, and these metal layers are typically referred to as M1, M2, etc.

[0040] Figure 2A-2E A process of forming an IC device layout 200 including a replica cell and a fill cell according to some embodiments of the present disclosure is shown. Figure 2A-2E The steps shown in 200 describe a process for forming an IC device layout 200, but many other processes for forming an IC device layout may be used instead. For example, the steps shown in 200 may be changed. Figure 2A-2E As another example, some steps may be changed, eliminated, or combined.

[0041] Figure 2A A design area 201 is shown that includes design blocks 210A-210D, which are collectively referred to as "design blocks 210" (single or multiple). Each design block 210 may include functional areas (such as Figure 1 The design area 201 may include a design of one of the functional areas 110 in the design area 201. The design block 210 may include information of an array of cells (e.g., standard cells). For example, the design block 210 may specify the number of rows of cells, the number of columns of cells, the components in each cell, the size of each cell, the electrical connection of one or more cells to one or more other cells or to one or more other design blocks 210, etc. A cell may include a group of transistors and interconnect structures that can provide a logic function (e.g., AND, OR, XOR, XNOR, inverter, etc.) or a storage function (e.g., flip-flop, latch, etc.). The design area 201 also includes a blank space 202. The blank space 202 may be a portion of the design area 201 that is not occupied by any design block 210. The blank space 202 may be a gap area.

[0042] exist Figure 2B , near blank blocks 213 (individually referred to as "near blank blocks" 213) and far blank blocks 230 are identified in the blank space 202. Each near blank block 213 is a portion of the blank space 202 adjacent to the design block 210. The near blank block 213 may share a border with the corresponding design block 210. The far blank block 230 is at least partially surrounded by the near blank block 213. In some embodiments, the edge of the far blank block 230 (e.g., the left edge of the far blank block 230) may be aligned with the center of the near blank block 213 between the design block 210B and the design block 210C. The center of the near blank block 213 may be the center across the Y axis. In some embodiments, the classification of a portion of the blank space 202 (i.e., whether the portion is classified as a near region or a far region) may be determined based on the attributes of the design block (single or multiple) under consideration. For example, one or more dimensions of the near blank block 213 may be determined based on the electrical characteristics of the corresponding design block 210 (or one or more components in the design block 210). Examples of electrical characteristics may include voltage, capacitance, current, etc. In some embodiments, the height of the nearly blank block 213 may correspond to the height of the cell in the design block 210. For example, the height of the nearly blank block 213 may be a predetermined multiple of the height of the cell in the design block 210. Figure 2C In the steps shown, the nearly blank block 213 can merge a predetermined number of rows of replication units.

[0043] exist Figure 2C In the embodiment, the nearly blank block 213 may be at least partially filled with a replicated cell, thereby forming replicated blocks 215A-215D (collectively referred to as "replicated blocks 215" (single or multiple)). The replicated cells may be formed by replicating cells in the design block 210. Figure 2C In the embodiment of the present invention, each replication block 215 has a single row of replication units. A gap is left between the replication blocks 215 or between the replication block 215 and the far blank block 230.

[0044] exist Figure 2D In the embodiment, some of the replicated blocks 215 are expanded to fill the gap. For example, the replicated block 215B is expanded to fill the gap between the replicated block 215A and the original replicated block 215B. In addition, new replicated blocks 215E and 215F are added to fill the gap between the design blocks 210B and 210C and the gap between the design blocks 210C and 210D. The expansion of the replicated block 215A makes the far blank block 230 smaller. Figure 2DAs shown, each replicated block 215 is adjacent to at least one design block 210, one or more other replicated blocks 215, or a far blank block 230. The replicated block 215 can be extended by adding more replicated units to the replicated block 215. These additional replicated units can be different from the original replicated units in the replicated block 215. For example, these additional replicated units can be cloned from units in the corresponding design block 210 that are different from the original replicated units.

[0045] In other embodiments, the replica block 215 may be in the same Figure 2D For example, the replica block 215A may be expanded to fill the gap between the design block 210A and the design block 210B without making the far blank block 230 smaller. Additionally or alternatively, the far blank block 230 may be expanded to fill the gap between the design block 210A and the design block 210B. Figure 2C For example, instead of replica block 215A or replica block 215B, far blank block 230 can be extended to fill the gap between design block 210A and design block 210B. Embodiments of replica block 215 include Figure 1 The copy area 115 in.

[0046] exist Figure 2E In the embodiment, the far blank block 230 is provided with a filling cell to form the non-functional block 220. The IC device layout 200 is formed. The IC device layout 200 can be used to manufacture an IC device, such as Figure 1 The IC device 100 in FIG. Figure 2A-2E The shapes, sizes or positions of the design blocks 210, near blank blocks 213, far blank blocks 230, duplicate blocks 215 and non-functional blocks 220 are used as examples. In other embodiments, the design blocks 210, near blank blocks 213, far blank blocks 230, duplicate blocks 215 or non-functional blocks 220 may have different shapes, sizes or positions.

[0047] Figures 3A-3E Another process of forming an IC device layout 300 including a replica cell and a fill cell according to some embodiments of the present disclosure is shown. Figures 3A-3E The steps shown in 300 describe a process for forming an IC device layout 300, but many other processes for forming an IC device layout may be used instead. For example, the steps shown in 300 may be changed. Figures 3A-3E As another example, some steps may be changed, eliminated, or combined.

[0048] Figure 3A A design area 301 is shown that includes design blocks 310A-210D, which are collectively referred to as "design blocks 310" (single or multiple). Each design block 310 may include functional areas (such as Figure 1Design area 301 also includes blank space 302. Blank space 302 may be a portion of design area 301 that is not occupied by any design block 310. Blank space 302 may be a gap area.

[0049] exist Figure 3B , a grid 305 is placed in a design area 301. The grid 305 includes elements 307 (individually referred to as "elements 307") arranged in six rows and 11 columns. Each element 307 may have a predetermined dimension along the X-axis or the Y-axis. In an example, the predetermined dimension of each element 307 may be the height of a cell in the design block 310. In another example, the predetermined dimension of each element 307 may be in a range from approximately 100 nanometers to approximately 900 nanometers. In some embodiments, the sizes of the elements 307 may be the same. The grid 305 may be placed in a manner such that the center of the grid 305 overlaps or is aligned with the center of the design area 301. In other embodiments, the grid 305 may include a different number of rows or columns. One or more additional rows or columns may be added to the grid 305. Similarly, one or more rows or columns may be removed from the grid 305. Even in Figure 3A In the example, the grid 305 does not cover the entire design area 301. In other embodiments, the grid 305 may fill the entire design area. Figure 3B-3E The empty space 302 is not shown.

[0050] exist Figure 3C , replicated blocks 315A-315D (collectively referred to as "replicated blocks (single or multiple) 315") are identified based on the grid 305. In the example, the replicated blocks 315 are placed in some elements 307 of the grid 305. Each of these elements 307 is partially occupied by a portion of the design block 310. These elements 307 can be determined to have significant local layout effects that should be reduced. Figure 3BIn an embodiment, cell rows 313A-313D (collectively referred to as "cell rows (single or multiple) 313") are identified in design blocks 310A-310D, respectively. Each cell row 313 may be a row of functional cells in a corresponding design block 310. Cell row 313 may be a row at a boundary of a design block 310 facing one or more other design blocks 310. Cell rows 313A-313D are cloned to generate replicated blocks 315A-315D, respectively, collectively referred to as "replicated blocks 315 (single or multiple)". Each replicated block 315 may include a single row of replicated cells. Replicated blocks 315 are outside of design block 310 and located in blank space 302. In other embodiments, multiple cell rows may be cloned to generate multiple cell rows for one or more design blocks 310.

[0051] exist Figure 3D In the embodiment of the present invention, non-functional blocks 320 are formed in portions of the blank area 302. Portions of the blank area 302 may be determined by identifying elements 307 of the grid 305 that are not on any design block 310 or replicated block 315. Filling cells may be provided to the identified elements 307 of the grid 305 to form the non-functional blocks 320. After the replicated blocks 315 and the non-functional blocks 320 are formed, gaps still exist in the blank area 302. These gaps are not occupied by any design block 310, replicated block 315, or non-functional block 320.

[0052] exist Figure 3E Some or all of the gaps are filled. Figure 3E Various arrows are shown indicating the expansion of some of the replicated blocks 315 (e.g., by adding another row of cells) and the expansion of the non-functional blocks 320 (e.g., by adding more filler cells). In addition, new replicated cells are formed in the gap between the design block 310B and the design block 310C. An intermediate boundary 340A is identified. Some of the cells in the design block 310B are cloned and provided to the gap between the design block 310B and the intermediate boundary 340A. Some of the cells in the design block 310C are cloned and provided to the gap between the design block 310C and the intermediate boundary 340A. Similarly, an intermediate boundary 340B is identified between the design block 310C and the design block 310D. Some of the cells in the design block 310C are cloned and provided to the gap between the design block 310C and the intermediate boundary 340B. Some of the cells in the design block 310D are cloned and provided to the gap between the design block 310D and the intermediate boundary 340B.

[0053] The IC device layout 300 is formed. The IC device layout 300 may be used to manufacture an IC device, such as Figure 1 The IC device 100 in FIG. Figures 3A-3EThe shapes, sizes or positions of the design block 310, the duplicate block 315 and the non-functional block 320 in FIG. 3 are for example. In other embodiments, the design block 310, the duplicate block 315 or the non-functional block 320 may have different shapes, sizes or positions.

[0054] Figure 4 An example cell 400 according to some embodiments of the present disclosure is shown. The cell 400 may be a standard cell. The cell 400 may have a logic function or a storage function. In some embodiments, the cell 400 may be a logic cell, a memory cell, etc. The boundaries of the cell 400 are defined by Figure 4 . The unit 400 includes semiconductor structures 410A and 410B (collectively referred to as "semiconductor structures (single or multiple) 410"), an electrical insulator 420, a via 430, vias 440A-440C (collectively referred to as "vias (single or multiple) 440"), gate electrodes 450A-450C (collectively referred to as "gate electrodes (single or multiple) 450"), electrodes 460A-460C (collectively referred to as "electrodes (single or multiple) 460"), and metal tracks 470A and 470B (collectively referred to as "metal tracks (single or multiple) 470"). The metal track 470 may be in a metal layer in the unit 400. In other embodiments, the unit 400 may include different, fewer, or more components. For example, the unit 400 may include different numbers of semiconductor structures 410, gate electrodes 450, or electrodes 460. As another example, the unit 400 may include one or more other metal layers.

[0055] Figure 4 An X-axis, a Y-axis, and a Z-axis are shown. The X-axis may be a vertical axis of the cell 400. The dimension of the cell 400 along the X-axis (e.g., the distance between two opposite boundaries of the cell 400 along the Y-axis) may be the height of the cell 400. The dimension of the cell 400 along the Y-axis (e.g., the distance between two opposite boundaries of the cell 400 along the X-axis) may be the width of the cell 400. The distance between two adjacent gate electrodes 450 (e.g., the distance between gate electrodes 450A and 450B or the distance between gate electrodes 450A and 450C) may be the contacted poly pitch of the cell 400. In some embodiments, the metal layer may be arranged over the semiconductor structure 410, the electrical insulator 420, the via 430, the via 440, the gate electrode 450, and the electrode 460 in a direction along the Z-axis.

[0056] The semiconductor structure 410 may include one or more semiconductor materials. In some embodiments, the semiconductor structure 410 may be a semiconductor substrate, and a transistor may be formed based on the semiconductor substrate. In some embodiments, the semiconductor structure 410 may include semiconductors with opposite doping types. For example, the semiconductor structure 410A may be an N-type semiconductor structure, and the semiconductor structure 410B may be a P-type semiconductor structure. In other embodiments, the semiconductor structure 410 may include semiconductors with the same doping type. In some embodiments, the semiconductor structure 410 may have a planar structure. In other embodiments, the semiconductor structure 410 may have a non-planar structure, such as a fin, a nanoribbon, etc.

[0057] The semiconductor structure 410 may have a longitudinal axis. In some embodiments, the dimension of the semiconductor structure 410 along its longitudinal axis may be greater than the dimension of the semiconductor structure 410 in a direction perpendicular to the longitudinal axis. For example, the semiconductor structure 410 may have a longitudinal axis parallel to the Y axis. The dimension of the semiconductor structure 410 along the Y axis may be greater than the dimension of the semiconductor structure 410 along the X axis or the Z axis. The semiconductor structure 410 may also have a transverse cross-section, which may be a cross-section in a plane perpendicular to its longitudinal axis.

[0058] The semiconductor structure 410 may include a source region, a channel region, and a drain region of a transistor. The channel region may be between the source region and the drain region in the direction along the Y axis. The channel region may be above a portion of the gate electrode 450A. The source region may be above a portion of the electrode 460. The drain region may be above a portion of another electrode 460. For example, the portion of the semiconductor structure 410A below the electrode 460A may be one of the source region and the drain region of the transistor, the portion of the semiconductor structure 410A below the gate electrode 450A may be the channel region of the transistor, and the portion of the semiconductor structure 410A below the electrode 460C may be the other of the source region and the drain region of the transistor. Similarly, the portion of the semiconductor structure 410B below the electrode 460B may be one of the source region and the drain region of the transistor, the portion of the semiconductor structure 410B below the gate electrode 450A may be the channel region of the transistor, and the portion of the semiconductor structure 410B below the electrode 460C may be the other of the source region and the drain region of the transistor. The two transistors may be FETs. In an embodiment, the two transistors are both P-type transistors, such as P-type metal oxide semiconductor (PMOS) transistors. In another embodiment, the two transistors are both N-type transistors, such as N-type metal oxide semiconductor (NMOS) transistors. In yet another embodiment, one of the two transistors is an N-type transistor and the other is a P-type transistor.

[0059] The channel region of the transistor may include a channel material. The channel material may be composed of a semiconductor material system including, for example, an N-type or P-type material system. In some embodiments, the channel material may include a high-mobility oxide semiconductor material, such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide. In some embodiments, the channel material may include a compound semiconductor having a first sub-lattice of at least one element from Group III of the periodic table (e.g., Al, Ga, In) and a second sub-lattice of at least one element from Group V of the periodic table (e.g., P, As, Sb). In some embodiments, the channel material may include a compound semiconductor having a first sub-lattice of at least one element from Group II of the periodic table (e.g., Zn, Cd, Hg) and a second sub-lattice of at least one element from Group IV of the periodic table (e.g., C, Si, Ge, Sn, Pb). In some embodiments, the channel material is an epitaxial semiconductor material deposited using an epitaxial deposition process. The epitaxial semiconductor material can have a polycrystalline structure with a grain size between about 2 nm and 100 nm including all values ​​and ranges therein.

[0060] For some example N-type transistor embodiments (i.e., for embodiments where the transistor is an NMOS transistor or an N-type TFET), the channel material may advantageously include a III-V material having high electron mobility, such as, but not limited to, InGaAs, InP, InSb, and InAs. For some such embodiments, the channel material may be a ternary III-V alloy, such as InGaAs, GaAsSb, InAsP, or InPSb. For some In x Ga 1-x As fin embodiments, the In content (x) may be between 0.6 and 0.9, and may advantageously be at least 0.7 (e.g., In 0.7 Ga 0.3 As). In some embodiments with the highest mobility, the channel material may be an intrinsic III-V material, i.e., a III-V semiconductor material that is not intentionally doped with any electrically active impurities. In alternative embodiments, a nominal impurity dopant level may be present in the channel material, e.g., to further fine tune the threshold voltage Vt, or to provide a HALO pocket implant, etc. However, even for impurity doped embodiments, the impurity dopant level in the channel material may be relatively low, e.g., less than 100 μm per cubic centimeter (cm3). -3 )10 15 dopant atoms, and advantageously less than 10 13 cm -3 These materials may be amorphous or polycrystalline, for example with a grain size between 0.5 nm and 100 nm.

[0061] For some example P-type transistor embodiments (i.e., for embodiments where the transistor is a PMOS transistor or a P-type TFET), the channel material may advantageously be a Group IV material having a high hole mobility, such as, but not limited to, Ge or a Ge-rich SiGe alloy. For some example embodiments, the channel material may have a Ge content between 0.6 and 0.9, and advantageously may be at least 0.7. In some embodiments having the highest mobility, the channel material may be an intrinsic III-V (or IV for P-type devices) material and is not intentionally doped with any electrically active impurities. In alternative embodiments, one or more nominal impurity dopant levels may be present within the channel material, for example to further set the threshold voltage (Vt), or to provide a HALO pocket implant, etc. However, even for impurity doped embodiments, the impurity dopant level within the channel portion is relatively low, for example, less than 10 15 cm -3 , and advantageously less than 10 13 cm -3 These materials may be amorphous or polycrystalline, for example having a grain size between 0.5 nm and 100 nm.

[0062] In some embodiments, the channel material may include a high-mobility oxide semiconductor material such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, indium gallium zinc oxide (IGZO), gallium oxide, titanium oxynitride, ruthenium oxide, aluminum zinc oxide, or tungsten oxide. Typically, for a thin film transistor (TFT), the channel material may include one or more of tin oxide, cobalt oxide, copper oxide, antimony oxide, ruthenium oxide, tungsten oxide, zinc oxide, gallium oxide, titanium oxide, indium oxide, titanium oxynitride, indium tin oxide, indium zinc oxide, nickel oxide, niobium oxide, copper peroxide, IGZO, indium telluride, molybdenite, molybdenum diselenide, tungsten diselenide, tungsten disulfide, molybdenum disulfide, N-type or P-type amorphous silicon or polycrystalline silicon, single crystal silicon, germanium, indium arsenide, indium gallium arsenide, indium selenide, indium antimonide, zinc antimonide, antimony selenide, silicon germanium, gallium nitride, aluminum gallium nitride, indium phosphite, black phosphorus, zinc sulfide, indium sulfide, and gallium sulfide, each of which may be doped with one or more of gallium, indium, aluminum, fluorine, boron, phosphorus, arsenic, nitrogen, tantalum, tungsten, and magnesium, etc. In some embodiments, thin film channel materials may be deposited at relatively low temperatures, which allows the channel materials to be deposited within the thermal budget imposed on back-end fabrication to avoid damaging other components, for example, front-end components such as logic devices.

[0063] As described above, the channel material may include IGZO. IGZO-based devices have several desirable electrical and manufacturing characteristics. IGZO has a high electron mobility compared to other semiconductors, for example, in the range of 20-50 times that of amorphous silicon. In addition, amorphous IGZO (a-IGZO) transistors are generally characterized by high bandgap, low temperature process compatibility, and low manufacturing cost relative to other semiconductors.

[0064] IGZO can be deposited as a uniform amorphous phase while maintaining a higher carrier mobility than oxide semiconductors such as zinc oxide. Different formulations of IGZO include different proportions of indium oxide, gallium oxide, and zinc oxide. One specific form of IGZO has the chemical formula InGaO 3 (ZnO) 5 Another example form of IGZO has an indium:gallium:zinc ratio of 1:2:1. In various other examples, the IGZO may have a gallium to indium ratio of 1:1, a gallium to indium ratio greater than 1 (e.g., 2:1, 3:1, 4:1, 5:1, 6:1, 7:1, 8:1, 9:1, or 10:1), and / or a gallium to indium ratio less than 1 (e.g., 1:2, 1:3, 1:4, 1:5, 1:6, 1:7, 1:8, 1:9, or 1:10). The IGZO may also include a tertiary dopant, such as aluminum or nitrogen.

[0065] The source region and drain region in the transistor are connected to the channel region. Both the source region and the drain region may include a semiconductor material with a dopant. In some embodiments, the source region and the drain region have the same semiconductor material, which may be the same as the channel material of the channel region. The semiconductor material of the source region or the drain region may be a compound of a IV group material, a compound of a IV group material, a III / V group material, a compound of a III / V group material, a II / VI group material, a compound of a II / VI group material, or other semiconductor material. Example II group materials include zinc (Zn), cadmium (Cd), etc. Example III group materials include aluminum (Al), boron (B), indium (In), gallium (Ga), etc. Example IV group materials include silicon (Si), germanium (Ge), carbon (C), etc. Example V group materials include nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), etc. Example VI group materials include sulfur (S), selenium (Se), tellurium (Te), oxygen (O), etc. The compound of IV group materials may be a binary compound, such as SiC, SiGe, etc. The compounds of the III / V group materials may be binary, ternary or quaternary compounds, such as GaN, InN, etc. The compounds of the II / VI group materials may be binary, ternary or quaternary compounds, such as CdSe, CdS, CdTe, ZnO, ZnSe, ZnS, ZnTe, CdZnTe and CZT, HgCdTe and HgZnTe, etc.

[0066] In some embodiments, the dopants in the source region and the drain region are of the same type. In other embodiments, the dopants in the source region and the drain region may be of different (e.g., opposite) types. In an example, the source region has an N-type dopant and the drain region has a P-type dopant. In another example, the source region has a P-type dopant and the drain region has an N-type dopant. Example N-type dopants include Te, S, As, tin (Sn), Si, Ga, Se, S, In, Al, Cd, chlorine (Cl), iodine (I), fluorine (F), etc. Example P-type dopants include beryllium (Be), Zn, magnesium (Mg), Sn, P, Te, lithium (Li), sodium (Na), Ga, Cd, etc.

[0067] In some embodiments, the source region and the drain region may be highly doped, for example, with a dopant concentration of about 1·10 21 cm -3 , so as to advantageously form ohmic contacts with corresponding S / D contacts (sometimes also interchangeably referred to as "S / D electrodes"), however these regions may also have lower dopant concentrations and, in some embodiments, may form Schottky contacts. Regardless of the exact doping levels, the source and drain regions may be regions with higher dopant concentrations than other regions, e.g., higher than the dopant concentration in the channel region, and, therefore, may be referred to as "highly doped" (HD) regions.

[0068] The channel region may include one or more semiconductor materials having a doping concentration that is significantly less than the doping concentration of the source and drain regions. For example, in some embodiments, the channel material of the channel region may be an intrinsic (e.g., undoped) semiconductor material or alloy that is not intentionally doped with any electrically active impurities. In alternative embodiments, a nominal impurity dopant level may be present in the channel material, such as to set a threshold voltage Vt, or to provide a HALO pocket implant, etc. However, in such an impurity doped embodiment, the impurity dopant level in the channel material is still significantly lower than the dopant level in the source and drain regions, such as less than 10 15 cm -3 or less than 10 13 cm -3 Depending on the context, the term “S / D terminal” may refer to an S / D region or an S / D contact or electrode of a transistor.

[0069] The gate electrode 450 includes one or more conductive materials, such as metal, polysilicon, other types of conductive materials, or some combination thereof. In some embodiments, the selection of the conductive material in the gate electrode 450 (e.g., gate electrode 450A) may depend on whether the transistor is a P-type transistor or an N-type transistor. For a P-type transistor, the gate electrode materials that may be used in different parts of the gate electrode may include, but are not limited to, Ru, palladium, platinum, Co, nickel, and conductive metal oxides (e.g., ruthenium oxide). For an N-type transistor, the gate electrode materials that may be used in different parts of the gate electrode may include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide).

[0070] In some embodiments, gate electrode 450 may include a stack of multiple gate electrode materials, wherein zero or more materials of the stack are work function materials, and at least one material of the stack is a fill metal layer. For other purposes, additional materials / layers may be included adjacent to the gate electrode, such as used as a diffusion barrier layer and / or an adhesion layer. In some embodiments, gate electrode 450B or 450C may be a dummy gate electrode. Gate electrode 450B or 450C may not be coupled to any power plane, ground plane, or signal plane.

[0071] Each electrode 460 may be on a source region or a drain region of a transistor in the cell 400. The electrode 460 on the source region may be referred to as a source electrode. The electrode 460 on the drain region may be referred to as a drain electrode. The electrode 460 may include one or more conductive materials. The conductive material may be a metal. Examples of metals in the electrode 460 may include, but are not limited to, Ru, Cu, Co, palladium, platinum, nickel, etc. Figure 4 In the embodiment of the present invention, electrode 460A is separated from electrode 460B by electrical insulator 420. During operation of cell 400, electrode 460A and electrode 460B can be at different electrical potentials. Electrode 460C can constitute a trench electrode for two transistors, and the source or drain regions of the two transistors can be subjected to the same electrical potential. In other embodiments, cell 400 can include a single electrode in place of electrodes 460A and 460B. In addition, cell 400 can include two separate electrodes in place of electrode 460C. Even in Figure 4 Not shown in the figure, the gate electrode 450 or the electrode 460 may also be separated from the electrical insulator 420 by a dielectric material. In some embodiments, the gate electrode 450 or the electrode 460 may be partially or fully encapsulated by the dielectric material.

[0072] The electrical insulator 420 may separate and insulate semiconductor components or conductive components in the cell 400. In some embodiments, the electrical insulator 420 may completely or partially surround one or more other components of the cell 400. For example, the electrical insulator 420 may completely or partially surround the via 430 or 440, the semiconductor structure 410, the gate electrode 450, the electrode 460, etc. The electrical insulator 420 may include one or more electrically insulating materials, such as dielectric materials, hysteresis materials, etc. Example dielectric materials include oxides (e.g., silicon-based oxides, metal oxides, etc.), high-k dielectrics, etc. Example hysteresis materials include ferroelectric materials, antiferroelectric materials, etc.

[0073] Vias 430 and 440 are conductive. Each of vias 430 and 440 may include one or more electrical conductors, such as metal, etc. In some embodiments, each of vias 430 and 440 may have a longitudinal axis parallel to the Z axis. In some embodiments, the dimension of each of vias 430 and 440 along its longitudinal axis may be greater than the dimension of the via in a direction perpendicular to the longitudinal axis (e.g., in a direction along the X axis or the Y axis). Each of vias 430 and 440 may have a transverse cross-section, which may be a cross-section in a plane perpendicular to its longitudinal axis (e.g., an XY plane).

[0074] like Figure 4 As shown, via 430 is connected to gate electrode 450A, and vias 440 are connected to electrode 460. In some embodiments, via 430 can be an input pin of unit 400 and can support unit 400 to receive signals from one or more other devices. Via 440 can be an output pin of unit 400 and can support unit 400 to send signals to one or more other devices. Via 430 can couple gate electrode 450A to another structure, for example, a metal track of a metal layer (e.g., M0) arranged above unit 400 in a direction along the Z axis. Each via 440 can couple a corresponding electrode 460 to another structure, for example, a metal track of a metal layer (e.g., M0) arranged above unit 400 in a direction along the Z axis.

[0075] In some embodiments, via 440A may have one end connected to electrode 460A and another end connected to metal track 470A. Via 440B may have one end connected to electrode 460B and another end connected to metal track 470B. Metal track 470 may also be referred to as a metal line, a metal interconnect, or a metal structure. In some embodiments, metal tracks 470 have longitudinal axes that are parallel or substantially parallel to each other. Metal track 470 may help deliver power to cell 400. In some embodiments, metal tracks 470 may be separated from each other by one or more electrical insulators. Metal tracks 470 may be a power plane and a ground plane, respectively, which may deliver power to cell 400. In some embodiments, the metal layer including metal track 470 may be M0 in the BEOL portion. Cell 400 may include one or more other metal layers stacked on the metal layer in the direction along the Z axis.

[0076] Figure 5A and 5B Another exemplary cell 500 according to some embodiments of the present disclosure is shown. Cell 500 may be a functional cell, such as a memory cell. In some embodiments, cell 500 is a static random access memory (SRAM) cell. Figure 5A A circuit diagram of unit 500 is shown. Figure 5B A top-down plan view of an example implementation of unit 500 is provided.

[0077] Cell 500 includes transistors M1-M4 for storing a bit value or memory state (e.g., a logical "1" or "0") of the cell, and two access transistors M5 and M6 for controlling access to the cell (e.g., access to write information to the cell or access to read information from the cell 500). Cell 500 is a 6-transistor (6T) memory cell. In other embodiments, cell 500 may include a different number of transistors. Each of transistors M1-M6 may have any transistor architecture, such as planar or non-planar (e.g., FinFET, nanoribbon / nanowire, etc.).

[0078] In the cell 500, each bit can be stored on four transistors (M1, M2, M3, M4), which form two cross-coupled inverters 520, each having an input 522 and an output 524. The first inverter 520-1 can be formed by an NMOS transistor M1 and a PMOS transistor M2, and the second inverter 520-2 can be formed by an NMOS transistor M3 and a PMOS transistor M4. The gate stack 512-1 of the transistor M1 can be coupled to the gate stack 512-2 of the transistor M2. Both gate stacks can be coupled to the input 522-1 of the first inverter 520-1. The first S / D region 514-1 of the transistor M1 can be coupled to the first S / D region 514-2 of the transistor M2. Both first S / D regions 514-1 and 514-2 can be coupled to the output 524-1 of the first inverter 520-1.

[0079] For the second inverter 520-2, the gate stack 512-3 of the transistor M3 can be coupled to the gate stack 512-4 of the transistor M4, and both gate stacks can be coupled to the input terminal 522-2 of the second inverter 520-2. The first S / D region 514-3 of the transistor M3 can be coupled to the first S / D region 514-4 of the transistor M4, and both first S / D regions 514-3 and 514-4 can be coupled to the output terminal 524-2 of the second inverter 520-2. When the transistors M1 and M3 are NMOS transistors and when the transistors M2 and M4 are PMOS transistors, the second S / D regions 516-1 and 516-3 of the transistors M1 and M3 can be coupled to the ground voltage 532, and the second S / D regions 516-2 and 516-4 of the transistors M2 and M4 can be coupled to the power supply voltage 534, such as VDD. In embodiments of cell 500 where NMOS transistors are replaced with PMOS transistors, and vice versa, the designations of ground voltage 532 and supply voltage 534 would also be reversed, all of which are within the scope of the present disclosure.

[0080] The four transistors M1-M4 in this configuration form a stable storage cell for storing a bit value of 0 or 1. Two additional access transistors M5 and M6 can be used to control access to the storage cells of transistors M1-M4 during read and write operations. The first S / D region 514-5 of the access transistor M5 can be coupled to the output terminal 524-1 of the first inverter 520-1. In other words, the first S / D region 514-5 of the access transistor M5 can be coupled to each of the first S / D region 514-1 of the transistor M1 and the first S / D region 514-2 of the transistor M2. The second S / D region 516-5 of the access transistor M5 can be coupled to the first bit line 540-1. Therefore, each of the first S / D region 514-1 of the transistor M1 and the first S / D region 514-2 of the transistor M2 can be coupled to the first bit line 540-1 (e.g., via the access transistor M5). Gate 512 - 5 of access transistor M5 may be coupled to word line 550 .

[0081] The first S / D region 514-6 of the access transistor M6 can be coupled to the output terminal 524-2 of the second inverter 520-2. In other words, the first S / D region 514-6 of the access transistor M6 can be coupled to each of the first S / D region 514-3 of the transistor M3 and the first S / D region 514-4 of the transistor M4. The second S / D region 516-6 of the access transistor M6 can be coupled to the second bit line 540-2. Therefore, each of the first S / D region 514-3 of the transistor M3 and the first S / D region 514-4 of the transistor M4 can be coupled to the second bit line 540-2 (e.g., via the access transistor M6). The gate 512-6 of the access transistor M6 can be coupled to the word line 550. Therefore, the gates 512-5 and 512-6 of both the access transistors M5 and M6 can be coupled to a single shared word line, namely the word line 550.

[0082] An input terminal 522-1 of the first inverter 520-1 may be coupled to the first S / D region 514-6 of the access transistor M6, and an input terminal 522-2 of the second inverter 520 may be coupled to the first S / D region 514-5 of the access transistor M5. In other words, each of the gate stack 512-1 of the transistor M1 and the gate stack 512-2 of the transistor M2 may be coupled to the first S / D region 514-6 of the access transistor M6, and each of the gate stack 512-3 of the transistor M3 and the gate stack 512-4 of the transistor M4 may be coupled to the first S / D region 514-5 of the access transistor M5. In other words, each of the gate stack 512-1 of transistor M1 and the gate stack 512-2 of transistor M2 can be coupled to the second bit line 540-2 (e.g., via access transistor M6), and each of the gate stack 512-3 of transistor M3 and the gate stack 512-4 of transistor M4 can be coupled to the first bit line 540-1 (e.g., via access transistor M5).

[0083] The word line 550 and the first and second bit lines 540 can be used together to read and program (i.e., write) the cell 500. In particular, access to the cell can be enabled by controlling the word line 550 of the two access transistors M5 and M6, which in turn control whether the cell 500 should be connected to the bit lines 540-1 and 540-2. During operation of the cell 500, the signal on the first bit line 540-1 can be complementary to the signal on the second bit line 540-2. The two bit lines 540 can be used to transmit data for read and write operations. In other embodiments of the cell 500, only a single bit line 540 can be used instead of two bit lines 540-1 and 540-2, however having a signal bit line and an opposite bit line (such as two bit lines 540) can help improve the noise margin.

[0084] During read access, bit line 540 can be actively driven high and low by inverter 520 in cell 500. The symmetrical structure of cell 500 also allows differential signaling, which can provide improvements in detecting small voltage swings. Another difference from DRAM that may help make SRAM faster than DRAM is that commodity chips accept all address bits at once. In contrast, commodity DRAM can multiplex the address into two halves, high bits followed by low bits, on the same package pins to keep its size and cost down.

[0085] Each of the word line 550 and the bit line 540, as well as the intermediate elements coupling these lines to the various terminals described herein, can be formed of any suitable conductive material, which can include alloys or stacks of multiple conductive materials. In some embodiments, such conductive materials can include one or more metals or metal alloys, where the metal is such as ruthenium, palladium, platinum, cobalt, nickel, hafnium, zirconium, titanium, tantalum, and aluminum. In some embodiments, such conductive materials can include one or more conductive alloys, oxides, or carbides of one or more metals.

[0086] Figure 5B Shows how it can be implemented Figure 5A The six transistors M1-M6 shown in FIG. Figure 5A Some components of Figure 5B For example, transistors M1-M6 are marked in Figure 5B is marked, where Figure 5B The approximate boundaries of the individual transistors are shown in FIG. 5 as dashed rectangles. Certain elements, such as certain S / D regions 514 and 516 and gate stack 512, are located within the Figure 5B are not marked in order not to clutter the drawing.

[0087] Transistors M1 and M5 may be provided along a first region of an N-type semiconductor 502, transistors M2 and M4 may each be provided along respective first and second regions of a P-type semiconductor 504, and transistors M4 and M6 may be provided along a second region of the N-type semiconductor 502. Each region of the N-type semiconductor 502 and the P-type semiconductor 504 may be formed in or on a support structure (e.g., a substrate), for example, as a fin or a nanoribbon. The N-type semiconductor 502 is suitable for forming a first type of transistor, such as an NMOS transistor, and the P-type semiconductor 504 is suitable for forming a second type of transistor, such as a PMOS transistor, thereby realizing NMOS transistors M1, M3, M5, and M6 and PMOS transistors M2 and M4.

[0088] The S / D contacts 506, the gate electrodes 508, and the interconnects 510 are formed on the N-type and P-type semiconductors 502 and 504, for example, as layers processed on the N-type and P-type semiconductors 502 and 504. Figure 5B It is not specifically shown in the figure, but the S / D region can be formed under the S / D contact 506, and the gate dielectric can be formed under the gate electrode 508. Figure 4 Describe any materials and processes to form Figure 5B The transistor shown in .

[0089] More specifically, a shared gate stack may be used to implement gate stack 512-1 of transistor M1 coupled to gate stack 512-2 of transistor M2. Figure 5B 522-1 in FIG. 500 represents a node that is an input terminal 522-1 of the first inverter 520-1 of the cell 500. Similarly, a shared gate stack may be used to implement the gate stack 212-3 of the transistor M3 coupled to the gate stack 212-4 of the transistor M4. Figure 5B The node labeled 522 - 2 in the figure represents the node which is the input terminal 522 - 2 of the second inverter 520 - 2 of the unit 500 .

[0090] The first shared S / D contact may be used to implement the first S / D region 514-1 of transistor M1 coupled to the first S / D region 514-2 of transistor M2. Figure 5B 524-1 in FIG. 500, indicating a node that is an output terminal 524-1 of the first inverter 520-1 of the cell 500. Similarly, a second shared S / D contact may be used to implement a first S / D region 514-3 of the transistor M3 coupled to a first S / D region 514-4 of the transistor M4. The first shared S / D contact is at Figure 5B The node labeled 524 - 2 in the figure represents the output terminal 524 - 2 of the second inverter 520 - 2 of the unit 500 .

[0091] The first interconnect 510-1 can then be used to couple the shared gate stack 522-1 of the first inverter 520-1 to the shared S / D contact 524-2 of the second inverter 520-2, thereby coupling the input 522-1 of the first inverter 520-1 to the output 524-2 of the second inverter 520-2. Similarly, the second interconnect 510-2 can then be used to couple the shared gate stack 522-2 of the second inverter 520-2 to the shared interconnect 524-1 of the first inverter 520-1, thereby coupling the input 522-2 of the second inverter 520-2 to the output 524-1 of the first inverter 520-1.

[0092] In a given cell 500, the first S / D region 514-5 of transistor M5 may be shared (e.g., the same) as the first S / D region 514-1 of transistor M1 (because both transistors are implemented in a single region of the N-type semiconductor 502). In addition, the first S / D region 514-3 of transistor M3 may be shared (e.g., the same) as the first S / D region 514-6 of transistor M6 (because both transistors are implemented in a single region of the N-type semiconductor 502).

[0093] The second S / D region 516-1 of transistor M1 and the second S / D region 516-3 of transistor M3 can both be coupled to a ground voltage 532, as shown in FIG. Figure 5B The second S / D region 516 - 2 of transistor M2 and the second S / D region 516 - 4 of transistor M4 may both be coupled to a power supply voltage 534 .

[0094] Fig. 6A and 6B 2002 and a top view of a wafer 2000 and a die 2002 that may include one or more IC devices with duplicate cells and fill cells according to some embodiments of the present disclosure. In some embodiments, the die 2002 may be included in an IC package according to some embodiments of the present disclosure. For example, any die 2002 may be used as Figure 7 Any die 2256 in the IC package 2200 shown. Wafer 2000 can be made of semiconductor material and can include one or more dies 2002 having IC devices formed on a surface of wafer 2000. The IC devices can include one or more replica cells and fill cells. Examples of IC devices can include Figure 1 2002. Each die 2002 may be a repeating component of a semiconductor product including any suitable IC (e.g., an IC having a replicated cell and a filler cell as described herein). After fabrication of the semiconductor product is complete (e.g., after fabrication of metal lines as described herein), the wafer 2000 may undergo a singulation process in which each die 2002 is separated from one another to provide discrete "chips" of the semiconductor product. In particular, a device including replicated cells and filler cells as disclosed herein may take the form of or include components in the form of the wafer 2000 (e.g., unsingulated) or in the form of the die 2002 (e.g., singulated). The die 2002 may include one or more diodes, one or more transistors (e.g., one or more III-N transistors as described herein), and optionally, supporting circuitry for routing electrical signals to the III-N diodes having N-doped wells and capping layers, and the III-N transistors, and any other IC components. In some embodiments, wafer 2000 or die 2002 may implement electrostatic discharge (ESD) protection devices, RF front-end devices, memory devices (e.g., SRAM devices), logic devices (e.g., AND, OR, NAND, or NOR gates), or any other suitable circuit elements. Multiple of these devices may be combined on a single die 2002.

[0095] Figure 7is a side cross-sectional view of an example IC package 2200 that may include one or more IC devices having a replica cell and a filler cell according to some embodiments of the present disclosure. In some embodiments, the IC package 2200 may be a system in package (SiP).

[0096] like Figure 7 As shown, IC package 2200 may include package substrate 2252. Package substrate 2252 may be formed of a dielectric material (e.g., ceramic, glass, a combination of organic and inorganic materials, a built-up film, an epoxy film with filler particles therein, etc., and may have embedded portions with different materials), and may have a conductive path extending through the dielectric material between face 2272 and face 2274, or between different locations on face 2272, and / or between different locations on face 2274.

[0097] The packaging substrate 2252 may include conductive contacts 2263 coupled to conductive paths 2264 passing through the packaging substrate 2252, thereby allowing the circuit system within the die 2256 and / or the insert 2257 to be electrically coupled to individual conductive contacts in the conductive contacts 2264 (or other devices included in the packaging substrate 2252, not shown).

[0098] The IC package 2200 may include an interposer 2257 coupled to a package substrate 2252 via conductive contacts 2261 of the interposer 2257 , first level interconnects 2265 , and conductive contacts 2263 of the package substrate 2252 . Figure 7 The first level interconnects 2265 shown in FIG. 22 are solder bumps, but any suitable first level interconnects 2265 may be used. In some embodiments, interposer 2257 may not be included in IC package 2200; instead, die 2256 may be coupled directly to conductive contacts 2263 at face 2272 via first level interconnects 2265.

[0099] IC package 2200 may include one or more dies 2256 coupled to interposer 2257 via conductive contacts 2254 of die 2256, first level interconnects 2258, and conductive contacts 2260 of interposer 2257. Conductive contacts 2260 may be coupled to conductive paths (not shown) through interposer 2257, thereby allowing circuitry within die 2256 to be electrically coupled to individual ones of conductive contacts 2261 (or to other devices included in interposer 2257, not shown). Figure 7The first level interconnect 2258 shown in the figure is a solder bump, but any suitable first level interconnect 2258 can be used. As used herein, a "conductive contact" can refer to a portion of an electrical material (e.g., a metal) that serves as an interface between different components; a conductive contact can be recessed in the surface of a component, flush with the surface of a component, or extend away from the surface of a component, and can take any suitable form (e.g., a conductive pad or a socket).

[0100] In some embodiments, an underfill material 2266 may be disposed between the package substrate 2252 and the interposer 2257 around the first level interconnect 2265, and a mold compound 2268 may be disposed around the die 2256 and the interposer 2257 and in contact with the package substrate 2252. In some embodiments, the underfill material 2266 may be the same as the mold compound 2268. An example material that may be used for the underfill material 2266 and the mold compound 2268 is an epoxy molding material, as appropriate. The second level interconnect 2270 may be coupled to the conductive contact 2264. Figure 7 The second level interconnects 2270 shown in FIG. 2 are solder balls (e.g., for a ball grid array arrangement), but any suitable second level interconnects 2270 may be used (e.g., pins in a pin grid array arrangement or pads in a land grid array arrangement). The second level interconnects 2270 may be used to couple the IC package 2200 to another component, such as a circuit board (e.g., a motherboard), an interposer, or another IC package, as is known in the art and as described below with reference to Figure 8 discussed.

[0101] The die 2256 may take the form of any embodiment of the die 2002 discussed herein, and may include any embodiment of an IC device having a replica cell and a filler cell. In embodiments where the IC package 2200 includes a plurality of die 2256, the IC package 2200 may be referred to as a multi-chip package. Importantly, even in such embodiments of an MCP implementation of the IC package 2200, one or more IC devices having a replica cell and a filler cell may be provided in a single chip according to any embodiment described herein. The die 2256 may include circuitry for performing any desired function. For example, one or more of the die 2256 may be an ESD protection die, one or more of the die 2256 may be a logic die (e.g., a silicon-based die), one or more of the die 2256 may be a memory die (e.g., a high bandwidth memory), and the like. In some embodiments, any of the die 2256 may include one or more backside metal layers. In some embodiments, at least some of the die 2256 may not include any III-N diodes having an N-doped well and a capping layer.

[0102] Figure 7The IC package 2200 shown in FIG. 2 may be a flip chip package, however other package architectures may also be used. For example, the IC package 2200 may be a ball grid array (BGA) package, such as an embedded wafer level ball grid array (eWLB) package. In another example, the IC package 2200 may be a wafer level chip scale package (WLCSP) or a panel fan-out (FO) package. Although FIG. Figure 7 Two dies 2256 are shown in the IC package 2200, but the IC package 2200 may include any desired number of dies 2256. The IC package 2200 may include additional passive components, such as surface mount resistors, capacitors, and inductors, which may be disposed on the first side 2272 or the second side 2274 of the package substrate 2252, or on either side of the interposer 2257. More generally, the IC package 2200 may include any other active or passive components known in the art.

[0103] Figure 8 is a cross-sectional side view of an IC device assembly 2300 according to some embodiments of the present disclosure, which IC device assembly may include a component having one or more IC devices having replica units and filler units. IC device assembly 2300 includes a plurality of components disposed on a circuit board 2302 (e.g., which may be a motherboard). IC device assembly 2300 includes components disposed on a first side 2340 of circuit board 2302 and an opposing second side 2342 of circuit board 2302; typically, the components may be disposed on one or both of sides 2340 and 2342. In particular, any suitable component of IC device assembly 2300 may include any IC device having replica units and filler units according to any embodiment disclosed herein; for example, any IC package discussed below with reference to IC device assembly 2300 may take the form described above with reference to FIG. Figure 7 Any of the embodiments of IC package 2200 discussed (eg, may include duplicate cells and filler cells in / on die 2256 ) may be used.

[0104] In some embodiments, circuit board 2302 may be a PCB including multiple metal layers separated from each other by layers of dielectric material and interconnected by conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals between components coupled to circuit board 2302 (optionally in conjunction with other metal layers). In other embodiments, circuit board 2302 may be a non-PCB substrate.

[0105] Figure 8The IC device assembly 2300 shown in FIG. 2 includes a package-on-interposer structure 2336 coupled to a first side 2340 of a circuit board 2302 via a coupling component 2316. The coupling component 2316 can electrically and mechanically couple the package-on-interposer structure 2336 to the circuit board 2302 and can include solder balls (e.g., Figure 7 as shown), male and female portions of a socket, adhesive, bottom fill material and / or any other suitable electrical and / or mechanical coupling structure.

[0106] The package-on-interposer structure 2336 may include an IC package 2320 coupled to the interposer 2304 via a coupling component 2318. The coupling component 2318 may take any suitable form for the application, such as the forms discussed above with reference to the coupling component 2316. The IC package 2320 may be or include, for example, a die ( Figure 6B 2002), IC devices (e.g., Figure 1 IC device 100) or any other suitable component. In particular, IC package 2320 may include one or more IC devices having a replica unit and a filler unit as described herein. Figure 8 A single IC package 2320 is shown in the figure, but multiple IC packages can be coupled to the interposer 2304; in fact, additional interposers can be coupled to the interposer 2304. The interposer 2304 can provide an intervening substrate for bridging the circuit board 2302 and the IC package 2320. In general, the interposer 2304 can extend the connection to a loose spacing, or reroute the connection to a different connection. For example, the interposer 2304 can couple the IC package 2320 (e.g., a die) to a BGA for coupling to a coupling component 2316 of the circuit board 2302. Figure 8 In the illustrated embodiment, IC package 2320 and circuit board 2302 are attached to opposite sides of interposer 2304; in other embodiments, IC package 2320 and circuit board 2302 can be attached to the same side of interposer 2304. In some embodiments, three or more components can be interconnected through interposer 2304.

[0107] The insert 2304 may be formed of epoxy, glass fiber reinforced epoxy, ceramic material, or a polymer material such as polyimide. In some embodiments, the insert 2304 may be formed of an alternative rigid or flexible material, which may include the same materials as those used for the semiconductor substrate described above, such as silicon, germanium, and other III-V and IV materials. The insert 2304 may include metal interconnects 2308 and vias 2310, including but not limited to TSV 2306. The insert 2304 may also include embedded devices 2314, including both passive and active devices. Such devices may include but are not limited to capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, ESD protection devices, and memory devices. More complex devices, such as other RF devices, power amplifiers, power management devices, antennas, arrays, sensors, and micro-electromechanical systems (MEMS) devices, may also be formed on the insert 2304. In some embodiments, IC devices with duplicate cells and filler cells as described herein may also be implemented in / on the insert 2304. The package-on-interposer structure 2336 may take the form of any of the package-on-interposer structures known in the art.

[0108] IC device assembly 2300 may include an IC package 2324 coupled to first side 2340 of circuit board 2302 via coupling component 2322. Coupling component 2322 may take the form of any of the embodiments discussed above with reference to coupling component 2316, and IC package 2324 may take the form of any of the embodiments discussed above with reference to IC package 2320.

[0109] Figure 8 The illustrated IC device assembly 2300 includes a package-on-package structure 2334 coupled to the second side 2342 of the circuit board 2302 via a coupling component 2328. The package-on-package structure 2334 may include an IC package 2326 and an IC package 2332 coupled together via the coupling component such that the IC package 2326 is disposed between the circuit board 2302 and the IC package 2332. The coupling components 2328 and 2330 may take the form of any embodiment of the coupling component 2316 described above, and the IC packages 2326 and 2332 may take the form of any embodiment of the IC package 2320 described above. The package-on-package structure 2334 may be configured according to any package-on-package structure known in the art.

[0110] Fig. 92400, which may include one or more components having one or more IC devices having a replication unit and a padding unit. For example, according to some embodiments of the present disclosure, any suitable component among the components of the computing device 2400 may include a die including a replication unit and a padding unit (e.g., Figure 6B Any component of computing device 2400 may include an IC device (e.g., Figure 1 IC device 100) and / or IC package (e.g., Figure 7 Any component of computing device 2400 may include an IC device component (e.g., Figure 8 IC device component 2300).

[0111] Fig. 9 2400, but any one or more of these components may be omitted or duplicated, depending on the application. In some embodiments, some or all of the components included in the computing device 2400 may be attached to one or more motherboards. In some embodiments, some or all of these components are manufactured onto a single SoC (system on chip) die.

[0112] In addition, in various embodiments, the computing device 2400 may not include Fig. 9 , but computing device 2400 may include interface circuitry for coupling to one or more components. For example, computing device 2400 may not include display device 2406, but may include display device interface circuitry (e.g., connector and driver circuitry), to which display device 2406 may be coupled. In another set of examples, computing device 2400 may not include audio input device 2418 or audio output device 2408, but may include audio input or output device interface circuitry (e.g., connector and support circuitry), to which audio input device 2418 or audio output device 2408 may be coupled.

[0113] The computing device 2400 may include a processing device 2402 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory to convert the electronic data into other electronic data that can be stored in registers and / or memory. The processing device 2402 may include one or more digital signal processors (DSPs), application specific ICs (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptographic processors (specialized processors that execute cryptographic algorithms in hardware), server processors, or any other suitable processing devices. The computing device 2400 may include a memory 2404, which itself may include one or more memory devices, such as volatile memory (e.g., DRAM), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or a hard drive. In some embodiments, the memory 2404 may include a memory that shares a die with the processing device 2402. The memory may be used as a cache memory and may include, for example, eDRAM and / or spin transfer torque magnetic random access memory (STT-MRAM).

[0114] In some embodiments, computing device 2400 may include a communication chip 2412 (e.g., one or more communication chips). For example, communication chip 2412 may be configured to manage wireless communications for transmitting data to and from computing device 2400. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that can communicate data through a non-solid medium using modulated electromagnetic radiation. The term does not mean that the associated devices do not contain any wires, although in some embodiments they may not contain any wires.

[0115] The communication chip 2412 may implement any of a variety of wireless standards or protocols, including but not limited to Institute of Electrical and Electronics Engineers (IEEE) standards, including Wi-Fi (IEEE 802.11 series), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long Term Evolution (LTE) project, and any amendments, updates, and / or revisions (e.g., Advanced LTE project, Ultra Mobile Broadband (UMB) project (also known as "3GPP2"), etc.). IEEE 802.16-compatible broadband wireless access (BWA) networks are commonly referred to as WiMAX networks, which is an abbreviation standing for Worldwide Interoperability for Microwave Access and is a certification mark for products that have passed conformance and interoperability testing of the IEEE 802.16 standard. The communication chip 2412 may operate in accordance with a Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 2411 may operate according to Enhanced GSM Evolution Data (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 2412 may operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution Data Optimized (EV-DO) and its derivatives, and any other wireless protocols designated as 3G, 4G, 5G and higher. In other embodiments, the communication chip 2412 may operate according to other wireless protocols. The computing device 2400 may include an antenna 2422 to facilitate wireless communications and / or receive other wireless communications (such as AM or FM radio transmissions).

[0116] In some embodiments, the communication chip 2412 can manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., Ethernet). As described above, the communication chip 2412 can include multiple communication chips. For example, the first communication chip 2412 can be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, while the second communication chip 2412 can be dedicated to longer-range wireless communications such as global positioning systems (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, etc. In some embodiments, the first communication chip 2412 can be dedicated to wireless communications, while the second communication chip 2411 can be dedicated to wired communications.

[0117] In various embodiments, the IC devices as described herein can be particularly advantageously used as part of an ESD circuit that protects power amplifiers, low noise amplifiers, filters (including arrays of filters and filter banks), switches, or other active components. In some embodiments, the IC devices as described herein can be used in PMICs, for example, as rectifier diodes for large currents. In some embodiments, the IC devices as described herein can be used in audio devices and / or various input / output devices.

[0118] Computing device 2400 may include battery / power circuitry 2414. Battery / power circuitry 2414 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuitry for coupling components of computing device 2400 to an energy source separate from computing device 2400 (e.g., AC line power).

[0119] Computing device 2400 may include display device 2406 (or corresponding interface circuitry as described above). Display device 2406 may include any visual indicator such as, for example, a heads-up display, a computer monitor, a projector, a touch screen display, a liquid crystal display (LCD), a light emitting diode display, or a flat panel display.

[0120] Computing device 2400 may include audio output device 2408 (or corresponding interface circuitry as described above). Audio output device 2408 may include any device that generates an audible indicator, such as, for example, a speaker, headphones, or earbuds.

[0121] Computing device 2400 may include audio input device 2418 (or corresponding interface circuitry as described above). Audio input device 2418 may include any device that generates a signal representative of sound, such as a microphone, a microphone array, or a digital musical instrument (e.g., a musical instrument with a Musical Instrument Digital Interface (MIDI) output).

[0122] Computing device 2400 may include a GPS device 2416 (or corresponding interface circuitry as described above). GPS device 2416 may communicate with a satellite-based system and may receive the location of computing device 2400, as is known in the art.

[0123] Computing device 2400 may include another output device 2410 (or corresponding interface circuitry as described above). Examples of other output devices 2410 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

[0124] The computing device 2400 may include another input device 2420 (or corresponding interface circuitry as described above). Examples of other input devices 2420 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device (such as a mouse, a stylus, a touchpad), a barcode reader, a quick response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0125] The computing device 2400 may have any desired form factor, such as a handheld or mobile computing device (e.g., a cellular phone, a smart phone, a mobile Internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra-mobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control component, a vehicle control component, a digital camera, a digital video recorder, or a wearable computing device. In some embodiments, the computing device 2400 may be any other electronic device that processes data.

[0126] The following paragraphs provide various examples of the embodiments disclosed herein.

[0127] Example 1 provides an IC device, comprising: a first functional region including a first semiconductor device, the first semiconductor device having a first logic or storage function; a second functional region including a second semiconductor device, the second semiconductor device having a second logic or storage function; a replica region, the replica region including one or more first semiconductor devices of the first functional region; and a non-functional region, wherein the replica region and the non-functional region are between the first functional region and the second functional region, and the first functional region is closer to the replica region than to the non-functional region.

[0128] Example 2 provides the IC device of Example 1, wherein the first semiconductor device is in a standard cell.

[0129] Example 3 provides the IC device of Example 2, wherein a height of the replicated region is the same as or substantially similar to a height of a standard cell.

[0130] Example 4 provides the IC device of Example 3, wherein the standard cell includes conductive structures stacked in a first direction, and the height of the standard cell is a dimension of the standard cell in a second direction perpendicular to the first direction.

[0131] Example 5 provides an IC device according to any one of Examples 1-4, wherein: the replica area is a first replica area, the IC device also includes a second replica area, the second replica area includes one or more second semiconductor devices of the second functional area, and the second functional area is closer to the second replica area than to the non-functional area.

[0132] Example 6 provides the IC device of Example 5, wherein the non-functional area is between the first copy area and the second copy area.

[0133] Example 7 provides an IC device according to any one of Examples 1-6, further comprising: a third functional region including a third semiconductor device, the third semiconductor device having a third logic or storage function; and an additional replica region, the additional replica region including one or more second semiconductor devices of the second functional region and one or more third semiconductor devices of the third functional region, wherein the additional replica region is between the second functional region and the third functional region.

[0134] Example 8 provides the IC device of any of Examples 1-7, wherein a height of the replicated region is no greater than approximately 2 microns.

[0135] Example 9 provides the IC device of any of Examples 1-8, wherein the replication area is adjacent to the first functional area.

[0136] Example 10 provides a method for forming an IC device, the method comprising: determining a first region between a first functional region and a second functional region, the first functional region comprising a first semiconductor device having a first logic or storage function, the second functional region comprising a second semiconductor device having a second logic or storage function; determining a second region between the first functional region and the second functional region, wherein the first functional region is closer to the first region than to the second region; copying one or more first semiconductor devices of the first functional region to the first region; and providing a filling unit in the second region.

[0137] Example 11 provides a method according to Example 10, wherein copying the one or more first semiconductor devices in the first functional area into the first area includes: identifying the one or more first semiconductor devices, wherein the one or more first semiconductor devices are in a logic unit or a memory unit; and copying the logic unit or the memory unit into the first area.

[0138] Example 12 provides a method according to Example 10 or 11, wherein determining the second area includes: providing a grid above an area including the first functional area and the second functional area, the grid including components in rows and columns; identifying one or more first components in the grid above an edge of the first functional area; identifying one or more second components in the grid above an edge of the second functional area; and selecting one or more third components in the grid by excluding the one or more first components and the one or more second components, wherein the second area is above the one or more third components.

[0139] Example 13 provides a method according to Example 12, wherein determining the first area includes: after determining the second area, identifying an area between the first functional area and the second area as the first area.

[0140] Example 14 provides a method according to any one of Examples 10-13, further comprising: determining a division boundary between the second functional region and a third functional region, the third functional region comprising a third semiconductor device having a third logic or storage function; copying one or more second semiconductor devices of the second functional region to an area between the second functional region and the division boundary; and copying one or more third semiconductor devices of the third functional region to an area between the third functional region and the division boundary.

[0141] Example 15 provides a method according to any one of Examples 10-14, further comprising: determining a third region between a first functional region and a second functional region, wherein the second functional region is closer to the third region than to the second region; and copying one or more second semiconductor devices of the second functional region into the third region.

[0142] Example 16 provides a method according to any one of Examples 10-15, wherein determining the first area includes: determining a height of a standard cell in the first functional area; and determining a height of the first area based on the height of the standard cell, wherein the height of the first area is the same as or substantially similar to the height of the standard cell.

[0143] Example 17 provides an IC device, comprising: a first block including a first functional unit; a second block including a second functional unit; a third block including one or more replicas of the first functional units in the first block; and a fourth block including a fill unit, wherein the first functional unit or the second functional unit is a logic unit or a memory unit, the third block is between the first block and the fourth block, and the fourth block is between the second block and the third block.

[0144] Example 18 provides an IC device according to Example 17, further including: a fifth block including a fifth functional unit, wherein the functional unit is a logic unit or a memory unit; a sixth block, the sixth block including one or more copies of the fifth functional unit in the fifth block; and a seventh block, the seventh block including one or more copies of the second functional unit in the second block, wherein the sixth block and the seventh block are between the second block and the fifth block, the one or more second functional units are at the edge of the second block, and the one or more fifth functional units in the fifth functional unit are at the edge of the fifth block.

[0145] Example 19 provides an IC device according to Example 17 or 18, further including: a fifth block, the fifth block including a replica of one or more second functional units in the second block, wherein the fifth block is between the second block and the fourth block, and the one or more second functional units are at the edge of the second block.

[0146] Example 20 provides the IC device of any of Examples 17-19, wherein a height of the third block is the same as or substantially similar to a height of the first functional unit.

[0147] Example 21 provides an IC package, comprising: an IC device according to any of Examples 1-20; and another IC component coupled to the IC device.

[0148] Example 22 provides the IC package of Example 21, wherein the another IC component includes one of a package substrate, an interposer, or another IC die.

[0149] Example 23 provides an IC package according to Example 21 or 22, wherein the IC device may include at least one of a memory device, a computing device, a wearable device, a handheld electronic device, and a wireless communication device, or is a part thereof.

[0150] Example 24 provides an electronic device, comprising: a carrier substrate; and an IC package according to any of Examples 21-23 coupled to the carrier substrate.

[0151] Example 25 provides the electronic device of Example 24, wherein the carrier substrate is a motherboard.

[0152] Example 26 provides the electronic device of Example 24, wherein the carrier substrate is a PCB.

[0153] Example 27 provides an electronic device according to any one of Examples 24-26, wherein the electronic device is a wearable electronic device or a handheld electronic device.

[0154] Example 28 provides an electronic device according to any one of Examples 24-27, wherein the electronic device further includes one or more communication chips and an antenna.

[0155] Example 29 provides the electronic device of any of Examples 24-28, wherein the electronic device is an RF transceiver.

[0156] Example 30 provides an electronic device according to any of Examples 24-28, wherein the electronic device is one of a switch, a power amplifier, a low noise amplifier, a filter, a filter bank, a duplexer, an upconverter or a downconverter of an RF communication device such as an RF transceiver.

[0157] Example 31 provides an electronic device according to any of Examples 24-30, wherein the electronic device is a computing device.

[0158] Example 32 provides an electronic device according to any of Examples 24-31, wherein the electronic device is included in a base station of a wireless communication system.

[0159] Example 33 provides an electronic device according to any of Examples 24-31, wherein the electronic device is included in a user equipment device of a wireless communication system.

[0160] The above description of the embodiments shown in the present disclosure, including the contents described in the abstract, is not intended to be exhaustive or limit the present disclosure to the precise form disclosed. Although specific embodiments and examples of the present disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the present disclosure as will be appreciated by those skilled in the relevant art. These modifications may be made to the present disclosure in accordance with the above detailed description.

Claims

1. An integrated circuit (IC) device comprising: A first functional region comprising a first semiconductor device, the first semiconductor device having a first logic or storage function; comprising a second functional region of a second semiconductor device, the second semiconductor device having a second logic or storage function; a replication region, the replication region including one or more first semiconductor devices of the first functional region; as well as A non-functional area, wherein the duplicate area and the non-functional area are between the first functional area and the second functional area, and the first functional area is closer to the duplicate area than to the non-functional area.

2. The IC device according to claim 1, wherein: The first semiconductor device is in a standard cell.

3. The IC device according to claim 2, wherein: The height of the replication region is the same as or substantially similar to the height of the standard cell.

4. The IC device according to claim 3, wherein: The standard cell includes a conductive structure stacked in a first direction, and the height of the standard cell is a dimension of the standard cell in a second direction perpendicular to the first direction.

5. The IC device according to any one of claims 1 to 4, wherein: The duplicate region is a first duplicate region, the IC device further includes a second duplicate region, the second duplicate region includes one or more second semiconductor devices of the second functional region, and the second functional region is closer to the second duplicate region than to the non-functional region.

6. The IC device according to claim 5, wherein: The non-functional area is between the first replication area and the second replication area.

7. The IC device according to any one of claims 1 to 4, further comprising: A third functional region including a third semiconductor device, the third semiconductor device having a third logic or storage function; as well as an additional replication region including one or more second semiconductor devices of the second functional region and one or more third semiconductor devices of the third functional region, wherein the additional replication region is between the second functional region and the third functional region.

8. The IC device according to any one of claims 1 to 4, wherein: The height of the replicated area is no greater than approximately 2 microns.

9. The IC device according to any one of claims 1 to 4, wherein: The copy area is adjacent to the first functional area.

10. A method of forming an integrated circuit (IC) device, the method comprising: determining a first region between a first functional region including a first semiconductor device having a first logic or storage function and a second functional region including a second semiconductor device having a second logic or storage function; determining a second region between the first functional region and the second functional region, wherein the first functional region is closer to the first region than to the second region; replicating one or more first semiconductor devices in the first functional region into the first region; and A filling unit is provided in the second region.

11. The method according to claim 10, wherein: Copying the one or more first semiconductor devices of the first functional area to the first area includes: identifying the one or more first semiconductor devices, wherein the one or more first semiconductor devices are in a logic unit or a memory unit; and The logic unit or memory unit is copied into the first area.

12. The method according to claim 10 or 11, wherein: Determining the second area includes: providing a grid over the area including the first functional area and the second functional area, the grid including components in rows and columns; and One or more components in the grid are selected, wherein the second region is above the one or more components.

13. The method according to claim 12, wherein: Selecting the one or more components includes: identifying one or more first components in the grid that are above an edge of the first functional area; and One or more components in the grid are selected by excluding the one or more first components.

14. The method according to claim 13, wherein: Selecting the one or more components further comprises: identifying one or more second components in the grid that are above an edge of the second functional area; and One or more components in the grid are selected by also excluding the one or more second components.

15. The method according to claim 12, wherein: Determining the first area includes: After determining the second area, an area between the first functional area and the second area is identified as the first area.

16. The method according to claim 10 or 11, further comprising: determining a dividing boundary between the second functional region and a third functional region, the third functional region including a third semiconductor device having a third logic or storage function; as well as One or more second semiconductor devices of the second functional region are copied to a region between the second functional region and the partition boundary.

17. The method according to claim 16, further comprising: The one or more third semiconductor devices of the third functional region are copied into a region between the third functional region and the partition boundary.

18. The method according to claim 10 or 11, further comprising: determining a third area between the first functional area and the second functional area, wherein the second functional area is closer to the third area than to the second area; and One or more second semiconductor devices in the second functional region are copied into the third region.

19. The method according to claim 10 or 11, wherein: Determining the first area includes: determining the height of the standard cells in the first functional area; and A height of the first region is determined based on the height of the standard cell.

20. The method according to claim 19, wherein: The height of the first region is the same as or substantially similar to the height of the standard cell.

21. An integrated circuit (IC) device comprising: A first block comprising a first functional unit; a second block comprising a second functional unit; a third block including a replica of one or more first functional units in the first block; and A fourth block includes a filling unit, wherein the first functional unit or the second functional unit is a logic unit or a memory unit, the third block is between the first block and the fourth block, and the fourth block is between the second block and the third block.

22. The IC device of claim 21, further comprising: a fifth block comprising a fifth functional unit, wherein the functional unit is a logic unit or a memory unit; a sixth block, the sixth block comprising a replica of one or more of the fifth functional units in the fifth block; and A seventh block includes a replica of one or more second functional units in the second block.

23. The IC device according to claim 22, wherein: The sixth block and the seventh block are between the second block and the fifth block, the one or more second functional units are at an edge of the second block, and the one or more fifth functional units of the fifth functional units are at an edge of the fifth block.

24. The IC device according to any one of claims 21 to 23, further comprising: A fifth block includes a replica of one or more second functional units in the second block, wherein the fifth block is between the second block and the fourth block, and the one or more second functional units are at an edge of the second block.

25. The IC device according to any one of claims 21 to 23, wherein: The height of the third block is the same as or substantially similar to the height of the first functional unit.

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