High-voltage regulation and control latch-up static electricity and surge resisting integrated protection circuit

Abstract

The invention discloses a high-voltage regulation and control anti-latch-up static electricity and surge integrated protection circuit which comprises a multi-structure transistor auxiliary trigger circuit and a double-SCR trigger bleeder circuit, wherein the multi-structure transistor auxiliary trigger circuit is composed of a resistor Rn1, a resistor Rn2, a resistor Rp, a Zener tube ZD, a transistor T1, a transistor T2, a transistor T3, a transistor T4, a transistor T5 and a transistor T6. The high-integration electrostatic surge integrated bleeder circuit which is adjustable in trigger voltage, resistant to latch-up and high in robustness is formed; the electrostatic surge protection design window is adjusted by adjusting key characteristic parameters and chip areas in different trigger and discharge circuits, so that the requirements of different working voltages and surge discharge of a high-voltage switch or a driving chip are met, the influence of electrostatic surge pulses on the performance of the high-voltage switch or the driving chip is avoided, and the service life of the high-voltage switch or the driving chip is prolonged. Therefore, the problems of performance degradation, circuit failure and the like of multi-type high-voltage switches or driving chips of different technologies, different power domains and different application scenes caused by instant pulses and electric surges are solved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and in particular to a high-voltage regulation anti-latch static electricity and surge integrated protection circuit. Background Art

[0002] Electrostatic discharge (ESD) is a charge transfer phenomenon caused by a potential difference between two objects that are in contact or close to each other, which can generate extremely large instantaneous current and voltage in a very short time. Surge is a type of electrical over stress (EOS), which is usually an instantaneous overvoltage exceeding the normal operating voltage caused by lightning strikes and the start and stop of electronic equipment. When the surge voltage or current exceeds the maximum withstand voltage of the chip port, the chip will fail due to ESD or EOS. Due to the differences in the intensity, time and cycle of ESD and EOS stress, the mechanisms of ESD and ESD that cause circuit failure are quite different, and the protection methods are quite different. Although ESD and EOS failure phenomena are often manifested as internal short circuits, open circuits, and deterioration or even damage of performance parameters of the chip, the ESD / EOS protection measures and methods are different.

[0003] Traditional ESD protection units mostly use structures such as diodes, triodes, and MOS tubes, and EOS protection devices mostly use large-area single-structure multi-finger stacked transient suppressor tubes. They all have problems such as high trigger voltage, easy latching, large voltage hysteresis after opening, large parasitic capacitance, large chip area, large leakage level, and weak ESD robustness per unit area. The Silicon Controlled Rectifier (SCR) structure has attracted widespread attention in the industry due to its advantages such as strong ESD robustness per unit area, strong current discharge capacity, and good process compatibility. However, the trigger voltage of the SCR structure is too high, and it is easy to produce latching effects, making it difficult to control the current amplification factor of the transistor inside the circuit and the degree of internal positive feedback. Summary of the invention

[0004] In order to solve the above technical problems, the present invention provides a high-voltage regulation anti-latch electrostatic and surge integrated protection circuit, including a multi-structure transistor auxiliary trigger circuit and a dual SCR trigger leakage circuit; the high-voltage regulation anti-latch electrostatic surge integrated protection circuit is composed of a P-type substrate, a high-voltage N-well, a high-voltage P-well, a first N-well, a first P-well, a second N-well, a second P-well, a P-type doped region, a first N+ injection region, a first P+ injection region, a second N+ injection region, a second P+ injection region, a third N+ injection region, a third P+ injection region, a polysilicon gate, a fourth P+ injection region, a fourth N+ injection region and a fifth P+ injection region; The multi-structure transistor auxiliary trigger circuit is composed of transistor T2, Zener transistor ZD and transistor T6; the dual SCR trigger leakage circuit is composed of transistor T1, transistor T4, transistor T3 and transistor T5; The resistor Rn1 is a parasitic resistor composed of the first N+ injection region and the first N well; the resistor Rp is a parasitic resistor composed of the high-voltage P well, the second P well and the fifth P+ injection region; the resistor Rn2 is a parasitic resistor composed of the second N well and the second N+ injection region; the transistor T1 is composed of the first P+ injection region, the first N well, the high-voltage N well and the high-voltage P well; the transistor T2 is composed of the first P+ injection region, the first N well, the high-voltage N well, the high-voltage P well, the first P well and the second P+ injection region; the transistor T3 is composed of the third P+ injection region, the second N well and the second P well; the transistor T4 is composed of the high-voltage N well, the high-voltage P well and the fourth N+ injection region; the transistor T5 is composed of the second N well, the second P well and the fourth N+ injection region; the transistor T6 is composed of the third P+ injection region, the polysilicon gate and the fourth P+ injection region; The emitter of transistor T1, one end of resistor Rn1, the emitter of transistor T2, the cathode of Zener ZD, one end of resistor Rn2, the emitter of transistor T3, the source of transistor T6 and the gate of transistor T6 are all connected to the anode of the high-voltage regulation anti-latching electrostatic surge integrated protection circuit; the base of transistor T1 and the other end of resistor Rn1 are all connected to the base of transistor T2; the collector of transistor T1, the base of transistor T4, one end of resistor Rp and the collector of transistor T3 are all connected to the base of transistor T5; the base of transistor T3 and the collector of transistor T5 are all connected to the substrate electrode of transistor T6; the drain of transistor T6, the emitter of transistor T5, the other end of resistor Rp, the anode of Zener ZD and the collector of transistor T2 are all connected to the cathode of the high-voltage regulation anti-latching electrostatic and surge integrated protection circuit.

[0005] The technical solution further defined in the present invention is: Furthermore, by adjusting the length of the polysilicon gate, the voltage withstand capability of the high voltage control anti-latch static and surge integrated protection circuit can be adjusted. As described above, a high-voltage regulated anti-latch electrostatic and surge integrated protection circuit adjusts the voltage withstand capability of the high-voltage regulated anti-latch electrostatic and surge integrated protection circuit by adjusting the distance between the third P+ injection region and the polysilicon gate.

[0006] As described above, a high-voltage regulated anti-latching electrostatic and surge integrated protection circuit forms a Zener diode ZD between the second N+ injection region and the P-type doped layer, a first reverse biased junction is formed between the second N well and the second P well, and a second reverse biased junction is formed between the high-voltage N well and the high-voltage P well; when static electricity or surge voltage electrical stress acts between the anode and cathode of the high-voltage regulated anti-latching electrostatic surge integrated protection circuit, as the static electricity and surge electrical stress increase, the Zener diode ZD, the first reverse biased junction, the transistor T6 and the second reverse biased junction are sequentially turned on in an orderly manner, thereby achieving timely response to multiple types of transient pulses that meet different electrical stress intensities, rising edges and stress cycles.

[0007] As described above, in a high-voltage regulated anti-latch electrostatic and surge integrated protection circuit, transistor T2 forms a first drift current P1, a second drift current P2 is formed between the high-voltage N-well and the high-voltage P-well, and Zener transistor ZD forms a third drift current P3; when the static electricity or surge electrical stress is not sufficient to trigger the opening of the static electricity and surge integrated protection circuit, the first drift current P1, the second drift current P2 and the third drift current P3 will all promote the voltage on the resistor Rp to continue to increase, thereby assisting in triggering the transistor T4 and the transistor T5 to turn on.

[0008] As described above, a high-voltage regulated anti-latch electrostatic and surge integrated protection circuit is formed by transistor T1 and transistor T4 to form a leakage path P4, and transistor T3 and transistor T5 to form a leakage path P5; by adjusting the resistance values ​​of resistor Rn1, resistor Rp and resistor Rn2, the conduction speed of leakage path P4 and leakage path P5 can be regulated. Since the breakdown voltage of the first reverse biased junction is lower than that of the second reverse biased junction, leakage path P5 is opened earlier than leakage path P6.

[0009] The beneficial effects of the present invention are: (1) In the present invention, by adjusting the length of the polysilicon gate, or adjusting the distance between the third P+ injection region and the polysilicon gate, the voltage withstand capability of the high-voltage control anti-latch electrostatic and surge integrated protection circuit can be adjusted to meet the electrostatic withstand capability of high-voltage driver chips with different operating voltages and different process steps; (2) In the present invention, when static electricity or surge voltage electrical stress acts between the anode and cathode of the high-voltage regulation anti-latch electrostatic surge integrated protection circuit, as the static electricity and surge electrical stress increase, the Zener diode ZD, the first reverse bias junction, the transistor T6 and the second reverse bias junction are sequentially turned on in an orderly manner, achieving timely response to multiple types of transient pulses that meet different electrical stress intensities, rising edges and stress cycles, thereby enhancing the reliability of the protected circuit system; (3) In the present invention, when the electrostatic or surge electrical stress is small and insufficient to trigger the electrostatic and surge integrated protection circuit to start, the first drift current P1, the second drift current P2, and the third drift current P3 will all promote the voltage on the resistor Rp to increase continuously, thereby assisting in triggering the transistor T4 and the transistor T5 to start, thereby enhancing the response speed of the high-voltage control anti-latch electrostatic and surge integrated protection circuit and improving the system stability; (4) In the present invention, by adjusting the resistance values ​​of resistor Rn1, resistor Rp and resistor Rn2, the rapid conduction of leakage path P4 and leakage path P5 can be controlled. Since the breakdown voltage of the first reverse-biased junction is lower than that of the second reverse-biased junction, leakage path P5 is turned on earlier than leakage path P6, thereby realizing orderly triggering, high integration and integrated protection functions of electrostatic and surge protection. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 It is a schematic diagram of the overall structure of the present invention; Figure 2 It is an equivalent circuit diagram of high voltage regulation anti-latch static electricity and surge integrated protection in an embodiment of the present invention; Figure 3 Schematic diagram of a multi-structure transistor auxiliary trigger circuit in an embodiment of the present invention; Figure 4 Schematic diagram of a dual SCR triggering leakage circuit in an embodiment of the present invention.

[0011] Among them: 100, P-type substrate; 101, high-voltage N-well; 102, high-voltage P-well; 103, first N-well; 104, first P-well; 105, second N-well; 106, second P-well; 107, P-type doped region; 108, first N+ injection region; 109, first P+ injection region; 110, second N+ injection region; 111, second P+ injection region; 112, third N+ injection region; 113, third P+ injection region; 114, polysilicon gate; 115, fourth P+ injection region; 116, fourth N+ injection region; 117, fifth P+ injection region. DETAILED DESCRIPTION

[0012] This embodiment provides a high voltage regulation anti-latch static and surge integrated protection circuit, such as Figure 1 As shown, it is composed of a P-type substrate 100, a high-voltage N-well 101, a high-voltage P-well 102, a first N-well 103, a first P-well 104, a second N-well 105, a second P-well 106, a P-type doped region 107, a first N+ injection region 108, a first P+ injection region 109, a second N+ injection region 110, a second P+ injection region 111, a third N+ injection region 112, a third P+ injection region 113, a polysilicon gate 114, a fourth P+ injection region 115, a fourth N+ injection region 116 and a fifth P+ injection region 117.

[0013] like Figure 2 As shown, the high-voltage regulation anti-latch electrostatic and surge integrated protection circuit includes a multi-structure transistor auxiliary trigger circuit and a dual SCR trigger leakage circuit. The multi-structure transistor auxiliary trigger circuit is composed of a transistor T2, a Zener transistor ZD and a transistor T6; the dual SCR trigger leakage circuit is composed of a transistor T1, a transistor T4, a transistor T3 and a transistor T5.

[0014] The resistor Rn1 is a parasitic resistor formed by the first N+ injection region 108 and the first N well 103; the resistor Rp is a parasitic resistor formed by the high-voltage P well 102, the second P well 106 and the fifth P+ injection region 117; the resistor Rn2 is a parasitic resistor formed by the second N well 105 and the second N+ injection region 110; the transistor T1 is composed of the first P+ injection region 109, the first N well 103, the high-voltage N well 101 and the high-voltage P well 102; the transistor T2 is composed of the first P+ injection region 109, the first N well 103, the high-voltage N well 101 and the high-voltage P well 102. 101, a high-voltage P-well 102, a first P-well 104 and a second P+ injection region 111; a transistor T3 is composed of a third P+ injection region 113, a second N-well 105 and a second P-well 106; a transistor T4 is composed of a high-voltage N-well 101, a high-voltage P-well 102 and a fourth N+ injection region 116; a transistor T5 is composed of a second N-well 105, a second P-well 106 and a fourth N+ injection region 116; a transistor T6 is composed of a third P+ injection region 113, a polysilicon gate 114 and a fourth P+ injection region 115.

[0015] The emitter of transistor T1, one end of resistor Rn1, the emitter of transistor T2, the cathode of Zener ZD, one end of resistor Rn2, the emitter of transistor T3, the source of transistor T6 and the gate of transistor T6 are all connected to the anode of the high-voltage regulation anti-latching electrostatic surge integrated protection circuit; the base of transistor T1 and the other end of resistor Rn1 are all connected to the base of transistor T2; the collector of transistor T1, the base of transistor T4, one end of resistor Rp and the collector of transistor T3 are all connected to the base of transistor T5; the base of transistor T3 and the collector of transistor T5 are all connected to the substrate electrode of transistor T6; the drain of transistor T6, the emitter of transistor T5, the other end of resistor Rp, the anode of Zener ZD and the collector of transistor T2 are all connected to the cathode of the high-voltage regulation anti-latching electrostatic and surge integrated protection circuit.

[0016] By adjusting the length of the polysilicon gate 114, or adjusting the distance between the third P+ injection region 113 and the polysilicon gate 114, the voltage withstand capability of the high-voltage anti-latch electrostatic and surge integrated protection circuit can be regulated to meet the electrostatic withstand capability of high-voltage driving chips with different operating voltages and different process technologies.

[0017] like Figure 3 As shown, a Zener diode ZD is formed between the second N+ injection region 110 and the P-type doped layer 107, a first reverse bias junction is formed between the second N well 105 and the second P well 106, and a second reverse bias junction is formed between the high-voltage N well 101 and the high-voltage P well 102; when static electricity or surge voltage electrical stress acts between the anode and cathode of the high-voltage regulation anti-latch electrostatic surge integrated protection circuit, as the static electricity and surge electrical stress increase, the Zener diode ZD, the first reverse bias junction, the transistor T6 and the second reverse bias junction are sequentially turned on in an orderly manner, so as to achieve timely response to multiple types of transient pulses that meet different electrical stress intensities, rising edges and stress cycles, thereby enhancing the reliability of the protected circuit system.

[0018] like Figure 4 As shown, transistor T2 forms a first drift current P1, a second drift current P2 is formed between the high-voltage N-well 101 and the high-voltage P-well 102, and the Zener transistor ZD forms a third drift current P3; when the static electricity or surge electrical stress is small and insufficient to trigger the start of the static electricity and surge integrated protection circuit, the first drift current P1, the second drift current P2 and the third drift current P3 will all promote the voltage on the resistor Rp to increase continuously, thereby assisting in triggering the transistor T4 and the transistor T5 to turn on, enhancing the response speed of the high-voltage regulation anti-latch static electricity and surge integrated protection circuit, and improving the system stability.

[0019] The leakage path P4 is formed by the transistor T1 and the transistor T4, and the leakage path P5 is formed by the transistor T3 and the transistor T5; by adjusting the resistance values ​​of the resistor Rn1, the resistor Rp and the resistor Rn2, the conduction speed of the leakage path P4 and the leakage path P5 can be controlled. Since the breakdown voltage of the first reverse-biased junction is lower than that of the second reverse-biased junction, the leakage path P5 is turned on earlier than the leakage path P6, thereby realizing orderly triggering, high integration and integrated protection functions of electrostatic and surge protection.

[0020] This embodiment utilizes a multi-structure transistor auxiliary trigger circuit and a dual SCR trigger discharge circuit, and realizes integrated electrostatic and surge protection with strong discharge capability, adjustable high voltage, and controllable voltage hysteresis amplitude by regulating the characteristic parameters of different transistors and their structures. It can enhance the electrostatic and surge protection level of the chip and its application system, enhance the stability and reliability of the circuit system, and solve the problems of high trigger voltage, easy latching, large voltage hysteresis amplitude after turning on, large parasitic capacitance, large chip area, large leakage level, and weak ESD robustness per unit area in traditional discrete ESD and EOS protection circuits.

[0021] In addition to the above embodiments, the present invention may also have other implementation modes. Any technical solution formed by equivalent replacement or equivalent transformation falls within the protection scope required by the present invention.

Claims

1. A high voltage regulation anti-latch static and surge integrated protection circuit, characterized in that: It comprises a multi-structure transistor auxiliary trigger circuit and a dual SCR trigger leakage circuit; the high-voltage regulation anti-latch electrostatic surge integrated protection circuit is composed of a P-type substrate (100), a high-voltage N well (101), a high-voltage P well (102), a first N well (103), a first P well (104), a second N well (105), a second P well (106), a P-type doped region (107), a first N+ injection region (108), a first P+ injection region (109), a second N+ injection region (110), a second P+ injection region (111), a third N+ injection region (112), a third P+ injection region (113), a polysilicon gate (114), a fourth P+ injection region (115), a fourth N+ injection region (116) and a fifth P+ injection region (117); The multi-structure transistor auxiliary trigger circuit is composed of transistor T2, Zener transistor ZD and transistor T6; the dual SCR trigger leakage circuit is composed of transistor T1, transistor T4, transistor T3 and transistor T5; The resistor Rn1 is a parasitic resistor formed by the first N+ injection region (108) and the first N well (103); the resistor Rp is a parasitic resistor formed by the high-voltage P well (102), the second P well (106) and the fifth P+ injection region (117); and the resistor Rn2 is a parasitic resistor formed by the second N well (105) and the second N+ injection region (110); The transistor T1 is composed of a first P+ injection region (109), a first N well (103), a high-voltage N well (101), and a high-voltage P well (102); the transistor T2 is composed of a first P+ injection region (109), a first N well (103), a high-voltage N well (101), a high-voltage P well (102), a first P well (104), and a second P+ injection region (111); The transistor T3 is composed of a third P+ injection region (113), a second N-well (105) and a second P-well (106); the transistor T4 is composed of a high-voltage N-well (101), a high-voltage P-well (102) and a fourth N+ injection region (116); the transistor T5 is composed of a second N-well (105), a second P-well (106) and a fourth N+ injection region (116); the transistor T6 is composed of a third P+ injection region (113), a polysilicon gate (114) and a fourth P+ injection region (115); The emitter of transistor T1, one end of resistor Rn1, the emitter of transistor T2, the cathode of Zener tube ZD, one end of resistor Rn2, the emitter of transistor T3, the source of transistor T6 and the gate of transistor T6 are all connected to the anode of the high-voltage regulation anti-latch electrostatic surge integrated protection circuit; the base of transistor T1 and the other end of resistor Rn1 are all connected to the base of transistor T2; The collector of transistor T1, the base of transistor T4, one end of resistor Rp and the collector of transistor T3 are all connected to the base of transistor T5; the base of transistor T3 and the collector of transistor T5 are all connected to the substrate electrode of transistor T6; the drain of transistor T6, the emitter of transistor T5, the other end of resistor Rp, the anode of Zener transistor ZD and the collector of transistor T2 are all connected to the cathode of the high-voltage regulation anti-latch electrostatic and surge integrated protection circuit.

2. A high voltage control anti-latch static electricity and surge integrated protection circuit according to claim 1, characterized in that: By adjusting the length of the polysilicon gate (114), the voltage withstand capability of the high-voltage control anti-latch static electricity and surge integrated protection circuit can be regulated.

3. The high voltage regulation anti-latch static electricity and surge integrated protection circuit according to claim 1, characterized in that: By adjusting the distance between the third P+ injection region (113) and the polysilicon gate (114), the voltage withstand capability of the high-voltage control anti-latch static electricity and surge integrated protection circuit is regulated.

4. The high voltage regulation anti-latch static electricity and surge integrated protection circuit according to claim 1, characterized in that: A Zener diode ZD is formed between the second N+ injection region (110) and the P-type doped layer (107), a first reverse bias junction is formed between the second N well (105) and the second P well (106), and a second reverse bias junction is formed between the high-voltage N well (101) and the high-voltage P well (102); when static electricity or surge voltage electrical stress acts between the anode and cathode of the high-voltage regulation anti-latch static electricity surge integrated protection circuit, as the static electricity and surge electrical stress increase, the Zener diode ZD, the first reverse bias junction, the transistor T6 and the second reverse bias junction are sequentially turned on in an orderly manner, thereby achieving timely response to multiple types of transient pulses that meet different electrical stress intensities, rising edges and stress cycles.

5. The high voltage regulation anti-latch static electricity and surge integrated protection circuit according to claim 1, characterized in that: The transistor T2 forms a first drift current P1, a second drift current P2 is formed between the high-voltage N-well (101) and the high-voltage P-well (102), and the Zener transistor ZD forms a third drift current P3; when the static electricity or surge electrical stress is insufficient to trigger the start of the static electricity and surge integrated protection circuit, the first drift current P1, the second drift current P2 and the third drift current P3 will all promote the voltage on the resistor Rp to continuously increase, thereby assisting in triggering the transistor T4 and the transistor T5 to turn on.

6. The high voltage regulation anti-latch static electricity and surge integrated protection circuit according to claim 4, characterized in that: The transistor T1 and the transistor T4 form a leakage path P4, and the transistor T3 and the transistor T5 form a leakage path P5; by adjusting the resistance values ​​of the resistor Rn1, the resistor Rp and the resistor Rn2, the conduction speed of the leakage path P4 and the leakage path P5 can be controlled. Since the breakdown voltage of the first reverse biased junction is lower than that of the second reverse biased junction, the leakage path P5 is opened earlier than the leakage path P6.

Images