Preparation method of solar cell

Abstract

The invention discloses a preparation method of a solar cell, and the preparation method comprises the following steps: providing a silicon substrate which comprises a first surface and a second surface which are oppositely arranged, and the second surface comprises a first region and a second region; preparing a tunneling layer, a second doping layer and a mask which are stacked in sequence on the second surface; removing the mask on the second region by adopting a laser film opening process; removing the second doping layer on the second region by adopting a chemical etching process, and reserving the tunneling layer and the second doping layer on the first region; and preparing a second electrode in contact with the second doped layer on the first region. According to the invention, the mask is prepared on the back surface of the silicon substrate, the laser is adopted to carry out patterned film opening, and then the polycrystalline silicon layer in the back non-metal region is removed by chemical etching, so that the short-circuit current of the cell can be improved, and the conversion efficiency and the double-sided rate of the cell are further improved.

Description

Technical Field

[0001] The invention belongs to the technical field of solar cells, and in particular relates to a method for preparing a solar cell. Background Art

[0002] With the rapid development of the photovoltaic industry, the performance and efficiency requirements of solar cells in the domestic and foreign photovoltaic markets are also constantly increasing, and industry manufacturers have focused on the research and development of high-efficiency batteries. TOPCon (Tunnel Oxide Passivated Contact) cells can improve the surface passivation performance of the cell, reduce the metal contact composite current, and effectively increase the open circuit voltage and short circuit current of the cell by sequentially preparing an ultra-thin tunnel oxide layer and a doped polysilicon layer on the back of the silicon substrate. In recent years, the market share of TOPCon cells has risen rapidly, and has gradually surpassed PERC cells to become the mainstream technology for solar cells.

[0003] Both the n+ polarity and the p+ polarity in TOPCon cells have excellent passivation and conductivity properties, and are compatible with traditional industrial production, and have broad development prospects. With the continuous optimization of TOPCon cells, the parasitic absorption of the back polysilicon layer (poly) has become the primary factor limiting the improvement of TOPCon cell efficiency and bifaciality.

[0004] In TOPCon cells, the back polysilicon layer is doped with phosphorus to form a doped polysilicon layer (N+Poly), which has three main functions: 1. Provide field passivation effect; 2. As a phosphorus-rich layer, it greatly improves the contact on the back; 3. Isolates the direct contact between the Ag metal and the silicon substrate, reducing metal recombination. In addition to the above advantages, the parasitic absorption of the polysilicon layer is its biggest disadvantage. Parasitic absorption refers to an optical absorption mechanism that does not generate electron-hole pairs in the silicon body, thereby reducing the utilization rate of light. In order to reduce the recombination of the Ag metal area on the back, the thickness of the polysilicon layer is generally greater than 100nm. Reducing the thickness of the polysilicon layer while ensuring that the passivation of the metal area is not lost has become the main optimization direction of TOPCon cells.

[0005] Therefore, in view of the above technical problems, it is necessary to provide a method for preparing a solar cell. Summary of the invention

[0006] The object of the present invention is to provide a method for preparing a solar cell to improve the conversion efficiency and bifaciality of the cell.

[0007] In order to achieve the above purpose, the technical solution provided by an embodiment of the present invention is as follows:

[0008] A method for preparing a solar cell, the method comprising the following steps:

[0009] Providing a silicon substrate, the silicon substrate comprising a first surface and a second surface arranged opposite to each other, the second surface comprising a first region and a second region;

[0010] Prepare a tunneling layer, a second doping layer and a mask layer stacked in sequence on the second surface;

[0011] Using a laser film opening process to remove the mask on the second area;

[0012] Using a chemical etching process, the second doping layer on the second region is removed, and the tunneling layer and the second doping layer on the first region are retained;

[0013] A second electrode contacting the second doping layer is prepared on the first region.

[0014] In one embodiment, the mask is a silicon oxide mask with a thickness of 2nm to 50nm or 15nm to 20nm.

[0015] In one embodiment, the laser power in the laser film opening process is 45W-55W, the scanning speed is 40000mm / s-60000mm / s, and the laser frequency is 500KHz-600KHz.

[0016] In one embodiment, the first region includes a plurality of first sub-regions that are distributed in parallel and at equal intervals, the second electrode includes a plurality of gate lines that are distributed in parallel, and the width of the first sub-region is greater than or equal to the width of the gate line.

[0017] In one embodiment, the width of the first sub-region is 50 μm to 150 μm, and the width of the gate line is 15 μm to 100 μm.

[0018] In one embodiment, the chemical etching process includes:

[0019] The second doping layer on the second region is removed by using an alkaline solution, wherein the mass fraction of the alkaline solution is 3% to 15% and the treatment time is 100s to 500s;

[0020] The tunneling layer on the second area and the mask on the first area are removed by using an acid solution, the mass fraction of the acid solution is 5% to 20%, and the processing time is 100s to 500s.

[0021] In one embodiment, before removing the second doped layer on the second region, the method further includes: removing the mask formed around the edge of the silicon substrate by using an acid solution, wherein the mass fraction of the acid solution is 5% to 30% and the processing time is 30s to 100s; and / or,

[0022] After removing the tunneling layer on the second area and the mask on the first area, the method further includes: performing RCA cleaning on the silicon substrate.

[0023] In one embodiment, preparing a tunneling layer, a second doping layer, and a mask stacked in sequence on the second surface includes:

[0024] Depositing a tunneling layer, a doped amorphous silicon layer and a mask in sequence on the second surface of the silicon substrate;

[0025] The silicon substrate on which the tunneling layer, the doped amorphous silicon layer and the mask are deposited is annealed at a temperature of 880° C. to 980° C. to transform the doped amorphous silicon layer into a doped polysilicon layer.

[0026] In one embodiment, the preparation method further comprises:

[0027] The light trapping structure is prepared on the first surface and the second surface of the silicon substrate by a texturing process; and / or the second surface of the silicon substrate is polished before the tunneling layer, the second doping layer and the mask are prepared.

[0028] In one embodiment, the preparation method further comprises:

[0029] forming a first doping layer at the first surface, the first doping layer having a doping type opposite to that of the second doping layer; and,

[0030] A first electrode is prepared on the first surface and in contact with the first doping layer.

[0031] In one embodiment, the preparation method further comprises:

[0032] Prepare a first passivation layer and / or a first anti-reflection layer on the first surface of the silicon substrate;

[0033] A second passivation layer and / or a second anti-reflection layer is prepared on the second surface of the silicon substrate.

[0034] In one embodiment, the first anti-reflection layer and / or the second anti-reflection layer is a stacked film formed by any one or more of a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer, and has a thickness of 60 nm to 130 nm; and / or,

[0035] The first passivation layer and / or the second passivation layer is an aluminum oxide passivation layer. The thickness of the first passivation layer is 2nm to 7nm or 3nm to 6nm, and the thickness of the second passivation layer is 3nm to 5nm.

[0036] In one embodiment, the tunneling layer is a silicon oxide layer, a silicon oxynitride layer, or a combination of both, with a thickness of 1 nm to 3 nm; and / or,

[0037] The first doped layer is formed by a diffusion process or deposited by a PECVD process. The first doped layer is a P-type doped layer with a surface doping concentration of 3E18 cm -3 ~3E19cm -3 and / or,

[0038] The second doped layer is an N-type doped polysilicon layer with a surface doping concentration of 1E20cm -3 ~1E21cm -3 , thickness is 1nm~120nm or 80nm~100nm;

[0039] The silicon substrate is an N-type silicon substrate.

[0040] Compared with the prior art, the present invention has the following beneficial effects:

[0041] The present invention prepares a mask on the back of a silicon substrate and uses a laser to pattern the film, and then uses chemical etching to remove the polysilicon layer in the non-metallic area on the back, thereby improving the short-circuit current of the battery and further improving the conversion efficiency and bifaciality of the battery. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0043] Figure 1 is a schematic structural diagram of a solar cell in Example 1 of the present invention;

[0044] Figure 2 for Figure 1 Schematic diagram of the local structure at A in the middle;

[0045] Figure 3 is a schematic plan view of the second surface of the silicon substrate in Example 1 of the present invention;

[0046] Figure 4 is a plan view schematically showing the second surface and the second electrode in Example 1 of the present invention;

[0047] Figures 5a to 5j is a process flow chart of preparing a solar cell in Example 1 of the present invention;

[0048] Figure 6 Schematic diagram of laser pattern in the laser film opening process in Example 1 of the present invention;

[0049] Figure 7 is a surface morphology image of the second region on the silicon substrate after the chemical etching process in Example 1 of the present invention;

[0050] Figures 8a to 8c This is a process flow chart for preparing a first doping layer on the first surface of a silicon substrate in Example 2 of the present invention.

[0051] Description of main reference numerals:

[0052] 10-substrate, 11-first doped layer, 11'-boron-doped amorphous silicon layer, 21-first passivation layer, 31-first anti-reflection layer, 12-tunneling layer, 13-second doped layer, 22-second passivation layer, 32-second anti-reflection layer, 41-first electrode, 42-second electrode, 421-secondary gate line, 50-mask, S1-first surface, S2-second surface, S21-first region, S22-second region, 101-first sub-region, 102-second sub-region. DETAILED DESCRIPTION

[0053] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0054] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0055] The present invention discloses a method for preparing a solar cell, comprising the following steps:

[0056] Providing a silicon substrate, the silicon substrate comprising a first surface and a second surface arranged opposite to each other, the second surface comprising a first region and a second region;

[0057] Prepare a tunneling layer, a second doping layer and a mask layer stacked in sequence on the second surface;

[0058] Using a laser film opening process to remove the mask on the second area;

[0059] Using a chemical etching process, the second doping layer on the second region is removed, and the tunneling layer and the second doping layer on the first region are retained;

[0060] A second electrode contacting the second doping layer is prepared on the first region.

[0061] Furthermore, the preparation method also includes:

[0062] forming a first doping layer at the first surface, the first doping layer having a doping type opposite to that of the second doping layer; and,

[0063] A first electrode is prepared on the first surface and in contact with the first doping layer.

[0064] The present invention prepares a mask on the back of a silicon substrate and uses a laser to pattern the film, and then uses chemical etching to remove the polysilicon layer in the non-metallic area on the back, thereby improving the short-circuit current of the battery and further improving the conversion efficiency and bifaciality of the battery.

[0065] The present invention is further described below in conjunction with specific embodiments.

[0066] Embodiment 1:

[0067] Ginseng Figure 1 The solar cell in this embodiment is a schematic diagram of the structure of the solar cell, which is a TOPCon cell, including a silicon substrate 10, Figure 5a As shown, the silicon substrate 10 includes a first surface S1 and a second surface S2 that are relatively arranged, and the second surface S2 includes a first area S21 and a second area S22. The first surface S1 is the front side (i.e., the light-receiving side) of the silicon substrate 10, and the second surface S2 is the back side (i.e., the backlight side) of the silicon substrate 10. The first area S21 is a back metal area, and the second area S22 is a back non-metal area.

[0068] The silicon substrate 10 in this embodiment is an N-type silicon substrate, and the resistivity is 0.3 Ω·cm to 7 Ω·cm, preferably 0.5 Ω·cm to 3.5 Ω·cm.

[0069] Furthermore, a light trapping structure is formed on the first surface S1 of the silicon substrate 10. For example, a pyramid velvet structure can be formed on the first surface S1 of the silicon substrate 10 by alkali texturing, and the size of the pyramid is 0.5μm to 3μm. The second surface S2 of the silicon substrate 10 is a polished surface, which can be the surface of the light trapping structure after chemical polishing, or the surface of the back of the original silicon substrate after direct chemical polishing. For example, in this embodiment, a pyramid velvet structure can be formed on the second surface S2 of the silicon substrate 10 by alkali texturing, and the size of the pyramid is 0.5μm to 3μm, and then the back is alkali polished to obtain a polished surface. Compared with the back of a conventional silicon substrate, a plurality of tower bases will be formed on the polished surface (the tower base is the base left after the pyramid velvet structure is polished).

[0070] In this embodiment, a first doping layer 11 is formed on the first surface S1 of the silicon substrate 10 by a diffusion process, thereby forming a PN junction, and generating minority carrier-hole pairs after light exposure. For example, the first doping layer 11 is a P-type doping layer (i.e., a P+ emitter) formed by a boron doping process, and the surface doping concentration is 3E18cm -3 ~3E19cm -3 , square resistance is 250Ω / sq~300Ω / sq, preferably 250Ω / sq~280Ω / sq.

[0071] Combination Figure 2 As shown, in this embodiment, a tunneling layer 12 and a second doping layer 13 are sequentially stacked on the first area S21 on the second surface S2 of the silicon substrate 10. The tunneling layer 12 can provide a good interface passivation effect, and the second doping layer 13 can provide a field passivation effect. At the same time, because the doping concentration of this layer is relatively high, the contact can be improved and the resistance can be reduced.

[0072] The tunneling layer 12 is a silicon oxide layer, a silicon oxynitride layer, or a combination of the two, preferably a silicon oxide layer, with a thickness of 1 nm to 3 nm; the second doping layer 13 is a phosphorus-doped N-type doped polysilicon layer, with a surface doping concentration of 1E20 cm -3 ~1E21cm -3 The thickness is 1nm to 120nm, preferably 80nm to 100nm. The thickness of the second doping layer of this embodiment is further reduced, which can reduce parasitic absorption without affecting the metallization contact performance, increase the short-circuit current density of the battery, and significantly improve the battery efficiency and bifaciality.

[0073] Preferably, in this embodiment, a first passivation layer 21 and a first anti-reflection layer 31 are sequentially stacked on the first surface S1 of the silicon substrate 10, and a second passivation layer 22 and a second anti-reflection layer 32 are sequentially stacked on the second surface S2 of the silicon substrate 10. The second passivation layer 22 and the second anti-reflection layer 32 cover the second doping layer 13 and extend into the second region S22. In the second region S22, the second passivation layer 22 is in direct contact with the silicon substrate 10. The first passivation layer 21 can provide excellent field passivation and chemical passivation effects, the second passivation layer 22 can provide a chemical passivation effect, and the first anti-reflection layer 31 can reduce reflectivity and increase light utilization.

[0074] Exemplarily, the first passivation layer 21 is an aluminum oxide passivation layer with a thickness of 2nm to 7nm, preferably 3nm to 6nm, and the second passivation layer 22 is an aluminum oxide passivation layer with a thickness of 3nm to 5nm; the first anti-reflection layer 31 and the second anti-reflection layer 32 can be a stacked film formed by any one or more of a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer, with a thickness of 60nm to 130nm, preferably a silicon nitride layer. Silicon nitride is chemically inactive, has strong acid and alkali corrosion resistance, and can reduce the sensitivity of the battery to the environment.

[0075] In addition, the first electrode 41 in this embodiment is located on the first surface S1 of the silicon substrate 10 and contacts the first doping layer 11, and the second electrode 42 is located on the second surface S2 of the silicon substrate 10, specifically on the first area S21 in the second surface S2, and contacts the second doping layer 13.

[0076] Ginseng Figure 3 As shown, in this embodiment, the first region S21 includes a plurality of first sub-regions 101 that are parallel and equally spaced, and the second region S22 includes a plurality of second sub-regions 102 that are parallel and equally spaced, and the first sub-regions 101 and the second sub-regions 102 are staggered. The width of the first sub-region 101 is smaller than the width of the second sub-region 102, for example, the ratio of the widths of the two can be 1: (5-20), preferably, the first region S21 occupies about 10% of the area of ​​the entire second surface S2.

[0077] Combination Figure 4 As shown, the second electrode 42 is a gate electrode, which at least includes a plurality of parallel auxiliary gate lines 421, and the width of the first sub-region 101 is greater than or equal to the width of the auxiliary gate line 421. Optionally, the second electrode 42 may also include a plurality of main gate lines (not shown) perpendicular to the auxiliary gate lines 421.

[0078] In this embodiment, taking a 210TOPCon battery as an example, the size is 203.396±15mm, there are 230 secondary grid lines 421, the width is 15μm to 100μm, and the spacing between adjacent secondary grid lines is 0.907±0.015mm. The spacing between adjacent first sub-regions 101 is equal to the spacing between adjacent secondary grid lines, and each first sub-region 101 is distributed with a secondary grid line 421, and the width of the first sub-region 101 is greater than the width of the secondary grid line 421, and the width of the first sub-region is 50μm to 150μm, such as the width of the secondary grid line is 40μm, and the width of the first sub-region is 80μm.

[0079] The method for preparing a solar cell in this embodiment specifically includes the following steps:

[0080] 1. Double-sided velveting

[0081] Ginseng Figure 5a As shown, a silicon substrate 10 is provided, and the silicon substrate 10 includes a first surface S1 and a second surface S2 that are arranged opposite to each other. The second surface S2 includes a first area S21 and a second area S22. The first surface S1 is the front side (i.e., the light-receiving side) of the silicon substrate 10, and the second surface S2 is the back side (i.e., the backlight side) of the silicon substrate 10. The first area S21 is a back metal area, and the second area S22 is a back non-metal area.

[0082] The silicon substrate 10 in this embodiment is an N-type silicon substrate with a resistivity of 0.3 Ω·cm to 7 Ω·cm, preferably 0.5 Ω·cm to 3.5 Ω·cm. Figure 5b As shown, the first surface S1 and the second surface S2 of the silicon substrate 10 are formed with a pyramid texture structure (not shown) by an alkali texturing process, and the size of the pyramid is 0.5 μm to 3 μm.

[0083] 2. Boron Diffusion

[0084] Ginseng Figure 5c As shown, a P-type doped first doping layer (i.e., a P+ emitter) 11 is formed at the first surface S1 of the silicon substrate 10 by a boron diffusion process. Specifically, a boron source (e.g., BCl3 or BBr3, etc.) is used in a high-temperature furnace tube for diffusion, and a layer of silicon oxide is formed on the outer layer. After diffusion, the surface doping concentration of the first doping layer is 3E18cm -3 ~3E19cm -3 , the square resistance is 250Ω / sq~300Ω / sq, preferably 250Ω / sq~280Ω / sq. In the boron diffusion process, BSG (not shown) is formed on the second surface S2 of the silicon substrate.

[0085] In this embodiment, the outer silicon layer of the first surface S1 of the silicon substrate 10 is transformed into a boron diffusion layer. Figure 5c The total thickness of the silicon substrate 10 and the first doping layer 11 after the boron diffusion is Figure 5b The thickness of the silicon substrate 10 before the boron diffusion is uniform.

[0086] 3. Back polishing

[0087] Ginseng Figure 5d As shown, the silicon substrate after boron diffusion is first passed through a single-sided chain device, and a hydrofluoric acid solution is used to remove the back silicon oxide. The back side is then alkaline polished to remove the edge junction and back side wrap (BSG), and finally cleaned.

[0088] 4. Preparation of back-side tunneling passivation structure

[0089] Ginseng Figure 5e As shown, a tunneling layer 12, a second doping layer 13 and a mask 50 stacked in sequence are prepared on the second surface S2.

[0090] Illustratively, in this embodiment, a PECVD process is used to first deposit a silicon oxide tunneling layer with a thickness of 1nm to 3nm on the back side, and then deposit a phosphorus-doped amorphous silicon layer or multiple phosphorus-doped amorphous silicon layers with different doping concentrations, with a total thickness of 1nm to 120nm, preferably 80nm to 100nm, and finally deposit a silicon oxide mask layer with a mask thickness of 2nm to 50nm, preferably 15nm to 20nm.

[0091] 5. Annealing activation

[0092] Annealing is performed in a high-temperature annealing furnace at a temperature of 880°C to 980°C, preferably 900°C to 950°C. After annealing, the phosphorus-doped amorphous silicon layer is transformed into a phosphorus-doped polysilicon layer. Phosphorus is activated by annealing to form a tunnel passivation contact structure on the back side.

[0093] 6. Laser film opening

[0094] Ginseng Figure 5f As shown, the laser film opening process is used to remove the mask on the second area S22.

[0095] After annealing, the back structure of the silicon substrate is tunneling layer (SiO2) + doped polysilicon layer (N+poly) + mask (SiO2). The laser processing mainly acts on the mask (SiO2). For the silicon oxide mask with a thickness of 15nm to 20nm, the laser power in the laser film opening process is 45W to 55W, preferably 50W, the scanning speed is 40000mm / s to 60000mm / s, preferably 50000mm / s, and the laser frequency is 500KHz to 600KHz, preferably 500KHz.

[0096] Ginseng Figure 6 The figure shows the laser pattern in the laser film opening process in this embodiment. The black line part corresponds to the metal area, that is, the first area S21, and the blank part is the laser scanning area, that is, the second area S22. Figure 3 As shown, the laser scanning area is the second area S22 (ie, the back non-metal area), and the mask 50 on the second area S22 is removed by a laser film opening process to expose the doped polysilicon layer thereunder.

[0097] It should be understood that the laser pattern in the present invention can be designed according to different electrode structures, so that the mask in the laser scanning area (i.e., the non-metallic area on the back) is removed and the mask in the metal area on the back is retained. The laser patterns for other electrode structures will not be illustrated one by one here.

[0098] 7. De-plating and chemical etching

[0099] Ginseng Figure 5g As shown, this step specifically includes:

[0100] Pickling 1: Use an acid solution in the pickling tank to remove the mask around the edge of the silicon substrate, the mass fraction of the acid solution is 5% to 30%, and the processing time is 30s to 100s, preferably 60s. Exemplarily, in this step, the front side of the silicon substrate is passed through a chain hydrofluoric acid tank to remove the silicon oxide mask around the edge on one side.

[0101] Alkali etching: using an alkaline solution in an alkaline washing tank to remove the second doping layer 13 on the second region S22, the mass fraction of the alkaline solution is 3% to 15%, and the processing time is 100s to 500s, preferably 350s;

[0102] Pickling 2: using an acid solution in an acid pickling tank to remove the tunneling layer 12 on the second area S22 and the mask 50 on the first area S21, the mass fraction of the acid solution is 5% to 20%, and the processing time is 100s to 500s, preferably 300s;

[0103] Finally, RCA cleaning is performed. RCA cleaning is a prior art and will not be described in detail here.

[0104] Preferably, the acid solution in this embodiment is obtained by mixing industrial-grade hydrofluoric acid solution (mass fraction ~40%) and water in a certain proportion, and the alkaline solution is obtained by mixing industrial-grade sodium hydroxide solution (mass fraction ~32%) and water in a certain proportion.

[0105] After the laser film opening process, the mask on the second area S22 has been removed by laser. In the alkaline etching step, the doped polysilicon in the second area S22 will be etched by the alkaline solution. After 350s, the doped polysilicon in the second area S22 has been completely etched. Since the first area S21 is protected by the mask, the doped polysilicon on the first area S21 is not affected.

[0106] During the alkaline etching process, the second doped layer 13 (i.e., the phosphorus-doped polysilicon layer) on the second region S22 is corroded, which can reduce the parasitic absorption on the back side of the battery and significantly improve the current; while the first region S21 has a mask to block the corrosion of the alkaline solution, thereby not affecting the contact performance between the back electrode and the second doped layer.

[0107] 8. Preparation of passivation layer

[0108] Ginseng Figure 5h As shown, the ALD process is used to prepare the first passivation layer 21 and the second passivation layer 22 on the first surface S1 and the second surface S2 of the silicon substrate respectively. The first passivation layer 21 is an aluminum oxide passivation layer with a thickness of 2nm to 7nm, preferably 3nm to 6nm, and the second passivation layer 22 is an aluminum oxide passivation layer with a thickness of 3nm to 5nm.

[0109] After the de-plating and chemical etching steps, the tunneling layer and the doped polysilicon layer on the first area S21 can still ensure the passivation effect, while there is no passivation layer protection on the second area S22. Therefore, while preparing the first passivation layer on the front side, it is necessary to prepare the second passivation layer on the back side at the same time to ensure a good interface passivation effect on the second area S22.

[0110] In addition, under high-temperature sintering conditions to ensure good front contact, the second passivation layer 22 has a certain barrier effect on the back paste, so the second doping layer 13 can be further thinned, thereby improving the short-circuit current density of the battery.

[0111] 9. Preparation of anti-reflection layer

[0112] Ginseng Figure 5i As shown, a first anti-reflection layer 31 and a second anti-reflection layer 32 are respectively prepared on a first surface S1 and a second surface S2 of a silicon substrate by a PECVD process. The first anti-reflection layer 31 and the second anti-reflection layer 32 can be a stacked film formed by any one or more of a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer, with a thickness of 60nm to 130nm.

[0113] 10. Printing metal electrodes

[0114] Ginseng Figure 5j As shown, the first electrode 41 and the second electrode 42 are printed on the front and back sides respectively by screen printing, and then sintering and light injection or electric injection treatment are performed to form ohmic contacts.

[0115] The first electrode 41 and the second electrode 42 are gate line electrodes in the prior art, and usually include a main gate line and a secondary gate line. It is worth noting that since the secondary gate line in the second electrode 42 needs to be printed on the first area S21, the width of the first sub-area 101 needs to be greater than the width of the secondary gate line 421 in the second electrode 42, so that the secondary gate line 421 can be aligned.

[0116] The process flow in this embodiment is texturing → boron diffusion → back polishing → PE-poly → annealing → laser film opening → de-wrap plating → ALD → PECVD → screen printing. TOPCon batteries can be prepared through the above steps, and finally the battery cells are tested, sorted and stored.

[0117] Comparative Example 1:

[0118] The process flow in this comparative example is texturing→boron diffusion→back polishing→PE-poly→annealing→de-coating→ALD→PECVD→screen printing, which is the mass production process flow in the prior art.

[0119] Compared with Example 1, in this comparative example, no mask is deposited in the step of preparing the back tunneling passivation structure, and no laser film opening process is performed. The entire back surface of the silicon substrate has a tunneling passivation contact structure of a tunneling layer + doped polysilicon layer, and the rest is the same as Example 1.

[0120] Comparative Example 2:

[0121] The process flow in this comparative example is texturing → boron diffusion → back polishing → LP-poly + phosphorus diffusion → annealing → laser → de-coating → ALD → PECVD → screen printing.

[0122] Compared with Example 1, in this comparative example, laser is used to remove PSG (phosphosilicate glass), polysilicon (poly) and SiO2 tunneling layer generated after LP-poly+ phosphorus diffusion (~870°C) in the non-metallic area in one step, and then chemical etching is used to remove the remaining polysilicon.

[0123] Compared with comparative example 1, embodiment 1 only needs to add one step of laser film opening process, and the preparation method is simple. The TOPCon cells prepared in embodiment 1 and comparative example 1 are tested, and the performance parameters shown in Table 1 can be obtained.

[0124] Table 1: TOPCon battery performance parameter comparison table

[0125]

[0126] It can be seen that the battery performance of Example 1 is greatly improved compared with that of Comparative Example 1, the short-circuit current Isc can be increased by about 1%, the battery conversion efficiency Eta can be increased by about 0.4%, the back parasitic absorption can be greatly reduced, and the bifaciality can be increased by about 6% at most.

[0127] Compared with Comparative Example 2, in Example 1, laser is used to open the silicon oxide mask, and polysilicon and tunneling silicon oxide are removed by chemical etching process, while in Comparative Example 2, laser is used to remove PSG, polysilicon and tunneling silicon oxide in one step. Example 1 has at least the following advantages:

[0128] 1. Adjust the laser parameters for the silicon oxide mask, and use the laser film opening process to remove only the silicon oxide mask in the non-metallic area without affecting the passivation performance of the metal area;

[0129] 2. Compared with PSG, the silicon oxide mask has a higher crystallization temperature and better density, which can better block the damage of the laser to the amorphous silicon layer on the silicon substrate;

[0130] 3. Chemical etching is used to remove polysilicon and tunneling silicon oxide, which is gentler and less damaging than laser removal. At the same time, chemical etching will form Figure 7 The tower base shown (the tower base is the base left after the pyramid velvet structure is polished) can further increase the photoelectric conversion efficiency and improve the bifaciality.

[0131] Embodiment 2:

[0132] The solar cell and the preparation method in this embodiment are substantially the same as those in Embodiment 1, except that the first doping layer 11 in Embodiment 1 is prepared by a boron diffusion process, while the first doping layer 11 in this embodiment is prepared by a PECVD process.

[0133] Specifically, in this embodiment, a boron-doped amorphous silicon layer 11 ′ is first deposited on the first surface S1 by using a PECVD process, and then a first doped layer 11 , ie, a P-type doped polysilicon layer, is formed after high-temperature oxidation annealing.

[0134] Ginseng Figure 8a As shown, firstly, the silicon substrate 10 is double-sided textured, and the texture process is exactly the same as that in Example 1, which will not be described again here.

[0135] Ginseng Figure 8b As shown, a boron-doped amorphous silicon layer 11' is first deposited on the first surface S1 by a PECVD process. Exemplarily, in the PECVD process, N2O is first introduced to form a silicon oxide layer (not shown) on the first surface S1, then SiH4 and trimethyl boron are introduced to form a boron-doped amorphous silicon layer on the silicon oxide layer, and finally N2O is introduced to form a silicon oxynitride mask (not shown).

[0136] Ginseng Figure 8c As shown, finally, a first doped layer 11 is formed by a high temperature oxidation annealing process. The P-type doped amorphous silicon layer can be transformed into a P-type doped polysilicon layer by the high temperature oxidation annealing process.

[0137] Different from the first embodiment, in the present embodiment, a P-type doped polysilicon layer is prepared on the surface of the silicon substrate 10 by a PECVD process and an annealing method, and the thickness of the silicon substrate 10 is constant during this process. Figure 8c After the annealing, the total thickness of the silicon substrate 10 and the first doping layer 11 is equal to Figure 8b The total thickness of the silicon substrate 10 and the boron-doped amorphous silicon layer 11' before annealing is greater than Figure 8a The thickness of the silicon substrate 10 before the PECVD process.

[0138] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

[0139] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A method for preparing a solar cell, characterized in that: The preparation method comprises the following steps: Providing a silicon substrate, the silicon substrate comprising a first surface and a second surface arranged opposite to each other, the second surface comprising a first region and a second region; Prepare a tunneling layer, a second doping layer and a mask stacked in sequence on the second surface; Using a laser film opening process to remove the mask on the second area; Using a chemical etching process, the second doping layer on the second region is removed, and the tunneling layer and the second doping layer on the first region are retained; A second electrode contacting the second doping layer is prepared on the first region.

2. The preparation method according to claim 1, characterized in that: The mask is a silicon oxide mask with a thickness of 2nm to 50nm or 15nm to 20nm.

3. The preparation method according to claim 2, characterized in that: The laser power in the laser film opening process is 45W-55W, the scanning speed is 40000mm / s-60000mm / s, and the laser frequency is 500KHz-600KHz.

4. The preparation method according to claim 1, characterized in that: The first region includes a plurality of first sub-regions that are distributed in parallel and at equal intervals, the second electrode includes a plurality of gate lines that are distributed in parallel, and the width of the first sub-region is greater than or equal to the width of the gate line.

5. The preparation method according to claim 4, characterized in that: The width of the first sub-region is 50 μm to 150 μm, and the width of the gate line is 15 μm to 100 μm.

6. The preparation method according to claim 1, characterized in that: The chemical etching process comprises: The second doping layer on the second region is removed by using an alkaline solution, wherein the mass fraction of the alkaline solution is 3% to 15% and the treatment time is 100s to 500s; The tunneling layer on the second region and the mask on the first region are removed by using an acid solution, the mass fraction of the acid solution is 5% to 20%, and the processing time is 100s to 500s.

7. The preparation method according to claim 6, characterized in that: Before removing the second doping layer on the second region, the method further includes: removing the mask formed around the edge of the silicon substrate by using an acid solution, wherein the mass fraction of the acid solution is 5% to 30% and the processing time is 30s to 100s; and / or, After removing the tunneling layer on the second area and the mask on the first area, the method further includes: performing RCA cleaning on the silicon substrate.

8. The preparation method according to claim 1, characterized in that: Preparing a tunneling layer, a second doping layer and a mask stacked in sequence on the second surface includes: Depositing a tunneling layer, a doped amorphous silicon layer and a mask in sequence on the second surface of the silicon substrate; The silicon substrate on which the tunneling layer, the doped amorphous silicon layer and the mask are deposited is annealed at a temperature of 880° C. to 980° C. to transform the doped amorphous silicon layer into a doped polysilicon layer.

9. The preparation method according to claim 1, characterized in that: The preparation method further comprises: The light trapping structure is prepared on the first surface and the second surface of the silicon substrate by a texturing process; and / or, The second surface of the silicon substrate is polished before the tunneling layer, the second doping layer and the mask are prepared.

10. The preparation method according to claim 1, characterized in that: The preparation method further comprises: forming a first doping layer at the first surface, the first doping layer having a doping type opposite to that of the second doping layer; and, A first electrode is prepared on the first surface and in contact with the first doping layer.

11. The preparation method according to claim 10, characterized in that: The preparation method further comprises: Prepare a first passivation layer and / or a first anti-reflection layer on the first surface of the silicon substrate; A second passivation layer and / or a second anti-reflection layer is prepared on the second surface of the silicon substrate.

12. The preparation method according to claim 11, characterized in that: The first anti-reflection layer and / or the second anti-reflection layer is a laminated film formed by any one or more of a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer, and has a thickness of 60 nm to 130 nm; and / or, The first passivation layer and / or the second passivation layer is an aluminum oxide passivation layer. The thickness of the first passivation layer is 2nm to 7nm or 3nm to 6nm, and the thickness of the second passivation layer is 3nm to 5nm.

13. The preparation method according to claim 10, characterized in that: The tunneling layer is a silicon oxide layer, a silicon oxynitride layer, or a combination of the two, and has a thickness of 1 nm to 3 nm; and / or, The first doped layer is formed by a diffusion process or deposited by a PECVD process. The first doped layer is a P-type doped layer with a surface doping concentration of 3E18 cm -3 ~3E19cm -3 and / or, The second doped layer is an N-type doped polysilicon layer with a surface doping concentration of 1E20cm -3 ~1E21cm -3 , thickness is 1nm~120nm or 80nm~100nm; The silicon substrate is an N-type silicon substrate.

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