Light emitting diode epitaxial wafer and preparation method thereof

Abstract

The embodiment of the present invention discloses a light-emitting diode epitaxial wafer and a preparation method thereof. By setting a transition layer between a first semiconductor layer and a quantum well layer, and the surface of the first semiconductor layer away from the substrate includes a concave-convex structure, the lattice mismatch stress generated at the interface formed between the surface of the first semiconductor layer away from the substrate and the transition layer can be released, the crystal quality of the transition layer formed on the surface of the first semiconductor layer is improved, the incorporation capability of the high-component set element of the quantum well layer is effectively improved, the overall crystal quality of the quantum well layer is improved, and the luminous efficiency of the quantum well layer of the high-component set element is improved. The component of the set element in at least one tensile stress providing layer of the transition layer is greater than the component of the set element in the quantum well layer, and the tensile stress generated by the tensile stress providing layer on the quantum well layer can at least partially balance the compressive stress generated by the first semiconductor layer on the quantum well layer, weaken or even eliminate the QCSE effect, and further improve the luminous efficiency.

Description

Technical Field

[0001] The invention relates to the field of semiconductor technology, and in particular to a light emitting diode epitaxial wafer and a preparation method thereof. Background Art

[0002] Micro-LEDs are hailed as the next generation of display devices because of their advantages such as high responsiveness, high brightness, high contrast, ultra-high resolution and low power consumption.

[0003] Epitaxial wafers are used to make Micro-LEDs. Epitaxial wafers usually include N-GaN, quantum well layers and P-GaN. The quantum well layers include InGaN. Since the lattice constant of InGaN is greater than that of GaN, the quantum well layer is subject to compressive stress. The higher the In content of the quantum well layer, the more severe the compressive stress caused by the lattice mismatch, making it extremely difficult to grow InGaN films with high In content and the film quality is very poor. In addition, the large compressive stress in InGaN makes its quantum confined Stark effect (QCSE) serious, and there is a large piezoelectric polarization field. The presence of this piezoelectric field will cause the energy band to tilt, causing the spatial distribution of the electron-hole wave function to separate, resulting in a decrease in the probability of carrier radiation recombination, a red shift in the luminescence peak, and a reduction in luminescence efficiency.

[0004] Therefore, how to effectively improve the incorporation capacity of In components and reduce the compressive stress inside the quantum well becomes an urgent problem to be solved. Summary of the invention

[0005] The present invention provides a light-emitting diode epitaxial wafer and a preparation method thereof, so as to effectively improve the incorporation capability of In components, reduce the compressive stress inside the quantum well, improve the overall crystal quality of the quantum well layer, and improve the luminous efficiency.

[0006] According to one aspect of the present invention, a light emitting diode epitaxial wafer is provided, comprising: a substrate, and a first semiconductor layer, a quantum well layer, and a second semiconductor layer stacked on one side of the substrate;

[0007] A transition layer is also arranged between the first semiconductor layer and the quantum well layer, and a surface of the first semiconductor layer away from the substrate comprises a concave-convex structure;

[0008] The transition layer comprises at least one tensile stress providing layer, wherein the composition of the set element in the at least one tensile stress providing layer is greater than the composition of the set element in the quantum well layer, so as to generate tensile stress on the quantum well layer.

[0009] Optionally, the transition layer includes a first tensile stress providing layer and at least one second tensile stress providing layer; the second tensile stress providing layer is located between the first tensile stress providing layer and the quantum well layer;

[0010] The composition of the set element in the second tensile stress providing layer is less than that in the first tensile stress providing layer, and the composition of the set element in the second tensile stress providing layer is greater than or equal to that in the quantum well layer.

[0011] Optionally, the transition layer includes at least two second tensile stress providing layers, and the composition of the set elements in the second tensile stress providing layers gradually decreases along the direction pointing from the first semiconductor layer to the quantum well layer.

[0012] Optionally, along the direction from the first semiconductor layer to the quantum well layer, the thickness of the tensile stress providing layer gradually decreases.

[0013] Optionally, the transition layer includes a first stress-providing layer and at least one third stress-providing layer; the third stress-providing layer is located between the first semiconductor layer and the first stress-providing layer;

[0014] The composition of the set element in the third stress-providing layer is less than that in the first stress-providing layer, and the composition of the set element in the third stress-providing layer is greater than or equal to that in the quantum well layer.

[0015] Optionally, the transition layer includes at least two third tensile stress providing layers, and the composition of the setting elements in the third tensile stress providing layers gradually increases along the direction pointing from the first semiconductor layer to the quantum well layer.

[0016] Optionally, the light-emitting diode epitaxial wafer also includes a blocking layer, which is arranged between the first tensile stress-providing layer and the second tensile stress-providing layer; and / or the blocking layer is arranged on a side of the second tensile stress-providing layer away from the substrate; the blocking layer is used to block elements of the first tensile stress-providing layer or the second tensile stress-providing layer from entering the quantum well layer.

[0017] Optionally, the thickness of the barrier layer is smaller than the thickness of the first tensile stress-providing layer, and smaller than the thickness of the second tensile stress-providing layer.

[0018] Optionally, the barrier layer and the first semiconductor layer contain the same element.

[0019] Optionally, the first semiconductor layer includes a GaN layer, the quantum well layer includes an InGaN layer, and the setting element includes In.

[0020] Optionally, one of the tensile stress providing layers of the transition layer includes an InN layer.

[0021] Optionally, the tensile stress providing layer of the transition layer further comprises an InxGa1-xN layer, an InyGa1-yN layer and an InzGa1-zN layer, wherein the InxGa1-xN layer, the InyGa1-yN layer and the InzGa1-zN layer are on a side of the InN layer away from the substrate, and the InxGa1-xN layer, the InyGa1-yN layer and the InzGa1-zN layer are stacked in sequence along a direction from the first semiconductor layer to the quantum well layer, wherein 0.5 <x<1,0.3<y<1,0.1<z<1,x> y>z, and x is less than the In composition of the InN layer.

[0022] According to another aspect of the present invention, there is provided a method for preparing a light emitting diode epitaxial wafer, comprising:

[0023] growing a first semiconductor layer on one side of the substrate;

[0024] Roughening the surface of the first semiconductor layer away from the substrate to form a concave-convex structure;

[0025] Growing a transition layer on a side of the first semiconductor layer away from the substrate;

[0026] A quantum well layer is grown on a side of the transition layer away from the substrate; wherein the transition layer includes at least one tensile stress providing layer, and the composition of the set element in the at least one tensile stress providing layer is greater than the composition of the set element in the quantum well layer, so as to generate tensile stress on the quantum well layer;

[0027] A second semiconductor layer is grown on a surface of the quantum well layer away from the substrate.

[0028] Optionally, growing a transition layer on a side of the first semiconductor layer away from the substrate includes:

[0029] Adding a surfactant to grow a first tensile stress-providing layer on a side of the first semiconductor layer away from the substrate;

[0030] At least one second tensile stress providing layer is grown on a side of the first tensile stress providing layer away from the substrate, wherein the composition of the set element in the second tensile stress providing layer is less than the composition of the set element in the first tensile stress providing layer, and the composition of the set element in the second tensile stress providing layer is greater than or equal to the composition of the set element in the quantum well layer.

[0031] Optionally, before growing at least one second stress-providing layer on a side of the first stress-providing layer away from the substrate, the method further comprises: growing a barrier layer on a side of the first stress-providing layer away from the substrate;

[0032] Growing at least one second stress-providing layer on a side of the first stress-providing layer away from the substrate comprises:

[0033] At least one second tensile stress providing layer is grown on a side of the barrier layer away from the substrate.

[0034] Optionally, growing a first semiconductor layer on one side of the substrate includes:

[0035] Epitaxially growing a buffer layer and / or a superlattice composite buffer layer on one side of the cleaned substrate at a growth pressure of 100-500 Torr;

[0036] growing a first semiconductor layer on the superlattice composite buffer layer;

[0037] The surface of the first semiconductor layer away from the substrate is roughened to form a concave-convex structure, including:

[0038] HCl and H2 are introduced to roughen the surface of the first semiconductor layer away from the substrate to form a concave-convex structure, wherein the flow rate of HCl is 10-800 sccm, the flow rate of H2 is 100-2000 sccm, and the introduction time is 2-20 min;

[0039] Growing a transition layer on a side of the first semiconductor layer away from the substrate comprises:

[0040] Adding a surfactant, growing a first tensile stress providing layer on a side of the first semiconductor layer away from the substrate, with a growth temperature of 720-850° C. and a growth thickness of 30-1000 nm;

[0041] A barrier layer is grown on the side of the first stress-providing layer away from the substrate, with a growth temperature of 900-1000° C. and a growth thickness of 20-50 nm;

[0042] At least one second tensile stress providing layer is grown on a side of the barrier layer away from the substrate; wherein the composition of the set element in the second tensile stress providing layer is less than the composition of the set element in the first tensile stress providing layer, and the composition of the set element in the second tensile stress providing layer is greater than or equal to the composition of the set element in the quantum well layer.

[0043] The light-emitting diode epitaxial wafer and the preparation method thereof of the embodiment of the present invention, by setting a transition layer between the first semiconductor layer and the quantum well layer, and the surface of the first semiconductor layer away from the substrate side includes a concave-convex structure, the lattice mismatch stress generated at the interface formed by the surface of the first semiconductor layer away from the substrate side and the transition layer can be greatly released, the crystal quality of the transition layer formed on the surface of the first semiconductor layer is improved, the incorporation capability of the high-component set element of the quantum well layer is effectively improved, the overall crystal quality of the quantum well layer is improved, and the luminous efficiency of the quantum well layer of the high-component set element is improved. In addition, the concave-convex structure on the surface of the first semiconductor layer is conducive to enhancing the surface energy of the quantum well layer, reducing the phase separation of the epitaxial growth of the high-component set element, and improving its heat resistance. The transition layer includes at least one tensile stress providing layer, the component of the set element in at least one tensile stress providing layer is greater than the component of the set element in the quantum well layer, and the tensile stress generated by the tensile stress providing layer on the quantum well layer can at least partially balance the compressive stress generated by the first semiconductor layer on the quantum well layer, thereby weakening or even eliminating the QCSE effect generated by the compressive stress, and further improving the luminous efficiency.

[0044] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0046] Figure 1 It is a structural schematic diagram of a light emitting diode epitaxial wafer provided by an embodiment of the present invention;

[0047] Figure 2 is a schematic structural diagram of another light emitting diode epitaxial wafer provided by an embodiment of the present invention;

[0048] Figure 3 is a schematic structural diagram of another light emitting diode epitaxial wafer provided by an embodiment of the present invention;

[0049] Figure 4 is a schematic structural diagram of another light emitting diode epitaxial wafer provided by an embodiment of the present invention;

[0050] Figure 5 is a schematic structural diagram of another light emitting diode epitaxial wafer provided by an embodiment of the present invention;

[0051] Figure 6 is a schematic structural diagram of another light emitting diode epitaxial wafer provided by an embodiment of the present invention;

[0052] Figure 7 is a schematic structural diagram of another light emitting diode epitaxial wafer provided by an embodiment of the present invention;

[0053] Figure 8 It is a flow chart of a method for preparing a light emitting diode epitaxial wafer provided by an embodiment of the present invention;

[0054] Fig. 9 It is a flow chart of another method for preparing a light emitting diode epitaxial wafer provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0055] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0056] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0057] Figure 1 Schematic diagram of the structure of a light-emitting diode epitaxial wafer provided by an embodiment of the present invention, which can be used to prepare Micro-LED. Figure 1The light-emitting diode epitaxial wafer includes: a substrate 110 and a first semiconductor layer 120, a quantum well layer 130 and a second semiconductor layer 140 stacked on one side of the substrate 110; a transition layer 150 is also arranged between the first semiconductor layer 120 and the quantum well layer 130, and the surface of the first semiconductor layer 120 away from the substrate 110 includes a concave-convex structure; the transition layer 150 includes at least one tensile stress providing layer, and the composition of the set element in the at least one tensile stress providing layer is greater than the composition of the set element in the quantum well layer 130, so as to generate tensile stress on the quantum well layer 130.

[0058] The substrate 110 may be a silicon substrate, a sapphire substrate, a silicon carbide substrate or a gallium nitride substrate. The first semiconductor layer 120, the quantum well layer 130 and the second semiconductor layer 140 are arranged along the epitaxial growth direction Y, and the quantum well layer 130 is located between the first semiconductor layer 120 and the second semiconductor layer 140. Specifically, the first semiconductor layer 120 is on one side of the substrate 110, the quantum well layer 130 is located on the side of the first semiconductor layer 120 away from the substrate 110, and the second semiconductor layer 140 is located on the side of the quantum well layer 130 away from the substrate 110. The first semiconductor layer 120 is an N-type semiconductor layer, and the second semiconductor layer 140 is a P-type semiconductor layer; or the first semiconductor layer 120 is a P-type semiconductor layer, and the second semiconductor layer 140 is an N-type semiconductor layer. Exemplarily, the N-type semiconductor layer may include N-GaN, and the P-type semiconductor layer may include P-GaN. The quantum well layer 130 includes a set element. Optionally, the quantum well layer 130 includes a multi-quantum well layer 130 formed by alternately arranged InGaN / GaN. In this case, the set element included in the quantum well layer 130 is In. In other optional embodiments of the present invention, the set element included in the quantum well layer may also be other elements, such as P or Al.

[0059] In this embodiment, the surface of the first semiconductor layer 120 away from the substrate 110 includes a concave-convex structure, that is, the surface of the first semiconductor layer 120 away from the substrate 110 is uneven, and the concave-convex structure can be obtained by roughening the surface of the first semiconductor layer 120 away from the substrate 110. The concave-convex structure includes a concave structure 121 and a convex structure 122. The number of the concave structures 121 can be multiple, and the number of the convex structures 122 can also be multiple. The concave structures 121 and the convex structures 122 can occupy the entire surface of the first semiconductor layer 120 away from the substrate 110. In some embodiments, the bottom surface of the concave structure 121 is Figure 1The bottom surface of the recessed structure 121 is a plane parallel to the surface of the first semiconductor layer 120 close to the substrate 110. In other optional embodiments, the bottom surface of the recessed structure 121 may also be an inclined surface that is not parallel to the surface of the first semiconductor layer 120 close to the substrate 110. The bottom surface of the recessed structure 121 may also be a curved surface, which is not specifically limited in the embodiment of the present invention. The side surface of the recessed structure 121 may be parallel to the substrate 110. Figure 1 The plane shown is perpendicular to the surface of the first semiconductor layer 120 close to the substrate 110. The angle between the side surface of the recessed structure 121 and the surface of the first semiconductor layer 120 close to the substrate 110 can be greater than 90 degrees or less than 90 degrees. The side surface of the recessed structure 121 can also be a curved surface. The convex structure 122 shares a side surface with the adjacent recessed structure 121. The top surface of the convex structure 122 can be Figure 1 The plane shown is parallel to the surface of the first semiconductor layer 120 close to the substrate 110. In other optional embodiments, the top surface of the protruding structure 122 can also be an inclined surface that is not parallel to the surface of the first semiconductor layer 120 close to the substrate 110, and the top surface of the recessed structure 121 can also be a curved surface.

[0060] Figure 2 is a schematic diagram of the structure of another light emitting diode epitaxial wafer provided by an embodiment of the present invention, referring to Figure 2 In other optional embodiments of the present invention, the concave-convex structure may also be Figure 2 The cross-section shown is a triangular structure.

[0061] Optionally, the concave-convex structure can be a periodic three-dimensional nano-pattern structure. The concave and convex three-dimensional structure is formed on the surface of the first semiconductor layer 120 away from the substrate 110, so that the lattice mismatch stress generated at the interface formed by the surface of the first semiconductor layer 120 away from the substrate 110 and the transition layer 150 can be greatly released, so that the transition layer 150 can grow into a film on the surface of the first semiconductor layer 120, and improve the crystal quality of the transition layer 150 film, reduce internal defects and dislocations. In addition, the incorporation capacity of the high-component setting element of the quantum well layer 130 is effectively improved, and the stress release at the interface can also reduce QCSE and improve the luminous efficiency of the quantum well layer 130 of the high-component setting element. In addition, the concave-convex structure on the surface of the first semiconductor layer 120 is conducive to enhancing the surface energy of the quantum well layer 130, inhibiting surface migration, making it less likely to aggregate the setting element, reducing the phase separation of the epitaxial growth of the high-component setting element, and improving its heat resistance.

[0062] Continue to refer Figure 1 and Figure 2, the transition layer 150 is arranged between the first semiconductor layer 120 and the quantum well layer 130, and the transition layer 150 includes at least one tensile stress providing layer, and the tensile stress providing layer includes a set element. Optionally, the element composition of some tensile stress providing layers is the same as the element type of the quantum well layer 130. The component of the set element in the tensile stress providing layer is greater than the component of the set element in the quantum well layer 130, so that the tensile stress providing layer can generate tensile stress on the quantum well layer 130. In this way, the tensile stress generated by the tensile stress providing layer on the quantum well layer 130 can at least partially balance the compressive stress generated by the first semiconductor layer 120 on the quantum well layer 130, thereby weakening or even eliminating the QCSE effect generated by the compressive stress, thereby improving the luminous efficiency. In the case where the quantum well layer 130 includes an InGaN layer, one of the tensile stress providing layers in the transition layer 150 can be an InN layer. In some optional embodiments, the quantum well layer 130 can be grown on the InN layer.

[0063] Optionally, a buffer layer 160 and / or a superlattice composite buffer layer 170 is further provided between the substrate 110 and the first semiconductor layer 120, wherein the buffer layer 160 may be at least one of an AlN layer, a low-temperature gallium nitride layer (formed at a temperature of 500-600°C), and an AlGaN layer, and the superlattice composite buffer layer 170 may be a periodic structure layer in which AlN / AlGaN, AlN / GaN, or AlGaN / GaN are alternately provided. Optionally, an electron blocking layer ( Figure 1 and Figure 2 not shown).

[0064] The light-emitting diode epitaxial wafer of this embodiment, by setting a transition layer between the first semiconductor layer and the quantum well layer, and the surface of the first semiconductor layer away from the substrate side includes a concave-convex structure, can greatly release the lattice mismatch stress generated at the interface formed by the surface of the first semiconductor layer away from the substrate side and the transition layer, improve the crystal quality of the transition layer formed on the surface of the first semiconductor layer, effectively improve the incorporation ability of the high-component set element of the quantum well layer, improve the overall crystal quality of the quantum well layer, and improve the luminous efficiency of the quantum well layer of the high-component set element. In addition, the concave-convex structure on the surface of the first semiconductor layer is conducive to enhancing the surface energy of the quantum well layer, reducing the phase separation of the epitaxial growth of the high-component set element, and improving its heat resistance. High-temperature growth will further improve the quality of the quantum well and improve the internal quantum efficiency. The transition layer includes at least one tensile stress providing layer, and the component of the set element in at least one tensile stress providing layer is greater than the component of the set element in the quantum well layer. The tensile stress generated by the tensile stress providing layer on the quantum well layer can at least partially balance the compressive stress generated by the first semiconductor layer on the quantum well layer, thereby weakening or even eliminating the QCSE effect generated by the compressive stress, and further improving the luminous efficiency.

[0065] Figure 3 is a schematic diagram of the structure of another light emitting diode epitaxial wafer provided by an embodiment of the present invention, referring to Figure 3 Optionally, the transition layer 150 includes a first tensile stress providing layer 151 and at least one second tensile stress providing layer 152; the second tensile stress providing layer 152 is located between the first tensile stress providing layer 151 and the quantum well layer 130; the composition of the set element in the second tensile stress providing layer 152 is less than the composition of the set element in the first tensile stress providing layer 151, and the composition of the set element in the second tensile stress providing layer 152 is greater than or equal to the composition of the set element in the quantum well layer 130.

[0066] Optionally, the quantum well layer 130 includes an InGaN layer, and the first tensile stress providing layer 151 includes an InN layer. Specifically, the structures of the first tensile stress providing layer 151 and the quantum well layer 130 still need to be matched, otherwise the quantum well layer 130 is difficult to grow. In this embodiment, the transition layer 150 includes a first tensile stress providing layer 151 and at least one second tensile stress providing layer 152. The second tensile stress providing layer 152 is stacked with the first tensile stress providing layer 151 along the epitaxial growth direction. The composition of the set element in the second tensile stress providing layer 152 is less than the composition of the set element in the first tensile stress providing layer 151, and the composition of the set element in the second tensile stress providing layer 152 is greater than or equal to the composition of the set element in the quantum well layer 130. Therefore, the second tensile stress providing layer 152 is provided as a buffer between the first tensile stress providing layer 151 and the quantum well layer 130. Compared with the structure in which the transition layer 150 includes only one first tensile stress providing layer 151, the lattice mismatch stress between the quantum well layer 130 and the transition layer 150 can be reduced, so that the structures of the transition layer 150 and the quantum well layer 130 are more matched, and the crystal quality of the quantum well layer 130 is improved.

[0067] Figure 4 is a schematic diagram of the structure of another light emitting diode epitaxial wafer provided by an embodiment of the present invention, referring to Figure 4 Optionally, the transition layer 150 includes at least two layers of second tensile stress providing layers 152, and the composition of the set element in the second tensile stress providing layer 152 gradually decreases along the direction from the first semiconductor layer 120 to the quantum well layer 130 (i.e., the epitaxial growth direction Y). In this way, the difference between the composition of the set element in each tensile stress providing layer (including the first tensile stress providing layer 151 and the second tensile stress providing layer 152) and the composition of the set element in the quantum well layer 130 gradually decreases, and the composition of the set element in the first tensile stress providing layer 151 gradually transitions to the composition of the set element in the quantum well layer 130, so that the transition layer 150 can maintain a weak tensile stress along the epitaxial growth direction, realize the full release of the stress of the quantum well layer 130, and ensure the high-component set element incorporation capability of the quantum well layer 130.

[0068] in, Figure 4 The case of three layers of the second tensile stress providing layer 152 is exemplarily shown in FIG. Figure 4 , the first tensile stress providing layer 151 is an InN layer, the three second tensile stress providing layers 152 are respectively an InxGa1-xN layer 1521, an InyGa1-yN layer 1522 and an InzGa1-zN layer 1523, the InxGa1-xN layer 1521, the InyGa1-yN layer 1522 and the InzGa1-zN layer 1523 are on the side of the InN layer away from the substrate 110, and the InxGa1-xN layer 1521, the InyGa1-yN layer 1522 and the InzGa1-zN layer 1523 are stacked in sequence along the direction Y from the first semiconductor layer 120 to the quantum well layer 130, wherein 0.5 <x<1,0.3<y<1,0.1<z<1,x> y>z, and x is less than the In component of the InN layer.

[0069] Optionally, along a direction Y from the first semiconductor layer 120 to the quantum well layer 130 , the thickness of the tensile stress providing layer (including the first tensile stress providing layer and the second tensile stress providing layer) gradually decreases.

[0070] Optionally, in the above embodiment, the thickness of the first tensile stress providing layer 151 is 30~1000nm, the thickness of each second tensile stress providing layer 152 is 10~150nm, the thickness of the InxGa1-xN layer 1521 is greater than the thickness of the InyGa1-yN layer 1522, and the thickness of the InyGa1-yN layer 1522 is greater than the thickness of the InzGa1-zN layer 1523.

[0071] Figure 5 is a schematic diagram of the structure of another light emitting diode epitaxial wafer provided by an embodiment of the present invention, referring to Figure 5 , the transition layer 150 includes a first tensile stress providing layer 151 and at least one third tensile stress providing layer 153; the third tensile stress providing layer 153 is located between the first semiconductor layer 120 and the first tensile stress providing layer 151; the composition of the set element in the third tensile stress providing layer 153 is less than the composition of the set element in the first tensile stress providing layer 151, and the composition of the set element in the third tensile stress providing layer 153 is greater than or equal to the composition of the set element in the quantum well layer 130. In this way, the third tensile stress providing layer 153 is easier to grow on the first semiconductor layer 120 than the first tensile stress providing layer 151, and the third tensile stress providing layer 153 serves as a buffer between the first semiconductor layer 120 and the first tensile stress providing layer 151, that is, the first semiconductor layer 120 and the first tensile stress providing layer 151 are transitioned through the third tensile stress providing layer 153, which can improve the film quality in the transition layer 150 and the crystal quality in the transition layer 150.

[0072] Continue to refer Figure 5Optionally, the transition layer 150 includes at least two third tensile stress providing layers 153. Along the direction Y pointing from the first semiconductor layer 120 to the quantum well layer 130, the composition of the set element in the third tensile stress providing layer 153 gradually increases, thereby achieving a gradual transition of the composition of the set element and further improving the crystal quality of the transition layer 150. Figure 5 Schematically shows a case where there are three third tensile stress providing layers 153 .

[0073] Figure 6 is a schematic structural diagram of another light emitting diode epitaxial wafer provided by an embodiment of the present invention, Figure 7 is a schematic diagram of the structure of another light emitting diode epitaxial wafer provided by an embodiment of the present invention, referring to Figure 6 and Figure 7 Optionally, the light-emitting diode epitaxial wafer further includes a barrier layer 154, which is disposed between the first tensile stress providing layer 151 and the second tensile stress providing layer 152; and / or, the barrier layer 154 is disposed on a side of the second tensile stress providing layer 152 away from the substrate 110; the barrier layer 154 is used to block the elements of the first tensile stress providing layer 151 or the second tensile stress providing layer 152 from entering the quantum well layer 130. Figure 6 FIG. 4 shows a case where the barrier layer 154 is located between the first tensile stress providing layer 151 and the second tensile stress providing layer 152. Figure 7 The barrier layer 154 is located between the first tensile stress providing layer 151 and the second tensile stress providing layer 152 , and a portion of the second tensile stress providing layer 152 (eg, the InxGa1-xN layer 1521 and the InyGa1-yN layer 1522 ) is located away from the substrate 110 .

[0074] Specifically, in the preparation process of the first stress-providing layer 151, a surfactant needs to be added, and the elements of the surfactant may remain in the first stress-providing layer 151. The surfactant elements have a destructive effect on the quantum well, and by providing the barrier layer 154, the elements of the surfactant can be blocked from entering the quantum well layer 130, thereby ensuring the luminous efficiency of the quantum well layer 130. In addition, in the subsequent process, the elements (such as In) in the first stress-providing layer 151 and the second stress-providing layer 152 may also precipitate, and the barrier layer 154 can also block the elements in the first stress-providing layer 151 and the second stress-providing layer 152 from entering the quantum well layer 130, thereby ensuring the luminous efficiency of the quantum well layer 130.

[0075] Optionally, the thickness of the barrier layer 154 is less than the thickness of the first tensile stress providing layer 151, and less than the thickness of the second tensile stress providing layer 152. In this way, the stress formed by the barrier layer 154 on the quantum well layer 130 and the stress effect of the tensile stress providing layer in the transition layer 150 on the quantum well layer 130 can be reduced. Optionally, the thickness of the barrier layer 154 is 20-50 nm.

[0076] Optionally, among the second tensile stress providing layers 152 , the second tensile stress providing layer 152 (InzGa1-zN layer 1523 ) closest to the quantum well layer 130 does not include a barrier layer on a side away from the substrate 110 . That is, the second tensile stress providing layer 152 closest to the quantum well layer 130 is in direct contact with the quantum well layer 130 , thereby ensuring the film formation quality of the quantum well layer 130 .

[0077] Optionally, the barrier layer 154 and the first semiconductor layer 120 include the same element. For example, the first semiconductor layer 120 includes GaN, and the barrier layer 154 also includes GaN.

[0078] An embodiment of the present invention further provides a method for preparing a light-emitting diode epitaxial wafer. The method is used to prepare the light-emitting diode epitaxial wafer of any of the above embodiments of the present invention. Figure 8 is a flow chart of a method for preparing a light emitting diode epitaxial wafer provided by an embodiment of the present invention, with reference to Figure 8 , the light emitting diode epitaxial wafer preparation method comprises:

[0079] S210 , growing a first semiconductor layer on one side of the substrate.

[0080] S220, roughening the surface of the first semiconductor layer away from the substrate to form a concave-convex structure.

[0081] S230, growing a transition layer on a side of the first semiconductor layer away from the substrate.

[0082] The transition layer includes at least one tensile stress providing layer, and the composition of the set element in the at least one tensile stress providing layer is greater than the composition of the set element in the quantum well layer, so as to generate tensile stress on the quantum well layer.

[0083] Optionally, S230 includes: adding a surfactant to grow a first tensile stress-providing layer on a side of the first semiconductor layer away from the substrate; and growing at least one second tensile stress-providing layer on a side of the first tensile stress-providing layer away from the substrate.

[0084] The composition of the set element in the second tensile stress providing layer is less than the composition of the set element in the first tensile stress providing layer 151, and the composition of the set element in the second tensile stress providing layer is greater than or equal to the composition of the set element in the quantum well layer.

[0085] Optionally, the surfactant may include at least one of triethyl antimony, diethyl zinc, bismuth magnesium, and tetrakis (dimethylamino) germanium. The rational use of surfactants can significantly improve epitaxial quality, regulate surface morphology, reduce defects, and release stress, helping to achieve a higher quality first stress-providing layer material. The introduction of surfactants can make the surface nucleation pinning effect stronger, enhance the surface energy, so that the first stress-providing layer can be firmly formed on the surface of the concave-convex structure of the first semiconductor layer, increase the growth temperature of the first stress-providing layer, and ultimately achieve a high-quality first stress-providing layer.

[0086] Optionally, before growing at least one second stress-providing layer on the side of the first stress-providing layer away from the substrate, a barrier layer is grown on the side of the first stress-providing layer away from the substrate, and after the barrier layer is formed, at least one second stress-providing layer is grown on the side of the barrier layer away from the substrate. The barrier layer can prevent the residual surfactant elements in the first stress-providing layer and the elements of the first stress-providing layer and the second stress-providing layer from entering the quantum well layer, thereby ensuring the luminescence efficiency of the quantum well layer.

[0087] S240, growing a quantum well layer on a side of the transition layer away from the substrate.

[0088] S250, growing a second semiconductor layer on the surface of the quantum well layer away from the substrate.

[0089] The method for preparing a light emitting diode of this embodiment is used to prepare a light emitting diode epitaxial wafer of any of the above embodiments of the present invention, and has the beneficial effects of the light emitting diode epitaxial wafer of any of the above embodiments of the present invention.

[0090] The embodiment of the present invention also provides another method for preparing a light emitting diode epitaxial wafer. Fig. 9 is a flow chart of another method for preparing a light emitting diode epitaxial wafer provided by an embodiment of the present invention, with reference to Fig. 9 , the preparation method of the light emitting diode epitaxial wafer comprises:

[0091] S310 , epitaxially growing a buffer layer and / or a superlattice composite buffer layer on one side of the cleaned substrate, with a growth pressure of 100-500 Torr.

[0092] The buffer layer may be at least one of an AlN layer, a low-temperature gallium nitride layer (formed at a temperature of 500-600°C), and an AlGaN layer, and the superlattice composite buffer layer may be a periodic structure layer in which AlN / AlGaN, AlN / GaN, or AlGaN / GaN are alternately arranged. The thickness of the buffer layer may be 10-300nm, and the thickness of the superlattice composite buffer layer may be 10-500nm. The growth of the buffer layer and the superlattice buffer layer may be carried out by metal-organic chemical vapor deposition (MOCVD).

[0093] S320 , growing a first semiconductor layer on the superlattice composite buffer layer.

[0094] The thickness of the first semiconductor layer is 1-5 microns, the first semiconductor layer includes N-GaN, and the silicon doping concentration in the first semiconductor layer is 8E18-9E19 / cm 2 .

[0095] S330, introducing HCl and H2 to roughen the surface of the first semiconductor layer away from the substrate to form a concave-convex structure, wherein the flow rate of HCl is 10-800 sccm, the flow rate of H2 is 100-2000 sccm, and the introduction time is 2-20 min.

[0096] Specifically, S330 is performed after the growth of the first semiconductor layer thin film is stopped.

[0097] S340, adding a surfactant, growing a first tensile stress providing layer on a side of the first semiconductor layer away from the substrate, with a growth temperature of 720-850° C. and a growth thickness of 30-1000 nm.

[0098] For example, when the surfactant is triethyl antimony, the triethyl antimony flow rate is 10-100 sccm. The first tensile stress providing layer 151 includes an InN layer.

[0099] S350, growing a barrier layer on a side of the first stress-providing layer away from the substrate, with a growth temperature of 900-1000° C. and a growth thickness of 20-50 nm.

[0100] The barrier layer may be a GaN layer.

[0101] S360, growing at least one second tensile stress providing layer on a side of the barrier layer away from the substrate.

[0102] The composition of the set element in the second tensile stress providing layer is less than that in the first tensile stress providing layer, and the composition of the set element in the second tensile stress providing layer is greater than or equal to that in the quantum well layer.

[0103] Optionally, after the growth of the blocking layer is completed, three InxGa1-xN layers, InyGa1-yN layers, and InzGa1-zN layers with decreasing compositions are continuously grown along the epitaxial growth direction, where 0.5 < x < 1, 0.3 < y < 1, 0.1 < z < 1, and x > y > z. The growth temperature is between 750 and 900 °C, the thickness of each of the three layers is 10 to 150 nm, and the thickness of the InxGa1-xN layer > the thickness of the InyGa1-yN layer > the thickness of the InzGa1-zN layer.

[0104] S370. Grow a quantum well layer on the side of the second stress-providing layer away from the substrate.

[0105] Optionally, the quantum well region contains 1 to 14 pairs of multiple quantum wells (MQW). The thickness of the barrier GaN is 5 to 50 nm, the thickness of the well InGaN is 2 to 30 nm, the growth temperature of InGaN is 750 to 1000 °C, and the composition change range of InGaN is In0.1Ga0.9N to In0.9Ga0.1N.

[0106] S380. Grow an electron blocking layer on the side of the quantum well layer away from the substrate.

[0107] Among them, the electron blocking layer is a Mg-doped p-type AlGaN layer with a thickness of 20 to 200 nm and a growth temperature of 900 to 1020 °C.

[0108] S390. Grow a second semiconductor layer on the side of the electron blocking layer away from the substrate.

[0109] Among them, the second semiconductor layer is Mg-doped p-GaN, the thickness of p-GaN is 50 to 300 nm, and the growth temperature is 900 to 1000 °C. The Mg doping concentration is 1E19 - 8E19 / cm 2 .

[0110] It should be understood that various forms of the processes shown above can be used, steps can be reordered, added, or deleted. For example, the steps described in the present invention can be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. This is not limited herein.

[0111] The above specific embodiments do not constitute a limitation to the protection scope of the present invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims

1. A light emitting diode epitaxial wafer, characterized in that: include: A substrate and a first semiconductor layer, a quantum well layer, and a second semiconductor layer stacked on one side of the substrate; A transition layer is further provided between the first semiconductor layer and the quantum well layer, and a surface of the first semiconductor layer away from the substrate comprises a concave-convex structure; The transition layer includes at least one tensile stress providing layer, wherein the composition of the set element in the at least one tensile stress providing layer is greater than the composition of the set element in the quantum well layer, so as to generate tensile stress on the quantum well layer; the transition layer includes a first tensile stress providing layer and at least one second tensile stress providing layer; The second tensile stress providing layer is located between the first tensile stress providing layer and the quantum well layer; The composition of the setting element in the second tensile stress providing layer is less than the composition of the setting element in the first tensile stress providing layer, and the composition of the setting element in the second tensile stress providing layer is greater than or equal to the composition of the setting element in the quantum well layer; The first semiconductor layer includes a GaN layer, the quantum well layer includes an InGaN layer; the setting element includes In; and the first tensile stress providing layer includes an InN layer; The second tensile stress providing layer comprises an InxGa1-xN layer, an InyGa1-yN layer and an InzGa1-zN layer, wherein the InxGa1-xN layer, the InyGa1-yN layer and the InzGa1-zN layer are on a side of the InN layer away from the substrate, and the InxGa1-xN layer, the InyGa1-yN layer and the InzGa1-zN layer are stacked in sequence along a direction from the first semiconductor layer to the quantum well layer, wherein 0.5 <x<1,0.3<y<1,0.1<z<1,x> y>z, and x is less than the In composition of the InN layer.

2. The light emitting diode epitaxial wafer according to claim 1, characterized in that: The transition layer includes at least two layers of the second tensile stress providing layers, and the composition of the setting element in the second tensile stress providing layers gradually decreases along the direction from the first semiconductor layer to the quantum well layer.

3. The light emitting diode epitaxial wafer according to claim 1, characterized in that: Along the direction from the first semiconductor layer to the quantum well layer, the thickness of the tensile stress providing layer gradually decreases.

4. The light emitting diode epitaxial wafer according to claim 1, characterized in that: The transition layer comprises a first tensile stress providing layer and at least one third tensile stress providing layer; the third tensile stress providing layer is located between the first semiconductor layer and the first tensile stress providing layer; The composition of the setting element in the third tensile stress providing layer is less than that in the first tensile stress providing layer, and the composition of the setting element in the third tensile stress providing layer is greater than or equal to that in the quantum well layer.

5. The light emitting diode epitaxial wafer according to claim 4, characterized in that: The transition layer includes at least two layers of the third tensile stress providing layers, and the composition of the setting element in the third tensile stress providing layers gradually increases along the direction from the first semiconductor layer to the quantum well layer.

6. The light emitting diode epitaxial wafer according to claim 1, characterized in that: It also includes a barrier layer, which is arranged between the first tensile stress-providing layer and the second tensile stress-providing layer; and / or the barrier layer is arranged on a side of the second tensile stress-providing layer away from the substrate; the barrier layer is used to block elements of the first tensile stress-providing layer or the second tensile stress-providing layer from entering the quantum well layer.

7. The light emitting diode epitaxial wafer according to claim 6, characterized in that: The barrier layer has a thickness less than that of the first tensile stress-providing layer, and less than that of the second tensile stress-providing layer.

8. A method for preparing a light emitting diode epitaxial wafer, characterized in that: include: growing a first semiconductor layer on one side of the substrate; Roughening the surface of the first semiconductor layer away from the substrate to form a concave-convex structure; Growing a transition layer on a side of the first semiconductor layer away from the substrate; A quantum well layer is grown on the side of the transition layer away from the substrate; wherein the transition layer includes at least one tensile stress providing layer, and the composition of the set element in at least one tensile stress providing layer is greater than the composition of the set element in the quantum well layer, so as to generate tensile stress on the quantum well layer; Growing a second semiconductor layer on a surface of the quantum well layer away from the substrate; The transition layer comprises a first tensile stress providing layer and at least one second tensile stress providing layer; the second tensile stress providing layer is located between the first tensile stress providing layer and the quantum well layer; The composition of the setting element in the second tensile stress providing layer is less than the composition of the setting element in the first tensile stress providing layer, and the composition of the setting element in the second tensile stress providing layer is greater than or equal to the composition of the setting element in the quantum well layer; The first semiconductor layer includes a GaN layer, the quantum well layer includes an InGaN layer; the setting element includes In; and the first tensile stress providing layer includes an InN layer; The second tensile stress providing layer of the transition layer further comprises an InxGa1-xN layer, an InyGa1-yN layer and an InzGa1-zN layer, wherein the InxGa1-xN layer, the InyGa1-yN layer and the InzGa1-zN layer are on a side of the InN layer away from the substrate, and the InxGa1-xN layer, the InyGa1-yN layer and the InzGa1-zN layer are stacked in sequence along a direction from the first semiconductor layer to the quantum well layer, wherein 0.5 <x<1,0.3<y<1,0.1<z<1,x> y>z, and x is less than the In composition of the InN layer.

9. The method for preparing a light emitting diode epitaxial wafer according to claim 8, characterized in that: Growing a transition layer on a side of the first semiconductor layer away from the substrate comprises: adding a surfactant to grow a first tensile stress providing layer on a side of the first semiconductor layer away from the substrate; At least one second tensile stress providing layer is grown on a side of the first tensile stress providing layer away from the substrate, wherein the composition of the set element in the second tensile stress providing layer is less than the composition of the set element in the first tensile stress providing layer, and the composition of the set element in the second tensile stress providing layer is greater than or equal to the composition of the set element in the quantum well layer.

10. The method for preparing a light emitting diode epitaxial wafer according to claim 9, characterized in that: Before growing at least one second stress-providing layer on the side of the first stress-providing layer away from the substrate, the method further includes: growing a barrier layer on the side of the first stress-providing layer away from the substrate; Growing at least one second stress-providing layer on a side of the first stress-providing layer away from the substrate comprises: At least one second tensile stress providing layer is grown on a side of the barrier layer away from the substrate.

11. The method for preparing a light emitting diode epitaxial wafer according to claim 8, characterized in that: The step of growing a first semiconductor layer on one side of the substrate comprises: Epitaxially growing a buffer layer and / or a superlattice composite buffer layer on one side of the cleaned substrate at a growth pressure of 100-500 Torr; growing the first semiconductor layer on the superlattice composite buffer layer; The step of roughening the surface of the first semiconductor layer away from the substrate to form a concave-convex structure includes: Passing HCl and H2 to roughen the surface of the first semiconductor layer away from the substrate to form the concave-convex structure, wherein the flow rate of HCl is 10-800 sccm, the flow rate of H2 is 100-2000 sccm, and the passing time is 2-20 min; The step of growing a transition layer on a side of the first semiconductor layer away from the substrate comprises: Adding a surfactant, growing a first tensile stress providing layer on a side of the first semiconductor layer away from the substrate, with a growth temperature of 720-850° C. and a growth thickness of 30-1000 nm; Growing a barrier layer on a side of the first tensile stress-providing layer away from the substrate, with a growth temperature of 900-1000° C. and a growth thickness of 20-50 nm; At least one second tensile stress providing layer is grown on a side of the barrier layer away from the substrate; wherein the composition of the set element in the second tensile stress providing layer is less than the composition of the set element in the first tensile stress providing layer, and the composition of the set element in the second tensile stress providing layer is greater than or equal to the composition of the set element in the quantum well layer.

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