Quantum bit packaging device

Abstract

The invention relates to a quantum bit packaging device, and the device comprises a packaging pedestal, and a quantum chip is disposed in the packaging pedestal. The packaging cover plate is arranged on the base, and the packaging cover plate is used for sealing the packaging base; the connectors are uniformly distributed on the side wall of the packaging base according to a preset number; and the cable is vertically connected with the quantum chip in the packaging base through the cover plate. According to the quantum bit packaging device provided by the embodiment of the invention, the size of the packaging device and crosstalk between cables are reduced, and the packaging density is improved.

Description

Technical Field

[0001] The present application relates to the field of chip packaging technology, and in particular to a quantum bit packaging device. Background Art

[0002] Quantum technology, especially the research of quantum computers, has become an important frontier in global scientific research. Quantum computers use the principles of quantum mechanics to process information and calculate, and their core component is the quantum bit (qubit). Unlike the binary bits of traditional computers, quantum bits can be in multiple states at the same time. This quantum superposition and entanglement phenomenon provides quantum computers with great potential to surpass classical computers, especially in the fields of simulating complex physical systems, optimization problems, machine learning, etc.

[0003] The preparation of superconducting qubits usually requires the use of micro-nano processing technology to integrate them into superconducting circuits to form qubit chips. These chips are usually based on devices such as microwave resonators and superconducting circuits, and realize the transmission and processing of quantum information through integrated circuits. However, most proposals for large-scale quantum circuits are carried out in tiled two-dimensional lattices. Therefore, to achieve future scalability, it is necessary to transmit signals perpendicular to the plane of the two-dimensional circuit. Summary of the invention

[0004] In view of this, the present application proposes a quantum bit packaging device, which improves the packaging density by reducing the volume of the packaging device and the crosstalk between cables.

[0005] An embodiment of the present invention provides a quantum bit packaging device for packaging a quantum chip, comprising: a packaging base, in which the quantum chip is arranged; a packaging cover plate, which is arranged on the base and used to seal the packaging base; a connector, which is evenly distributed on the side wall of the packaging base according to a preset number; and a cable, which is vertically connected to the quantum chip in the packaging base through the cover plate.

[0006] In a possible implementation, the packaging base is a cylindrical structure, the outer wall of the packaging base is evenly provided with multiple through holes, threaded holes are symmetrically provided on both sides of the through holes, the through holes are used to plug the connector, and the threaded holes are used to fix the connector and the packaging base.

[0007] In a possible implementation manner, a groove is provided at the center of the packaging base, a square groove is provided in the groove, and the square groove is used to place the quantum chip.

[0008] In a possible implementation, a plurality of limit plates are evenly arranged on the outer periphery of the square groove, and a channel is formed between two adjacent limit plates. The plurality of channels correspond one to one to the through holes, and the channel is used to place the wiring of the PCB board. In the use state, the PCB board is bonded to the quantum chip with gold wires.

[0009] In a possible implementation, a plurality of threaded holes are disposed on the surface of the package base, and a plurality of through holes are disposed on the package cover plate. When the package cover plate and the package base are connected, the threaded holes and the through holes are threadedly connected in a one-to-one correspondence.

[0010] In a possible implementation manner, the package cover plate has a first plane, and a size of the first plane is the same as a peripheral size of the package base.

[0011] In a possible implementation, a plurality of cylinders are further provided on the packaging cover plate, and a plurality of grooves are correspondingly provided on the packaging base. The shapes of the plurality of cylinders are adapted to the shapes of the grooves. When the packaging cover plate and the packaging base are connected, the cylinders extend into the grooves for connection.

[0012] In a possible implementation, the package cover plate is further provided with a protrusion, a plurality of limiting plates are provided on the surface of the protrusion, channels are formed between adjacent limiting plates, and the channels are connected to the channels on the periphery of the quantum chip in a one-to-one correspondence.

[0013] In a possible implementation manner, a plurality of through holes are disposed at the center of the package cover plate, the diameter of the through holes matches the diameter of the cable, and the cable is welded to the through holes.

[0014] In a possible implementation, the cable extends through the through hole to above the surface of the quantum chip, the distance between the cable and the quantum chip is 0.9 mm, and an insertion hole is also provided on the periphery of the through hole, the insertion hole is used to fix a PIN needle, and the PIN needle is used to enhance the isolation between cables.

[0015] Beneficial effects of this application:

[0016] A quantum bit packaging device according to an embodiment of the present invention is connected via a packaging cover plate and a packaging base, the cables are arranged on the cover plate, the signal transmission line is short and straight, and the attenuation or error that may occur during signal transmission is reduced. The connector is arranged on the outer peripheral surface of the base, which optimizes the structural density of the packaging device, avoids signal distortion or short circuit problems that may occur in conventional packaging, effectively reduces the volume of the packaging device, reduces crosstalk between cables, and ensures efficient signal transmission.

[0017] Other features and aspects of the present application will become apparent from the following detailed description of exemplary embodiments with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the present application and, together with the description, serve to explain the principles of the present application.

[0019] Figure 1 A schematic diagram showing the structure of a quantum bit packaging device according to an embodiment of the present application;

[0020] Figure 2 A schematic diagram showing the disassembly of a quantum bit packaging device according to an embodiment of the present application;

[0021] Figure 3 A cross-sectional view showing a quantum bit packaging device according to an embodiment of the present application;

[0022] Figure 4 A schematic diagram showing a packaging base in a quantum bit packaging device according to an embodiment of the present application;

[0023] Figure 5 A front view of a packaging cover plate in a quantum bit packaging device according to an embodiment of the present application is shown;

[0024] Figure 6 A back view of a packaging cover plate in a quantum bit packaging device according to an embodiment of the present application is shown;

[0025] Figure 7 A schematic diagram showing a packaging cover plate plus PIN needles in a quantum bit packaging device according to an embodiment of the present application.

[0026] Reference numerals:

[0027] 1-package base; 101, 201, 202-through holes; 203, 204-insertion holes; 102, 105-threaded holes 106, 107-grooves; 103, 104, 208-square grooves;

[0028] 2-packaging cover plate; 205-first plane layer, 206-cylinder, 207-second plane layer;

[0029] 3-connector; 4-cable; 5-quantum chip; 6-PCB board; 7-PIN needle. DETAILED DESCRIPTION

[0030] Various exemplary embodiments, features and aspects of the present application will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0031] Among them, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application or simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0032] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0033] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0034] In addition, in order to better illustrate the present application, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present application can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present application.

[0035] Figure 1 A schematic diagram showing the structure of a quantum bit packaging device according to an embodiment of the present application; Figure 2 A schematic diagram showing the disassembly of a quantum bit packaging device according to an embodiment of the present application; Figure 3A cross-sectional view of a quantum bit packaging device according to an embodiment of the present application is shown; the embodiment of the present invention provides a quantum bit packaging device for packaging a quantum chip 5, including: a packaging base 1, in which the quantum chip 5 is arranged; a packaging cover plate 2, which is arranged on the base and used to seal the packaging base 1; a connector 3, which is evenly distributed on the side wall of the packaging base 1 according to a preset number; and a cable 4, which is vertically connected to the quantum chip 5 in the packaging base 1 through the cover plate. The cable 4 is arranged on the cover plate, and the signal transmission line is short and straight, which reduces the attenuation or error that may occur during the signal transmission process. The connector 3 is arranged on the outer peripheral surface of the packaging base 1, which optimizes the structural density of the packaging device, ensures the efficient communication between the quantum chip 5 and the external circuit, avoids the signal distortion or short circuit problems that may occur in conventional packaging, effectively reduces the volume of the packaging device, reduces the crosstalk between the cables 4, and ensures efficient signal transmission.

[0036] Specifically, the main body of the package base 1 is a cylindrical structure, a number of connectors 3 are connected to the side wall of the package base 1, a quantum chip 5 is arranged inside the package base 1, the package cover plate 2 is a circular plate, the package cover plate 2 is adapted to the opening of the package base 1, the package cover plate 2 is used to seal the package base 1, and the cable 4 is vertically connected to the quantum chip 5 inside the package base 1 through the package cover plate 2. In this embodiment, there are 22 connectors 3, which are arranged in the middle of the height direction of the package base 1. It should be noted that the specific number of connectors 3 can be determined according to needs and the performance of the packaged chip. Figure 4 A schematic diagram showing a packaging base 1 in a quantum bit packaging device according to an embodiment of the present application; Figure 5 A front view of a packaging cover plate 2 in a quantum bit packaging device according to an embodiment of the present application is shown; Figure 6 The back view of the package cover plate 2 in the quantum bit package device of the embodiment of the present application is shown; in a possible implementation, the package base 1 is a cylindrical structure, and the outer wall of the package base 1 is evenly provided with a plurality of through holes 101, and threaded holes 102 are symmetrically provided on both sides of the through holes 101, and the through holes 101 are used to plug the connector 3, and the threaded holes 102 are used to fix the connector 3 and the package base 1. A groove 107 is provided in the center of the package base 1, and a square groove 103 is provided in the groove 107, and the square groove 103 is used to place the quantum chip 5.

[0037] Specifically, the side wall of the package base 1 is provided with a circular through hole 101 and a circular threaded hole 102. The through hole 101 and the threaded hole 102 are used to place and fix the connector 3. The connector 3 is a through-wall SMA connector, and the connector 3 is threadedly connected to the package base 1. A cylindrical groove 107 is provided in the middle of the package base 1, and a square groove 103 is provided in the package base. The square groove 103 is located at the center of the package base and is used to place the chip 5. The size of the square groove 103 matches the size of the chip 5. A square groove 104 is provided around the square groove 103. The square groove 104 extends to the through hole 101 with the square groove 103 as the center, and is used to place the wiring of the PCB board 6. The PCB board 6 is welded and connected to the connector 3. The PCB board 6 is bonded with gold wires to the chip 5. The chip 5 is a superconducting quantum bit chip with a bit unit on the surface. A resonant cavity is also provided below the square groove 103. The resonant cavity is used to suppress the resonant frequency to a level outside the working frequency. The resonant cavity can effectively isolate and reduce the resonant frequencies that may appear in the system, avoiding the interference of these frequencies on the quantum chip or circuit. By pushing the resonant frequency outside the operating frequency, the resonant cavity can reduce the noise and instabilities caused by frequency resonance, enhancing the performance of sensitive electronic components such as quantum chips.

[0038] In a possible implementation, a plurality of limiting plates are evenly arranged on the periphery of the square groove 103, and a channel is formed between two adjacent limiting plates. The plurality of channels correspond to the through holes 101 one by one, and the channel is used to place the wiring of the PCB board 6. When in use, the PCB board 6 is gold-wire bonded to the quantum chip 5. The plurality of limiting plates surround the center of the package base 1 to form a square gap for placing the quantum chip 5, and a gap is left between two adjacent limiting plates to form a channel for placing the wiring of the PCB board 6.

[0039] In a possible implementation, a plurality of threaded holes 105 are provided on the surface of the package base, and a plurality of through holes 202 are provided on the package cover plate 2. When the package cover plate 2 and the package base 1 are connected, the threaded holes 105 and the through holes 202 are threadedly connected in a one-to-one correspondence. The package cover plate 2 has a first plane 205, and the size of the first plane 205 is the same as the outer circumferential size of the package base 1. A plurality of cylinders 206 are also provided on the package cover plate 2, and a plurality of grooves 106 are correspondingly provided on the package base 1. The shapes of the plurality of cylinders 206 are adapted to the shapes of the grooves 106. When the package cover plate 2 and the package base 1 are connected, the cylinders 206 extend into the grooves 106 for connection. The package cover plate 2 is also provided with a protrusion, and a plurality of limit plates are provided on the surface of the protrusion. A channel is formed between adjacent limit plates, and the channel is connected in a one-to-one correspondence with the channel on the periphery of the quantum chip 5. The package cover plate 2 and the package base 1 have the same diameter. The package base 1 is provided with a plurality of threaded holes 105, which correspond one to one with the through holes 202. When the package cover plate 2 and the package base 1 are connected, the threaded holes 105 are threadedly connected with the through holes 202. At the same time, the package cover plate 2 is also provided with a plurality of cylinders 206, and the package base 1 is correspondingly provided with a plurality of grooves 106. The cylinders 206 extend into the grooves 106 for connection, so as to further seal the package cover plate 2 and the package base 1.

[0040] Specifically, Figure 4 and Figure 7 As shown, the middle part of the encapsulation base 1 is an annular hollow structure, and there is also a quantum chip 5 support seat at the bottom, and a groove is arranged in the middle part of the support seat, and the area of ​​the groove is smaller than the area of ​​the quantum chip 5 to be packaged. The support seat shown is provided with a plurality of limit plates on the upper surface around the groove, and a channel is formed between two adjacent limit plates, and the number of channels is the same as the number of connectors 3, and the connector 3 passes through the channel to communicate with the quantum chip 5 packaged inside. It should also be noted that in this embodiment, a plurality of limit plates form a rectangular structure placement table at the inner edge in the direction toward the center, and the rectangular structure placement table matches the quantum chip 5 to be packaged. And the groove arranged in the middle part of the support seat is in the middle part of the rectangular placement table. It should be noted that the shape of the placement table is consistent with the shape of the quantum chip 5 to be packaged. When the quantum chip 5 to be placed is of other shapes, the shape of the placement table is also a corresponding shape, which can accurately place the quantum chip 5 to be packaged.

[0041] Furthermore, in one embodiment, a second limiting plate structure matching the limiting plate of the support seat is also provided on the top surface facing the packaging base 1. It should be noted that the second limiting plate and the limiting plate structure on the support seat are in exactly the same position. Preferably, as a feasible implementation method, the first limiting plate and the second limiting plate are in exactly the same position, but the first limiting plate and the second limiting plate can be configured as structures that mesh with each other. As shown in the figure, the first limiting plate is composed of two parts, one high and one low, and the second limiting plate is also composed of two parts, one high and one low. The height positions of the two limiting plates are just opposite, forming a matching combination. After buckling, they fit together to form a through-hole structure with only the side matching the connector 3.

[0042] In a possible implementation, a plurality of through holes 203 are provided in the center of the package cover plate, the diameter of the through hole 203 matches the diameter of the cable 4, and the cable 4 is welded to the through hole 203. The cable 4 extends through the through hole 203 to above the surface of the quantum chip 5, the distance between the cable 4 and the quantum chip 5 is 0.9 mm, and an insertion hole is also provided on the periphery of the through hole 203, the insertion hole is used to fix the PIN needle 7, and the PIN needle 7 is used to enhance the isolation between the cables 4. The distance between the cable 4 and the quantum chip 5 provides sufficient space for gold wire bonding. During the gold wire bonding process, the relative position of the quantum chip 5 and the cable 4 can be fine-tuned to ensure the precise alignment of the connection point, thereby improving the stability and reliability of the connection. Appropriate gaps can reduce heat transfer and mechanical stress between the quantum chip 5 and the cable 4, reduce the impact of thermal expansion on the connection point, and enhance the stability of the system under high temperature or long-term working conditions.

[0043] Specifically, a threaded hole 105 is provided on the upper wall of the packaging base 1, and a through hole 202 is provided on the packaging cover plate 2. The packaging cover plate 2 is threadedly connected to the packaging base 1, and the threaded hole 105 is arranged corresponding to the position of the through hole 201. The packaging cover plate 2 is provided with a first plane 205, and the outer size of the first plane 205 is arranged corresponding to the outer size of the outer size of the packaging base 1. A cylinder 206 is provided on the bottom surface of the packaging cover plate 2, and the cylinder 206 is arranged corresponding to the circular groove 106 for fixing the installation position of the packaging cover plate 2 and the packaging base 1. A protruding cylindrical second plane 207 is provided on the lower wall of the packaging cover plate 2, and the cylinder 207 is installed in the groove 107. The size of the cylinder 207 matches the groove 107. A square groove 208 is provided at the bottom of the packaging cover plate 2, and the square groove 208 is arranged corresponding to the square groove 104. A plurality of through holes 203 are arranged in the middle of the package cover plate 2. The diameter of the through hole 203 matches the diameter of the cable 4. The cable 4 is welded to the through hole 203. The inner conductor of the cable 4 extends to 0.9 mm above the chip surface through the through hole 203 to form a waveguide cavity. Signal transmission is performed by air coupling. Insertion holes 204 are arranged around the through hole 203. The insertion hole 204 is used to install and fix the PIN needle 7. The size of the PIN needle matches the size of the insertion hole to enhance the isolation between cables. The number of plug-in holes is 4. When the PIN needle 7 and the insertion hole are plugged in, the PIN needle 7 is inserted into the insertion hole one by one, and multiple PIN needles 7 are parallel to each other. The PIN needle 7 helps to evenly distribute the current and signal, reduce the possibility of electromagnetic interference and signal reflection, and optimize the transmission quality of the signal. There are 4 PIN needles 7 on the side of a cable. The PIN needle 7 is used to form a Faraday cage to enhance the isolation between cables.

[0044] In one possible implementation, the packaging base 1 and the packaging cover 2 are made of oxygen-free copper. The oxygen-free copper material used allows the quantum chip 5 packaging to maintain good performance even in an ultra-low temperature environment, further improving the high integration and high thermal conductivity of the quantum chip 5, and ensuring efficient quantum bit signal transmission.

[0045] The embodiments of the present application have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to the technology in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A quantum bit packaging device for packaging quantum chips, characterized in that: include: A packaging base, wherein the quantum chip is arranged in the packaging base; A packaging cover plate, the packaging cover plate is arranged on the base, and the packaging cover plate is used to seal the packaging base; Connectors, wherein the connectors are evenly distributed on the side wall of the packaging base according to a preset number; A cable is vertically connected to the quantum chip in the packaging base through the cover plate.

2. The quantum bit packaging device according to claim 1, characterized in that: The packaging base is a cylindrical structure, and a plurality of through holes are evenly arranged on the outer wall of the packaging base. Threaded holes are symmetrically arranged on both sides of the through holes. The through holes are used to plug the connectors, and the threaded holes are used to fix the connector and the packaging base.

3. The quantum bit packaging device according to claim 2, characterized in that: A groove is arranged at the center of the packaging base, a square groove is arranged in the groove, and the square groove is used to place the quantum chip.

4. The quantum bit packaging device according to claim 3, characterized in that: A plurality of limit plates are evenly arranged on the outer periphery of the square groove, and a channel is formed between two adjacent limit plates. The plurality of channels correspond to the through holes one by one, and the channel is used to place the wiring of the PCB board. In the use state, the PCB board is bonded to the quantum chip with gold wires.

5. The quantum bit packaging device according to claim 1, characterized in that: A plurality of threaded holes are arranged on the surface of the package base, and a plurality of through holes are arranged on the package cover plate. When the package cover plate and the package base are connected, the threaded holes and the through holes are threadedly connected in a one-to-one correspondence.

6. The quantum bit packaging device according to claim 4, characterized in that: The package cover has a first plane, and a size of the first plane is the same as a peripheral size of the package base.

7. The quantum bit packaging device according to claim 6, characterized in that: The packaging cover plate is also provided with a plurality of cylinders, and the packaging base is correspondingly provided with a plurality of grooves, and the shapes of the plurality of cylinders are adapted to the shapes of the grooves. When the packaging cover plate and the packaging base are connected, the cylinders extend into the grooves for connection.

8. The quantum bit packaging device according to claim 7, characterized in that: The packaging cover plate is also provided with a protrusion, and a plurality of limiting plates are provided on the surface of the protrusion, and channels are formed between adjacent limiting plates, and the channels are connected with the channels on the periphery of the quantum chip in a one-to-one correspondence.

9. The quantum bit packaging device according to claim 1, characterized in that: A plurality of through holes are arranged at the center of the packaging cover plate, the diameter of the through holes matches the diameter of the cables, and the cables are welded to the through holes.

10. The quantum bit packaging device according to claim 1, characterized in that: The cable extends through the through hole to above the surface of the quantum chip, the distance between the cable and the quantum chip is 0.9 mm, and an insertion hole is also provided on the periphery of the through hole, the insertion hole is used to fix a PIN needle, and the PIN needle is used to enhance the isolation between cables.

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