Array substrate and display panel

Abstract

The application discloses an array substrate and a display panel, and relates to the technical field of display. The side of the row driving area of the array substrate is designed with a plurality of first patterns, so that sufficient etching liquid is ensured to etch the source and the drain of the thin film transistor of the row driving area and the display area, and then the material residue of the source and the drain film layer caused by the insufficient etching liquid of the row driving area and the display area is avoided, the channel of the thin film transistor is prevented from being turned on due to the material residue of the source and the drain film layer above the active layer, the active layer of the thin film transistor is prevented from being conductorized, the characteristics of the thin film transistor are ensured, and the yield of the array substrate and the display effect of the display panel are improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Technology

[0002] Thin film transistors (TFTs) are widely used in flexible display panels due to their advantages such as fewer processing steps, high mobility, good bending performance, and low processing temperature.

[0003] In related technologies, thin-film transistors include: a gate, a gate insulating layer, an active layer, and a source-drain layer sequentially stacked along a direction away from the substrate. The source-drain layer includes a source and a drain disposed at intervals.

[0004] However, because the active layer of thin-film transistors is prone to becoming conductive during the fabrication process, it can easily lead to abnormal characteristics of the thin-film transistors, resulting in a low yield of the array substrate and poor display performance of the display panel. Summary of the Invention

[0005] This application provides an array substrate and a display panel, which can solve the problems of low yield of array substrates and poor display effect of display panels in related technologies. The technical solution is as follows:

[0006] On one hand, an array substrate is provided, the array substrate comprising:

[0007] A substrate having a display area and a peripheral area surrounding the display area, the peripheral area including at least a row driving area extending along a first direction;

[0008] Multiple thin-film transistors are disposed within the row driving region;

[0009] In addition, a plurality of first patterns, the plurality of first patterns being located at least on one side of the row driving region, and the plurality of first patterns being spaced apart from the row driving region along the first direction, and the plurality of first patterns being arranged in an array on the same side of the row driving region;

[0010] The thin-film transistor includes: a gate, a gate insulating layer, an active layer, and a source-drain layer sequentially stacked along a direction away from the substrate, wherein the source-drain layer includes a source and a drain disposed at intervals; and the plurality of first patterns are located in the same layer as at least one of the source and the drain.

[0011] Optionally, the shape of the orthographic projection of the first pattern onto the substrate is rectangular.

[0012] Optionally, the shape of the orthographic projection of the first pattern onto the substrate is a square.

[0013] Optionally, in the first pattern, one of the two perpendicular boundaries is parallel to the first direction, and the other boundary is parallel to the second direction;

[0014] The second direction is parallel to the arrangement direction of the display area and the row driving area, and the first direction and the second direction intersect.

[0015] Optionally, the length of the first pattern along the first direction is m1, the distance between any two adjacent first patterns along the first direction is n1, and the ratio of m1 / n1 ranges from 0.9 to 1.9; the length of the first pattern along the second direction is m2, the distance between any two adjacent first patterns along the second direction is n2, and the ratio of m2 / n2 ranges from 0.9 to 1.9.

[0016] Optionally, the minimum distance between the orthographic projection of the plurality of first patterns on the substrate and the orthographic projection of other structures in the array substrate on the substrate ranges from 15 micrometers to 30 micrometers.

[0017] Optionally, the peripheral area includes two row driving areas extending along the first direction, and the two row driving areas are respectively located on both sides of the display area;

[0018] The plurality of first patterns are located on both sides of each of the row driving regions.

[0019] Optionally, the peripheral region further includes a fan-out region extending along a second direction, the second direction being parallel to the arrangement direction of the row driving region and the display region; the array substrate further includes:

[0020] A plurality of second patterns, wherein the plurality of second patterns are located at least on one side of the fan-out region and are spaced apart from the fan-out region along the second direction, and an array of the plurality of second patterns located on the same side of the fan-out region is arranged, wherein the second patterns are different from at least one of the shape and size of the first pattern;

[0021] The plurality of second patterns include: a plurality of first-type second patterns and a plurality of second-type second patterns, wherein the plurality of first-type second patterns are located on the same layer as the gate, and the plurality of second-type second patterns are located on the same layer as the source and the drain.

[0022] Optionally, the orthographic projections of the plurality of first-type second patterns on the substrate do not overlap with the orthographic projections of the plurality of second-type second patterns on the substrate.

[0023] Optionally, the orthographic projections of the plurality of first-type second patterns on the substrate and the orthographic projections of the plurality of second-type second patterns on the substrate are staggered in the second direction.

[0024] Optionally, the number of the plurality of first-type second patterns is the same as the number of the plurality of second-type second patterns, and they correspond one-to-one;

[0025] The orthographic projection of each of the first type of second patterns on the substrate overlaps with the orthographic projection of the corresponding second type of second pattern on the substrate.

[0026] Optionally, the shape of the orthographic projection of the second pattern on the substrate is rectangular, and the length of the second pattern along the first direction is greater than the length along the second direction.

[0027] Optionally, one of the two perpendicular boundaries in the second pattern is parallel to the first direction, and the other boundary is parallel to the second direction.

[0028] Optionally, the length of the second pattern along the first direction is r1, the distance between any two adjacent second patterns along the first direction is s1, and the ratio of r1 / s1 ranges from 0.9 to 1.9.

[0029] The length of the second pattern along the second direction is r2, the distance between any two adjacent second patterns along the second direction is s2, and the ratio of r2 / s2 ranges from 0.9 to 1.9.

[0030] Optionally, the minimum distance between the orthographic projection of the second pattern on the substrate and the orthographic projection of other structures in the array substrate on the substrate ranges from 75 micrometers to 100 micrometers.

[0031] Optionally, the plurality of second patterns are located on both sides of the fan-out region.

[0032] Optionally, the multiple thin-film transistors located in the row driving region constitute multiple cascaded shift register units, each of the shift register units including 18 thin-film transistors and a storage capacitor.

[0033] Optionally, the active layer of the thin-film transistor is a metal oxide material.

[0034] On the other hand, a display panel is provided, the display panel including a plurality of pixel units and an array substrate as described above;

[0035] The plurality of pixel units are located in the display area of ​​the array substrate.

[0036] The beneficial effects of the technical solution provided in this application include at least the following:

[0037] This application provides an array substrate and a display panel. The array substrate has multiple first patterns designed on one side of the row driving region to ensure sufficient etching solution to etch the source and drain of the thin-film transistors forming the row driving region and the display region. This avoids material residue in the source and drain film layers due to insufficient etching solution in the row driving region and the display region, prevents the channel of the thin-film transistor from being turned on due to the material of the source and drain film layers remaining above the active layer, and prevents the active layer of the thin-film transistor from being conductive. This ensures the characteristics of the thin-film transistor, improves the yield of the array substrate and the display effect of the display panel. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. This application uses an oxide thin-film transistor as an example for illustration.

[0039] Figure 1 This is a graph showing the relationship between resistance and voltage of a thin-film transistor before and after the active layer is conductive, according to an embodiment of this application.

[0040] Figure 2 This is a schematic diagram illustrating the display effect after the active layer of a thin-film transistor in an array substrate is conductive, according to an embodiment of this application.

[0041] Figure 3 This is a schematic diagram of the structure of an array substrate provided in an embodiment of this application;

[0042] Figure 4 This is a top view of a substrate provided in an embodiment of this application;

[0043] Figure 5 The array substrate provided in the embodiments of this application is in Figure 4 A partial schematic diagram of region A in the middle;

[0044] Figure 6 This is a schematic diagram of the structure of a thin-film transistor provided in an embodiment of this application;

[0045] Figure 7 This is a top view of a first pattern provided in an embodiment of this application;

[0046] Figure 8 The array substrate provided in the embodiments of this application is in Figure 4 A partial schematic diagram of region B in the middle;

[0047] Figure 9 The array substrate provided in the embodiments of this application is in Figure 4 A partial schematic diagram of region C;

[0048] Figure 10 yes Figure 9 Schematic diagram of the cross section along the DD direction;

[0049] Figure 11 yes Figure 9 Cross-sectional scanning electron microscope (SEM) image along the DD direction;

[0050] Figure 12 This is a cross-sectional schematic diagram of a second pattern provided in an embodiment of this application;

[0051] Figure 13 This is a top view of a second pattern provided in an embodiment of this application;

[0052] Figure 14 This is a circuit structure diagram of a shift register unit provided in an embodiment of this application;

[0053] Figure 15 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application;

[0054] Figure 16 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Detailed Implementation

[0055] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0056] The process steps for oxide thin-film transistors (OSTs) are far fewer than those for low-temperature polycrystalline silicon (LTSi) thin-film transistors (LTSis), and the mobility of OSTs is significantly higher than that of amorphous silicon (ASiSis). OSTs also exhibit good bending performance and require lower processing temperatures, making them suitable for fabricating flexible substrates. Therefore, OSTs hold great promise for future applications in flexible displays.

[0057] However, compared to amorphous silicon thin-film transistors (TFTs), oxide thin-film transistors are more prone to conductor formation during the fabrication of the array substrate. This can cause abnormal characteristics in oxide TFTs, leading to display defects and significantly impacting the yield and low-cost advantages of oxide display panels. Oxide display panels can be used to indicate that the thin-film transistors in the display panel are oxide thin-film transistors.

[0058] Testing revealed that in oxide display panels, a large blank area on one side of the horizontal drive region makes the active layer of the thin-film transistors in the horizontal drive region prone to becoming conductive. (Reference) Figure 1 Before the active layer of a certain thin-film transistor is conductive, its resistance is 10 ohms. 10 The resistance is Ω (ohms), and it gradually decreases as the voltage increases until the thin-film transistor turns on. However, after the active layer of the thin-film transistor is made conductive, the resistance becomes 10 Ω. 4 Ω, the resistance does not change with increasing voltage, thus causing the thin-film transistor to fail. Therefore, refer to... Figure 2 The display panel has poor display quality, with horizontal lines appearing (weak dark lines appear every four rows).

[0059] in, Figure 1 1.00E+01 is used to represent 10 1 1.00E+02 is used to represent 10 2 1.00E+3 is used to represent 10 3 And so on, without going into further detail.

[0060] Figure 3 This is a schematic diagram of an array substrate provided in an embodiment of this application. (Reference) Figure 3 As can be seen, the array substrate 10 may include a substrate 101, a plurality of thin-film transistors 102 and a plurality of first patterns 103.

[0061] Figure 4 This is a top view of a substrate provided in an embodiment of this application. (Reference) Figure 3 and Figure 4 The substrate 101 also has a display area 101a and a peripheral area 101b surrounding the display area 101a. The peripheral area 101b includes at least a row driving area 101b1 extending along a first direction X. A thin-film transistor 102 is located at least in the row driving area 101b1. Of course, the thin-film transistor 102 may also be located in the display area 101a.

[0062] The thin-film transistor 102 located in the row driving region 101b1 can constitute the array substrate row driving (gate driven on array, GOA) circuit of the array substrate 10. The thin-film transistor 102 located in the display region 101a can constitute the driving circuit in the array substrate 10 for driving the light-emitting unit to emit light.

[0063] Figure 5 The array substrate provided in the embodiments of this application is in Figure 4 A partial schematic diagram of region A in the middle. (Combined with...) Figure 4 and Figure 5Multiple first patterns 103 are located at least on one side of the row driving region 101b1, and the multiple first patterns 103 are arranged at intervals along the first direction X with the row driving region 101b1, and the multiple first patterns 103 on the same side of the row driving region 101b1 are arranged in an array.

[0064] Figure 6 This is a schematic diagram of a thin-film transistor provided in an embodiment of this application. (Reference) Figure 6 The thin-film transistor 102 includes a gate 1021, a gate insulating layer 1022, an active layer 1023, and a source-drain layer 1024, sequentially stacked along a direction away from the substrate 101. The source-drain layer 1024 includes a source electrode 10241 and a drain electrode 10242 spaced apart. A plurality of first patterns 103 included in the array substrate 10 are located in the same layer as at least one of the source electrode 10241 and the drain electrode 10242 of the thin-film transistor 102. The phrase "a plurality of first patterns 103 are located in the same layer as at least one of the source electrode 10241 and the drain electrode 10242" can mean that the plurality of first patterns 103 are made of the same material and fabricated by the same patterning process as at least one of the source electrode 10241 and the drain electrode 10242. Typically, the source electrode 10241 and the drain electrode 10242 are made of the same material and fabricated by the same patterning process.

[0065] In the array substrate 10, there is usually a large blank area (i.e., an area where no traces and thin film transistors are set) on one side of the row driving region 101b1. Therefore, designing multiple first patterns 103 on one side of the row driving region 101b1 can reduce the consumption of etching solution when etching the source and drain film layers to form the source 10241 and drain 10242 of the thin film transistor 102. This avoids consuming large amounts of etching solution due to large-area etching, ensuring sufficient etching solution to etch the source 10241 and drain 10242 of the thin-film transistor 102 forming the row driving region 101b1 and the display region 101a. This also avoids material residue in the source and drain film layers due to insufficient etching solution in the row driving region 101b1 and the display region 101a, prevents the channel of the thin-film transistor 102 from being turned on by the material of the source and drain film remaining above the active layer 1023, and prevents the active layer 1023 of the thin-film transistor 102 from becoming conductive. This ensures the characteristics of the thin-film transistor 102, improves the yield of the array substrate 10 and the display effect of the display panel.

[0066] Furthermore, designing multiple first patterns 103 on one side of the horizontal driving region 101b1 can improve the uniformity of the source and drain film layer pattern on one side of the horizontal driving region 101b1 with the source and drain film layer pattern above the active layer in the display area.

[0067] In summary, the embodiments of this application provide an array substrate. One side of the row driving region of the array substrate is designed with multiple first patterns to ensure sufficient etching solution to etch the source and drain electrodes of the thin-film transistors forming the row driving region and the display region. This avoids material residue in the source and drain film layers due to insufficient etching solution in the row driving region and the display region, prevents the channels of the thin-film transistors from becoming conductive due to material residue in the source and drain film layers above the active layer, and prevents the active layer of the thin-film transistors from becoming conductive. This ensures the characteristics of the thin-film transistors, improves the yield of the array substrate, and enhances the display effect of the display panel.

[0068] In related technologies, to avoid the effects of static electricity, an electrostatic discharge (ESD) unit is designed on one side of the horizontal driving region 101b1. This application removes the ESD unit in this region and designs multiple first patterns 103, placing the ESD unit in the peripheral region 101b above the display region 101a (located on the side of the display region 101a away from the fan-out region 101b2). For example, removing the ESD unit can be used to adjust the mask without increasing the mask cost or process complexity.

[0069] In this embodiment, the active layer of the thin-film transistor 102 can be a metal oxide material. That is, the thin-film transistor 102 can be an oxide thin-film transistor.

[0070] In this embodiment, the source / drain electrode film may include a first film layer, a second film layer, and a third film layer stacked sequentially. The materials of the first and third film layers may be molybdenum-niobium alloy (MoNb), and the material of the second film layer may be copper (Cu). That is, the source / drain electrode film layer may be a MoNb / Cu / MoNb stacked structure.

[0071] Optionally, the orthographic projection of the first pattern 103 onto the substrate 101 is rectangular. This rectangle can be a right-angled rectangle, a chamfered rectangle, or a rounded rectangle. For example, the orthographic projection of the first pattern 103 onto the substrate 101 is square. That is, the orthographic projection of the first pattern 103 onto the substrate 101 includes at least two vertical boundaries of equal length.

[0072] refer to Figure 5 It can be seen that in the first pattern 103, one of the two perpendicular boundaries is parallel to the first direction X, and the other boundary is parallel to the second direction Y. The second direction Y is parallel to the arrangement direction of the display area 101a and the row driving area 101b1. The first direction X and the second direction Y intersect, for example, perpendicularly. Multiple first patterns 103 are arranged in an array along the first direction X and the second direction Y.

[0073] Optional, see reference Figure 7 The length of the first pattern 103 along the first direction X is m1, and the distance between any two adjacent first patterns 103 along the first direction X is n1, with the ratio of m1 / n1 ranging from 0.9 to 1.9. The length of the first pattern 103 along the second direction Y is m2, and the distance between any two adjacent first patterns 103 along the second direction Y is n2, with the ratio of m2 / n2 ranging from 0.9 to 1.9.

[0074] For example, the length m1 of the first pattern 103 along the first direction X and the length m2 along the second direction Y are both between 12 μm and 15 μm. The distance n1 between any two adjacent first patterns 103 along the first direction X and the distance n2 between any two adjacent first patterns 103 along the second direction Y are both between 8 μm and 13 μm. (Reference) Figure 7 The shape of the orthographic projection of the first pattern 103 on the substrate 101 can be a rectangle with chamfered corners at the four corners, that is, the shape of the orthographic projection of the first pattern 103 on the substrate 101 is a chamfered rectangle.

[0075] Optionally, the minimum distance between the orthographic projections of the plurality of first patterns 103 on the substrate 101 and the orthographic projections of other structures in the array substrate 10 on the substrate 101 ranges from 15 μm to 30 μm. That is, the distance between the plurality of first patterns 103 and other structures in the array substrate 10 can be relatively large to avoid the plurality of first patterns 103 affecting other structures in the array substrate 10. These other structures can be traces used for signal transmission in the array substrate 10, or thin-film transistors.

[0076] refer to Figure 3 and Figure 4 The peripheral area 101b may include two line driving areas 101b1 extending along the first direction X, and the two line driving areas 101b1 are respectively located on both sides of the display area 101a. A plurality of first patterns 103 are located on both sides of each line driving area 101b1. That is, the plurality of first patterns 103 may include a plurality of first patterns 103 located in a first area, a plurality of first patterns 103 located in a second area, a plurality of first patterns 103 located in a third area, and a plurality of first patterns 103 located in a fourth area. For example, refer to... Figure 8 The plurality of first pattern 103 arrays located in the first region are arranged in the upper left corner region of the substrate 101. In addition, the plurality of first pattern 103 arrays located in the second region are arranged in the lower left corner region of the substrate 101, the plurality of first pattern 103 arrays located in the third region are arranged in the upper right corner region of the substrate 101, and the plurality of first pattern 103 arrays located in the fourth region are arranged in the lower right corner region of the substrate 101.

[0077] refer to Figure 4 It can be seen that the surrounding area 101b may also include a fan-out area 101b2 extending along the second direction Y. Figure 9 The array substrate provided in the embodiments of this application is in Figure 4 A partial schematic diagram of region C. (Reference) Figure 4 and Figure 9 The array substrate 10 further includes a plurality of second patterns 104. The plurality of second patterns 104 are located at least on one side of the fan-out region 101b2, and are arranged at intervals along the second direction Y with respect to the fan-out region 101b2, with the plurality of second patterns 104 located on the same side of the fan-out region 101b2 arranged in an array. The second pattern 104 differs from at least one of the shape and size of the first pattern 103. Optionally, the shape of the orthographic projection of the second pattern 104 onto the substrate 101 can be rectangular.

[0078] Figure 10 yes Figure 9 Cross-sectional view along the DD direction. Figure 11 yes Figure 9 Schematic diagram of an electron microscope along the DD direction. (Reference) Figure 10 and Figure 11 The plurality of second patterns 104 include: a plurality of first-type second patterns 104a and a plurality of second-type second patterns 104b. The plurality of first-type second patterns 104a are located on the same layer as the gate 1021, and the plurality of second-type second patterns 104b are located on the same layer as the source 10241 and the drain 10242.

[0079] The phrase "multiple first-type second patterns 104a and gate 1021 located in the same layer" can mean that the multiple first-type second patterns 104a and gate 1021 are made of the same material and fabricated by the same patterning process. Similarly, "multiple second-type second patterns 104b and source 10241 and drain 10242 located in the same layer" can mean that the multiple second-type second patterns 104b and source 10241 and drain 10242 are made of the same material and fabricated by the same patterning process.

[0080] In this embodiment, multiple second patterns 104 are designed in the fan-out region 101b2, which can also reduce the consumption of etching solution, thereby avoiding material residue in the source and drain film layers due to insufficient etching solution in the row driving region 101b1 and the display region 101a. This prevents the channel of the thin film transistor 102 from being turned on due to the material of the source and drain film layers remaining above the active layer 1023, and prevents the active layer 1023 of the thin film transistor 102 from being conductive, thus ensuring the characteristics of the thin film transistor 102 and improving the display effect and yield of the array substrate.

[0081] Furthermore, the fan-out region 101b2 of the array substrate 10 is typically designed with multiple signal lines, and at least one segment of at least one signal line can be located on the same layer as the gate 1021, while another segment is located on the same layer as the source 10241 and drain 10242. Therefore, by ensuring that multiple first-type second patterns 104a and multiple second-type second patterns 104b of the multiple second patterns 104 are located on the same layer as the gate 1021 and the source 10241 (or drain 10242), respectively, it can be ensured that the design of the multiple second patterns 104 has good pattern uniformity with the design of the patterns (signal lines) in the fan-out region 101b2, thereby improving the yield of the array substrate 10.

[0082] refer to Figure 10 The orthographic projections of multiple first-type second patterns 104a on the substrate 101 do not overlap with the orthographic projections of multiple second-type second patterns 104b on the substrate 101, which can avoid mutual interference between the multiple first-type second patterns 104a and the multiple second-type second patterns 104b and ensure the yield of the array substrate 10.

[0083] Optional, see reference Figure 10 The orthographic projections of multiple first-type second patterns 104a on the substrate 101 and the orthographic projections of multiple second-type second patterns 104b on the substrate 101 are staggered in the second direction Y.

[0084] Optional, see reference Figure 11 The angle α between the connecting line between the first type of second pattern 104a and the second type of second pattern 104b closest to the first type of second pattern 104a and the bearing surface of the substrate 101 can range from 25 degrees to 60 degrees.

[0085] In addition, the angle β between the boundary slope of each second pattern 104 and the bearing surface of the substrate 101 ranges from 25 degrees to 60 degrees.

[0086] Or, refer to Figure 12 The number of multiple first-type second patterns 104a and multiple second-type second patterns 104b are the same and correspond one-to-one. The orthographic projection of each first-type second pattern 104a on the substrate 101 overlaps with the orthographic projection of the corresponding second-type second pattern 104b on the substrate 101.

[0087] In this embodiment, the orthographic projection of the second pattern 104 onto the substrate 101 is rectangular, and the length of the second pattern 104 along the first direction X can be greater than the length along the second direction Y. For example, the second pattern 104 can be a strip structure extending along the first direction X.

[0088] Optionally, one of the two vertical boundaries of the first pattern 103 is parallel to the first direction X, and the other boundary is parallel to the second direction Y. The second direction Y is parallel to the arrangement direction of the display area 101a and the row driving area 101b1. That is, multiple first patterns 103 are arranged in an array along the first direction X and the second direction Y.

[0089] Optional, see reference Figure 13 The length of the second pattern 104 along the first direction X is r1, and the distance between any two adjacent second patterns 104 along the first direction X is s1, with the ratio of r1 / s1 ranging from 0.9 to 1.9. The length of the second pattern 104 along the second direction X is r2, and the distance between any two adjacent second patterns 102 along the second direction Y is s2, with the ratio of r2 / s2 ranging from 0.9 to 1.9.

[0090] Optionally, the length r1 of the second pattern 104 along the first direction X ranges from 50 μm to 100 μm, and the length r2 of the second pattern 104 along the second direction Y ranges from 2 μm to 10 μm. The length r1 of the second pattern 104 along the first direction X is not too large (the second pattern 104 can be a short rod-shaped structure), which can avoid charge accumulation at the second pattern 104 due to its excessive length, thus avoiding the risk of electrostatic discharge.

[0091] In addition, the distance s1 between any two adjacent second patterns 104 along the first direction X ranges from 50 μm to 100 μm, and the distance s2 between any two adjacent second patterns 104 along the second direction Y ranges from 3 μm to 10 μm.

[0092] refer to Figure 13 The shape of the orthographic projection of the second pattern 104 onto the substrate 101 can be a rectangle with chamfered corners at the four corners, that is, the shape of the orthographic projection of the second pattern 104 onto the substrate 101 can be a chamfered rectangle.

[0093] Optionally, the minimum distance between the orthographic projections of the plurality of second patterns 104 on the substrate 101 and the orthographic projections of other structures in the array substrate 10 on the substrate 101 ranges from 75 μm to 100 μm. That is, the distance between the plurality of second patterns 104 and other structures in the array substrate 10 can be relatively large to avoid the plurality of second patterns 104 affecting other structures in the array substrate 10. These other structures can be traces used for signal transmission in the array substrate 10, or thin-film transistors.

[0094] In this embodiment, a plurality of second patterns 104 may be located on both sides of the fan-out region 101b2. For example, the plurality of second patterns 104 may include a plurality of second patterns 104 located in a fifth region and a plurality of second patterns 104 located in a sixth region. The fifth region and the sixth region are respectively located on both sides of the fan-out region 101b2.

[0095] In this embodiment, the multiple thin-film transistors 102 located in the row driving region 101b1 can form multiple cascaded shift register units. Each shift register unit may include 18 thin-film transistors 102 and a storage capacitor. Of course, the shift register unit can also have other structures, and this embodiment does not limit them.

[0096] Figure 14 This is a circuit structure diagram of a shift register unit provided in an embodiment of this application. (Reference) Figure 14 It can be seen that the shift register unit 01 may include: an input circuit 011, a first reset circuit 012, an output circuit 013, a second reset circuit 014, a first pull control circuit 015, a first pull circuit 016, a second pull control circuit 017, a second pull circuit 018, and a storage capacitor C.

[0097] The input circuit 011 includes: a first transistor M1, the gate and first terminal of the first transistor M1 are connected to the signal input terminal INPUT, and the second terminal of the first transistor M1 is connected to the pull-up node PU.

[0098] The first reset circuit 012 includes a second transistor M2 and a third transistor M4. The gate of the second transistor M2 is connected to the first reset signal terminal RES1, the first terminal of the second transistor M2 is connected to the pull-up node PU, and the second terminal of the second transistor M2 is connected to the first fixed voltage terminal LVGL. The gate of the third transistor M4 is connected to the first reset signal terminal RES1, the first terminal of the third transistor M4 is connected to the first signal output terminal OUT1, and the second terminal of the third transistor M4 is connected to the second fixed voltage terminal VGL.

[0099] Output circuit 013 includes: a first output transistor M3 and a second output transistor M11. The gate of the first output transistor M3 is connected to the pull-up node PU, the first terminal of the first output transistor M3 is connected to the clock signal terminal CLK, and the second terminal of the first output transistor M3 is connected to the first signal output terminal OUT1. The gate of the second output transistor M11 is connected to the pull-up node PU, the first terminal of the second output transistor M11 is connected to the clock signal terminal CLK, and the second terminal of the second output transistor M11 is connected to the second signal output terminal OUT2.

[0100] The second reset circuit 014 includes: a fourth transistor M15, the gate of the fourth transistor M15 is connected to the second reset signal terminal RES2, the first terminal of the fourth transistor M15 is connected to the pull-up node PU, and the second terminal of the fourth transistor M15 is connected to the first fixed voltage terminal LVGL.

[0101] The first pull-up control circuit 015 includes: a fifth transistor M5A, a sixth transistor M6A, and a seventh transistor M7A. The gate and first terminal of the fifth transistor M5A are connected to the first control terminal VDDo, and the second terminal of the fifth transistor M5A is connected to the first pull-down node PD1. The gate of the sixth transistor M6A is connected to the pull-up node PU, the first terminal of the sixth transistor M6A is connected to the first pull-down node PD1, and the second terminal of the sixth transistor M6A is connected to the first fixed voltage terminal LVGL. The gate of the seventh transistor M7A is connected to the signal input terminal INPUT, the first terminal of the seventh transistor M7A is connected to the first pull-down node PD1, and the second terminal of the seventh transistor M7A is connected to the first fixed voltage terminal LVGL.

[0102] The first pull-up circuit 016 includes: an eighth transistor M8A, a ninth transistor M12A, and a tenth transistor M13A. The gate of the eighth transistor M8A is connected to the first pull-down node PD1, its first terminal is connected to the pull-up node PU, and its second terminal is connected to the first fixed voltage terminal LVGL. The gate of the ninth transistor M12A is connected to the first pull-down node PD1, its first terminal is connected to the second signal output terminal OUT2, and its second terminal is connected to the first fixed voltage terminal LVGL. The gate of the tenth transistor M13A is connected to the first pull-down node PD1, its first terminal is connected to the first signal output terminal OUT1, and its second terminal is connected to the second fixed voltage terminal VGL.

[0103] The second pull-up control circuit 017 includes: an eleventh transistor M5B, a twelfth transistor M6B, and a thirteenth transistor M7B. The gate and first terminal of the eleventh transistor M5B are connected to the second control terminal VDDe, and the second terminal of the fifth transistor M5A is connected to the second pull-down node PD2. The gate of the twelfth transistor M6B is connected to the pull-up node PU, the first terminal of the twelfth transistor M6B is connected to the second pull-down node PD2, and the second terminal of the twelfth transistor M6B is connected to the first fixed voltage terminal LVGL. The gate of the thirteenth transistor M7B is connected to the signal input terminal INPUT, the first terminal of the thirteenth transistor M7B is connected to the second pull-down node PD2, and the second terminal of the thirteenth transistor M7B is connected to the first fixed voltage terminal LVGL.

[0104] The second pull-up circuit 018 includes: a fourteenth transistor M8B, a fifteenth transistor M12B, and a sixteenth transistor M13B. The gate of the fourteenth transistor M8B is connected to the second pull-down node PD2, its first terminal is connected to the pull-up node PU, and its second terminal is connected to the first fixed voltage terminal LVGL. The gate of the fifteenth transistor M12B is connected to the second pull-down node PD2, its first terminal is connected to the second signal output terminal OUT2, and its second terminal is connected to the first fixed voltage terminal LVGL. The gate of the sixteenth transistor M13B is connected to the second pull-down node PD2, its first terminal is connected to the first signal output terminal OUT1, and its second terminal is connected to the second fixed voltage terminal VGL.

[0105] The first terminal of the storage capacitor C is connected to the pull-up node PU, and the second terminal of the storage capacitor C is connected to the first signal output terminal OUT1.

[0106] In each transistor, one of the first and second terminals is the source, and the other is the drain.

[0107] In this embodiment, the thickness of the source / drain layer 1024 can be 350 nm, and the thickness of the gate 1021 can be 345 nm. Of course, the thickness of the source / drain layer 1024 and the gate 1021 can also be other thicknesses, and this embodiment does not limit them.

[0108] In summary, the embodiments of this application provide an array substrate. One side of the row driving region of the array substrate is designed with multiple first patterns to ensure sufficient etching solution to etch the source and drain electrodes of the thin-film transistors forming the row driving region and the display region. This avoids material residue in the source and drain film layers due to insufficient etching solution in the row driving region and the display region, prevents the channels of the thin-film transistors from becoming conductive due to material residue in the source and drain film layers above the active layer, and prevents the active layer of the thin-film transistors from becoming conductive. This ensures the characteristics of the thin-film transistors, improves the yield of the array substrate, and enhances the display effect of the display panel.

[0109] Figure 15 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application. (Reference) Figure 15 As can be seen, the display panel 01 may include a plurality of light-emitting units 20 and an array substrate 10 as provided in the above embodiment. The plurality of light-emitting units 20 may be located in the display area 101a of the array substrate 10. Figure 15 The light-emitting unit 20 shown in the figure is only used to indicate that the light-emitting unit 20 is located in the display area 101a, and is not used to indicate the actual shape of the light-emitting unit 20.

[0110] Figure 16 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. (Reference) Figure 16 The display device may include a power supply component 02 and a display panel 01 as provided in the above embodiments. The power supply component 02 can be used to supply power to the display panel 01.

[0111] Optionally, the display device can be: a liquid crystal display (LCD), an organic light-emitting diode (OLED) display device, electronic paper, a low-temperature poly-silicon (LTPS) display device, a low-temperature poly-silicon oxide (LTPO) display device, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or any other product or component with a display function.

[0112] In all embodiments of this application, the transistors can be thin-film transistors. Based on their function in the circuit, the transistors used in the embodiments of this invention are mainly switching transistors. Since the source and drain of the switching transistors used here are symmetrical, their sources and drains are interchangeable. In the embodiments of this application, the source is referred to as the first stage, and the drain as the second stage. According to the configuration shown in the drawings, the middle terminal of the transistor is the gate, the signal input terminal is the source, and the signal output terminal is the drain. Furthermore, the switching transistors used in the embodiments of this application can include either N-type switching transistors or P-type switching transistors. The N-type switching transistor is turned on when the gate is high and turned off when the gate is low, while the P-type switching transistor is turned on when the gate is low and turned off when the gate is high.

[0113] It will be understood that although the terms first, second, etc., may be used herein to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, area, layer, or part from another. Therefore, the first element, component, area, layer, or part discussed above may be referred to as a second element, component, area, layer, or part without departing from the teachings of this disclosure.

[0114] Spatial relative terms such as “row,” “column,” “below,” “above,” “left,” “right,” etc., may be used herein for ease of description to describe the relationship between one element or feature illustrated in the figures and another element(s). It will be understood that these spatial relative terms are intended to cover different orientations of the device in use or operation other than those depicted in the figures. For example, if the device in the figure is flipped, then an element described as “below other elements or features” will be oriented “above other elements or features.” Thus, the exemplary term “below” can cover both orientations above and below. Devices may be oriented in other ways (rotated 90 degrees or otherwise) and the spatial relative descriptors used herein will be interpreted accordingly. Additionally, it will be understood that when a layer is referred to as “between two layers,” it may be the only layer between those two layers, or there may be one or more intermediate layers.

[0115] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprising” and / or “including” as used herein specify the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Specific features, structures, materials, or characteristics described in this specification may be combined in a suitable manner in any one or more embodiments or examples. Furthermore, those skilled in the art can combine and integrate the different embodiments or examples described herein, as well as the features of different embodiments or examples, without contradiction.

[0116] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with their meanings in the relevant field and / or the context of this specification, and will not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0117] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. An array substrate, characterized in that, The array substrate includes: The substrate has a display area and a peripheral area surrounding the display area, the peripheral area including a row driving area extending along a first direction and a fan-out area extending along a second direction, the second direction being parallel to the arrangement direction of the row driving area and the display area; At least a plurality of thin-film transistors located within the row driving region; A plurality of first patterns located at least on one side of the row driving region, and the plurality of first patterns are arranged at intervals from the row driving region along the first direction, and a plurality of first patterns are arranged in an array on the same side of the row driving region; And, at least one of the second patterns located on one side of the fan-out region, the second patterns being spaced apart from the fan-out region along the second direction, and an array of the second patterns located on the same side of the fan-out region, wherein the second patterns are different from at least one of the shape and size of the first pattern; The thin-film transistor includes: a gate, a gate insulating layer, an active layer, and a source-drain layer sequentially stacked along a direction away from the substrate, wherein the source-drain layer includes a source and a drain disposed at intervals; the plurality of first patterns are located in the same layer as at least one of the source and the drain; the plurality of second patterns include: a plurality of first-type second patterns and a plurality of second-type second patterns, wherein the plurality of first-type second patterns are located in the same layer as the gate, and the plurality of second-type second patterns are located in the same layer as the source and the drain.

2. The array substrate according to claim 1, characterized in that, The shape of the orthographic projection of the first pattern onto the substrate is rectangular.

3. The array substrate according to claim 2, characterized in that, The shape of the orthographic projection of the first pattern onto the substrate is a square.

4. The array substrate according to claim 3, characterized in that, In the first pattern, one of the two perpendicular boundaries is parallel to the first direction, and the other boundary is parallel to the second direction; The second direction is parallel to the arrangement direction of the display area and the row driving area, and the first direction and the second direction intersect.

5. The array substrate according to claim 4, characterized in that, The length of the first pattern along the first direction is m1, the distance between any two adjacent first patterns along the first direction is n1, and the ratio of m1 / n1 ranges from 0.9 to 1.

9. The length of the first pattern along the second direction is m2, the distance between any two adjacent first patterns along the second direction is n2, and the ratio of m2 / n2 ranges from 0.9 to 1.

9.

6. The array substrate according to any one of claims 1 to 5, characterized in that, The minimum distance between the orthographic projection of the plurality of first patterns on the substrate and the orthographic projection of other structures in the array substrate on the substrate ranges from 15 micrometers to 30 micrometers.

7. The array substrate according to any one of claims 1 to 5, characterized in that, The surrounding area includes two row driving areas extending along the first direction, and the two row driving areas are respectively located on both sides of the display area; The plurality of first patterns are located on both sides of each of the row driving regions.

8. The array substrate according to any one of claims 1 to 5, characterized in that, The orthographic projections of the plurality of first-type second patterns on the substrate do not overlap with the orthographic projections of the plurality of second-type second patterns on the substrate.

9. The array substrate according to claim 8, characterized in that, The orthographic projections of the plurality of first-type second patterns on the substrate and the orthographic projections of the plurality of second-type second patterns on the substrate are arranged alternately in the second direction.

10. The array substrate according to any one of claims 1 to 5, characterized in that, The number of the plurality of first-type second patterns and the plurality of second-type second patterns are the same, and they correspond one-to-one; The orthographic projection of each of the first type of second patterns on the substrate overlaps with the orthographic projection of the corresponding second type of second pattern on the substrate.

11. The array substrate according to any one of claims 1 to 5, characterized in that, The shape of the orthographic projection of the second pattern onto the substrate is rectangular, and the length of the second pattern along the first direction is greater than the length along the second direction.

12. The array substrate according to claim 11, characterized in that, In the second pattern, one of the two perpendicular boundaries is parallel to the first direction, and the other boundary is parallel to the second direction.

13. The array substrate according to claim 12, characterized in that, The length of the second pattern along the first direction is r1, the distance between any two adjacent second patterns along the first direction is s1, and the ratio of r1 / s1 ranges from 0.9 to 1.

9. The length of the second pattern along the second direction is r2, the distance between any two adjacent second patterns along the second direction is s2, and the ratio of r2 / s2 ranges from 0.9 to 1.

9.

14. The array substrate according to any one of claims 1 to 5, characterized in that, The minimum distance between the orthographic projection of the second pattern on the substrate and the orthographic projection of other structures in the array substrate on the substrate ranges from 75 micrometers to 100 micrometers.

15. The array substrate according to any one of claims 1 to 5, characterized in that, The plurality of second patterns are located on both sides of the fan-out area.

16. The array substrate according to claim 1, characterized in that, The multiple thin-film transistors located in the row driving region constitute multiple cascaded shift register units, each of the shift register units including 18 thin-film transistors and a storage capacitor.

17. The array substrate according to claim 1, characterized in that, The active layer of the thin-film transistor is a metal oxide material.

18. A display panel, characterized in that, The display panel includes a plurality of light-emitting units and an array substrate as described in any one of claims 1 to 17; The plurality of light-emitting units are located in the display area of ​​the array substrate.

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