Atomicity assurance in write through mode

Abstract

A power-off protection fault is detected at a memory device. Based on detecting the power-off protection fault, an unused entry count in a log buffer is determined. A host command is received, and a number of entries required to record the host command to the log buffer is determined. In response to determining that the unused entry count in the log buffer includes at least the number of entries required to record the host command to the log buffer, the host command is recorded in the log buffer, and reducing the unused entry count by the number of entries required to record the host command to the log buffer.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to memory subsystems, and more particularly to managing log buffers to ensure memory device operation atomicity. Background Art

[0002] The memory subsystem may include one or more memory devices that store data. The memory devices may be, for example, nonvolatile memory devices and volatile memory devices. In general, the host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The present disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments of the present disclosure.

[0004] Figure 1 is a diagram illustrating an example computing system including a memory subsystem according to some embodiments of the present disclosure.

[0005] Figure 2 is a diagram illustrating example interactions between components of a memory subsystem in managing a log buffer to ensure atomicity of memory device operations according to some embodiments of the present disclosure.

[0006] Figure 3 is a diagram illustrating an example method for managing a log buffer to ensure atomicity of memory device operations according to some embodiments of the present disclosure.

[0007] Figure 4 is a flow chart illustrating an example method for managing a log buffer to ensure atomicity of memory device operations according to some embodiments of the present disclosure.

[0008] Figure 5 is a diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0009] Aspects of the present disclosure relate to a method for managing a log buffer to ensure atomicity of memory device operations. The memory subsystem may be a storage device (e.g., a solid state drive (SSD)), a memory module, or a combination of a storage device and a memory module. Figure 1Examples of other storage devices and memory modules are described. In general, a host system may utilize a memory subsystem that includes one or more components, such as memory devices that store data. The host system may provide data to be stored at the memory subsystem and may request data to be retrieved from the memory subsystem. A memory subsystem controller typically receives commands or operations from the host system and may convert the commands or operations into instructions or appropriate commands to achieve desired access to memory components of the memory subsystem.

[0010] The memory device may be a non-volatile memory device. An example of a non-volatile memory device is a NAND memory device. Figure 1 Other examples of non-volatile memory devices are described. A NAND memory device may include multiple NAND dies. Each die may include one or more planes and each plane includes multiple blocks. Each block includes an array including pages (rows) and strings (columns). A string includes multiple memory cells connected in series. A memory cell ("cell") is an electronic circuit that stores information. Depending on the cell type, a cell can store one or more binary information bits and have various logical states related to the number of bits stored. The logical state can be represented by a binary value (e.g., "0" and "1") or a combination of such values.

[0011] Various memory access operations can be performed on memory cells. Data can be written to memory cells, data can be read from memory cells, and data can be erased from memory cells. Memory cells can be grouped into write units, such as pages. For some types of memory devices, a page is the smallest write unit. The page size represents the number of specific cells in a page. For some types of memory devices (e.g., NAND), memory cells can be grouped into erase units, such as blocks. Data can be written to blocks page by page. Data can be erased at the block level. However, parts of a block cannot be erased.

[0012] In the context of a memory subsystem, a physical address identifies the physical location of data in a memory device. A logical address is a virtual address used by a host system as a reference to access a unit of data corresponding to a physical location in a memory device. A unit of data may correspond to a block, a page, or a subpage. The memory subsystem maintains a logical-to-physical (L2P) table (also referred to as an "L2P mapping" or "data mapping") to process access requests received from the host system. The L2P table contains a mapping between a physical address and a logical address. The L2P table is typically stored in a volatile memory and is therefore lost in the event of a power outage.

[0013] The log buffer is a data structure with a fixed number of entries that is used by the memory subsystem controller to rebuild the logical address to physical address mapping when the system is powered on after a sudden power off event. Each entry in the log buffer is used to record the physical address of the written data and the logical address corresponding to the physical address. One or more entries may be required to record each command. One or more log buffers may be maintained by the flash translation layer (FTL) of the memory subsystem controller.

[0014] Memory devices are typically equipped with a power loss protection (PLP) mechanism to ensure data integrity in the event of a power loss. Typically, the PLP mechanism includes a PLP capacitor to supply power to the memory device in the event of such a power loss. The power supplied by the PLP capacitor allows the memory subsystem controller to save critical data and corresponding system management information to the memory device. However, the PLP capacitor is susceptible to failure, especially in the later stages of the life cycle of the memory device. If the PLP capacitor fails, the memory subsystem controller cannot save data on the memory device when a power loss occurs.

[0015] Conventionally, if the memory subsystem controller detects a failure of the PLP capacitor, the memory subsystem controller places the memory device in read-only mode. While in read-only mode, only read commands (and a limited set of management commands) can be processed at the device, but write commands cannot be processed. However, this limited functionality does not meet common business needs well. Therefore, the memory subsystem is usually configured to place the memory device in write-through mode instead when a PLP failure is detected. While in write-through mode, write commands can be received from the host system, but the memory subsystem controller does not return completion status to the host system until the write data is saved to the memory device. Although the use of write-through mode is intended to be temporary (e.g., a few weeks), the memory device remains in write-through mode until the memory device is replaced.

[0016] Certain functional specifications (such as the NVMe specification) that define the functionality required of a memory device include requirements for atomicity of operations in the memory device to ensure that data from a first command is stored continuously without intermediate partial data from a second command. This requirement is also referred to as "atomic operation". In order to support atomic operations at the memory device, commands are serviced serially so that only a single unit of the logical address is serviced at any one time. In normal operation, this unit is defined as Atomic Write Unit Normal (AWUN), and when the PLP capacitor provides PLP in a power-off event, this unit is defined as "Atomic Write Unit Power Failure (AWUPF)".

[0017] To support atomic operations during write-through mode, the memory subsystem applies the following principles: 1) ensure that all data belonging to a single command is completely written to the memory device before returning completion status to the host system; and 2) aggregate as many write commands as possible before flushing critical flash translation layer (FTL) structures (such as the log buffer) to optimize write amplification. Typically, when in write-through mode, write commands are aggregated to saturate the log buffer. Therefore, if a sudden power outage occurs before the log buffer is flushed to the memory device, there is a risk of returning old data to the host system.

[0018] In some cases, it may be necessary to log commands to multiple entries that span two log buffers. If a sudden power outage occurs after the first log buffer is flushed but before the second log buffer is flushed, the requirement for atomic operations will be violated. That is, after the next power-on, only part of the log entries from the first log can be used to rebuild the translation table, but the translation table will not be fully updated because the log entries from the second log will be lost at the time of the power outage.

[0019] Aspects of the present disclosure solve the aforementioned problems by utilizing a method for managing a log buffer that ensures memory device atomicity when the memory device is in write-through mode. According to this method, based on placing the memory device in write-through mode in response to detecting a PLP failure, a log buffer management component of a memory subsystem controller initiates a log buffer entry budget, the log buffer entry budget including a count of unused entries (unfilled entries from a fixed number of total entries) in the log buffer. The log buffer management component uses the log buffer entry budget to determine whether to record a command to the log buffer or to first flush the log buffer to the memory device before recording the command.

[0020] In an example, when a PLP failure is detected at a memory device, the memory device is placed in write-through mode. Based on the memory device being placed in write-through mode, the log buffer management component accesses the log buffer to determine an unused entry count, and the log buffer management component uses the determined count to start a log buffer entry budget. When a command is received from a host system, the log buffer management component determines the number of entries required to record the command to the log buffer. If the log entry budget includes at least the number of entries required to record the command, the command is recorded to the log buffer (e.g., by filling one or more entries) and the log buffer entry budget is reduced accordingly. If the number of log entries required to record the command to the log buffer exceeds the unused entry count indicated by the log entry budget, the memory subsystem controller saves the command when the log buffer is flushed to the memory device. The log buffer entry budget increases based on the log buffer being flushed (e.g., to indicate that all entries in the log buffer are unused). Once the log buffer is flushed, the command is serviced and recorded.

[0021] With this method for managing the log buffer, entries for recording write commands will not span multiple log buffers, and thus data belonging to a write command interrupted by a sudden power failure after a PLP failure can be fully recovered during the next power-on sequence by traversing the entries of a single log buffer that has been flushed to the memory device. Therefore, the operation atomicity of the memory device can be maintained when in write-through mode.

[0022] Figure 1 An example computing system 100 is illustrated that includes a memory subsystem 110 according to some embodiments of the present disclosure. Memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination thereof.

[0023] The memory subsystem 110 may be a storage device, a memory module, or a mixture of a storage device and a memory module. Examples of storage devices include SSDs, flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual inline memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual inline memory modules (NVDIMMs).

[0024] Computing system 100 may be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, a car, or other transportation), a device with Internet of Things (IoT) capabilities, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked business device), or such a computing device including a memory and a processing device.

[0025] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to memory subsystems 110 of different types. Figure 1 An example of a host system 120 coupled to one memory subsystem 110 is illustrated. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, and the like.

[0026] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a peripheral component interconnect express (PCIe) controller, a serial advanced technology attachment (SATA) controller). The host system 120 uses the memory subsystem 110, for example, to write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0027] The host system 120 may be coupled to the memory subsystem 110 via a host interface. Examples of the host interface include, but are not limited to, a SATA interface, a PCIe interface, a USB interface, a Fibre Channel, a Serial Attached SCSI (SAS), a Small Computer System Interface (SCSI), a Double Data Rate (DDR) memory bus, a DIMM interface (e.g., a DIMM slot interface supporting Double Data Rate (DDR)), an Open NAND Flash Interface (ONFI), Double Data Rate (DDR), Low Power Double Data Rate (LPDDR), or any other interface. The host interface may be used to transfer data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 through a PCIe interface, the host system 120 may further utilize an NVM Express (NVMe) interface to access components (e.g., the memory device 130). The host interface may provide an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 120. Figure 1Memory subsystem 110 is illustrated. In general, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0028] The memory devices 130, 140 may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0029] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND-type flash memory and write-in-place memory, such as a three-dimensional cross-point (3D cross-point) memory device, which is a cross-point array of non-volatile memory cells. The cross-point array of non-volatile memory can be combined with a stackable cross-grid data access array to perform bit storage based on changes in body resistance. In addition, compared to many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, where non-volatile memory cells can be programmed without first erasing the non-volatile memory cells. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and 3D NAND.

[0030] Each of the memory devices 130 may include one or more arrays of memory cells. One type of memory cell (e.g., single-level cell (SLC)) may store one bit per cell. Other types of memory cells (e.g., multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC)) may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells (e.g., SLC, MLC, TLC, QLC, or any combination thereof). In some embodiments, a particular memory device may include an SLC portion, an MLC portion, a TLC portion, a QLC portion, or a PLC portion of memory cells. The memory cells of the memory device 130 may be grouped into pages, which may refer to a logical unit of a memory device used to store data. For some types of memory (e.g., NAND), pages may be grouped to form blocks. For example, a memory device may include a group of blocks. A design specification may define a constraint on the minimum number of valid blocks of the memory device 130, which may be different from the number of blocks in the group of blocks on the device.

[0031] Although nonvolatile memory components such as NAND-type flash memory (e.g., 2D NAND, 3D NAND), and 3D cross-point arrays of nonvolatile memory cells are described, the memory device 130 may be based on any other type of nonvolatile memory, such as read-only memory (ROM), phase-change memory (PCM), self-select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0032] The memory subsystem controller 115 (or simply controller 115) can communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data at the memory device 130, and other such operations. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware may include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0033] The memory subsystem controller 115 may include a processor 117 (processing device) configured to execute instructions stored in a local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes an embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0034] In some embodiments, local memory 119 may include memory registers that store memory pointers, fetched data, and the like. Local memory 119 may also include ROM for storing microcode. Figure 1 The example memory subsystem 110 in FIG. 1 has been described as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may rely on external control (e.g., provided by an external host, or provided by a processor or controller separate from the memory subsystem).

[0035] In general, the memory subsystem controller 115 may receive commands or operations from the host system 120 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130 and / or the memory device 140. The memory subsystem controller 115 may be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical addresses (e.g., logical block addresses (LBA), namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuit system to communicate with the host system 120 via a physical host interface. The host interface circuit system may convert commands received from the host system 120 into command instructions to access the memory device 130 and / or the memory device 140, and convert responses associated with the memory device 130 and / or the memory device 140 into information for the host system 120.

[0036] In some embodiments, the memory device 130 includes a local media controller 135 that operates in conjunction with the memory subsystem controller 115 to perform operations on one or more memory cells of the memory device 130 .

[0037] The memory subsystem 110 also includes a log buffer management component 113 that is responsible for managing a log buffer 114 in a manner that ensures atomicity of memory device operations. The log buffer is used to record host commands processed by the memory subsystem 110. Thus, the log buffer 114 includes a fixed number of entries for recording commands. The filled entries in the log buffer 114 include a logical address and an associated physical address corresponding to a location in one of the memory devices 130 or 140 where the data is written.

[0038] The log buffer management component 113 maintains a log buffer entry budget that includes a count of available (unfilled) entries from among a fixed number of total entries in the log buffer 114. When the memory device is placed in write-through mode (e.g., based on a PLP failure), the log buffer management component 113 uses the log buffer entry budget to determine whether to log a command to the log buffer 114 or to flush the log buffer 114 before logging a command.

[0039] In an example, when a PLP failure is detected at the memory device 130, the memory device 130 is placed in write-through mode. While in write-through mode, a write command may be received from the host system 120, but the memory subsystem 110 does not return a completion status to the host system 120 until the write data is completely saved to the memory device 130. Based on the memory device 130 being placed in write-through mode, the log buffer management component 113 accesses the log buffer 114 to determine the unused entry count and the log buffer management component 113 uses the determined count to start the log buffer entry budget. When a command is received from the host system 120, the log buffer management component 113 determines the number of entries required to record the command to the log buffer 114. If the log entry budget includes at least the number of entries to record the command, the command is recorded to the log buffer (e.g., by filling one or more entries) and the log entry budget is reduced accordingly. If the number of log entries required to record the command to the log buffer exceeds the unused entry count indicated by the log entry budget, the memory subsystem 110 saves the command when the log buffer 114 is flushed to the memory device 130. The log buffer entry budget is increased based on the log buffer 114 being flushed (eg, to indicate that all entries in the log buffer 114 are unused). Once the log buffer 114 is flushed, commands are serviced and logged. Further details on the functionality of the log buffer management component 113 are discussed below.

[0040] In some embodiments, the memory subsystem controller 115 includes at least a portion of the data log buffer. For example, the memory subsystem controller 115 may include a processor 117 (processing device) configured to execute instructions stored in the local memory 119 for performing the operations described herein. In some embodiments, the log buffer management component 113 is part of the host system 120, an application, or an operating system. In some embodiments, the local media controller 135 includes at least a portion of the log buffer management component 113.

[0041] Figure 2 is a conceptual diagram illustrating example interactions between components of a memory subsystem when managing a log buffer according to some embodiments of the present disclosure. Figure 2 In the example illustrated in , the memory device 130 is in the example form of a NAND memory device. In this example, the memory device 130 includes a plurality of NAND dies, each die may include one or more planes, each of the planes includes a plurality of blocks. Each block includes a 2D array including pages (rows) and strings (columns). A string includes a plurality of memory cells connected in series. Each memory cell is used to represent one or more bit values.

[0042] In this example, the memory device 130 includes a power loss protection (PLP) component 202 to ensure data integrity when a power loss event occurs at the memory device 130. The PLP component 202 may include one or more PLP capacitors to supply power to the memory device 130 in the event of such a power loss. The memory subsystem controller 115 monitors the operation of the PLP component 202, and upon detecting a PLP failure (at operation 204) (e.g., failure of a PLP capacitor), the memory subsystem controller 115 places the memory device 130 in a write-through mode (operation 206). When in the write-through mode, the memory device 130 may be powered from the memory device 130. Figure 1 The host system 120 receives the write command, but Figure 1 The memory subsystem 110 does not return a completion status to the host system 120 until the write data is completely saved to the memory device 130 .

[0043] Based on the memory device 130 being placed in write-through mode, the log buffer management component 113 initializes Figure 1 The log entry budget 210 in the local memory 119 of the log buffer 114 is calculated (operation 208). The log entry budget 210 includes a count of unused entries in the log buffer 114. The log buffer 114 includes a fixed number of total entries (Entry 0 To Entry N ), and one or more of the entries may be used to record one or more host commands directed to the memory device 130 that have been processed by the memory subsystem 110. When an entry in the log buffer 114 is filled (used), the entry includes a physical address where write data is written and a logical address corresponding to the physical address (used by the host system 120). Unused and available entries in the log buffer 114 are considered unused entries and are therefore included in the unused entry count.

[0044] When in write-through mode, Figure 1 The host system 120 receives a command to write data to the memory device 130 (operation 212). The command includes write data and specifies one or more logical addresses. The log buffer management component 113 determines the number of entries required to record the command in the log buffer 114 (operation 214). As an example, the log buffer management component 113 may determine the number of entries based on the number of logical addresses specified by the command.

[0045] At operation 216, the log buffer management component 113 compares the number of entries required to log the command in the log buffer 114 with the log entry budget 210 to determine whether there are enough entries to log the command in the log buffer 114. That is, the log buffer management component 113 determines whether the unused entry count in the log buffer 114 is equal to or greater than the number of entries required to log the command.

[0046] If the log entry budget 210 includes at least the number of entries required to record the command, the log buffer management component 113 records the command in the log buffer 114 (operation 218) and reduces the log entry budget 210 accordingly (operation 220). That is, the log buffer management component 113 fills the entries in the log buffer 114 with one or more logical addresses along the physical address corresponding to each logical address, and subtracts the number of entries used to record the command from the available entry count in the log entry budget 210.

[0047] If the number of entries required to log the command exceeds the unused entry count in the log buffer 114 (indicated by the log entry budget 210), the log buffer management component 113 flushes the log buffer 114 to the memory device 130 (operation 222), while the memory subsystem controller 115 saves the commands until there is enough space in the log buffer 114. When flushing the log buffer to the memory device 130, the log buffer management component 113 copies the filled entries to the table stored by the memory device 130 and removes the filled entries from the log buffer 114. Based on flushing the log buffer 114, the log buffer management component 113 updates the log entry budget 210 to reflect that the log buffer 114 has been flushed (operation 224). That is, the log buffer management component 113 increases the unused entry count in the log entry budget 210 by the number of entries flushed to the memory device 130.

[0048] For some embodiments, the flash translation layer of the memory subsystem controller 115 handles flushing the log buffer 114 to the memory device 130, and for these embodiments, the log buffer management component 113 instructs the flash translation layer to flush the log buffer 114 in response to determining that the number of entries required to log the command exceeds the unused entry count in the log buffer 114. The flash translation layer flushes the log buffer 114 in response to the instruction and instructs the log buffer management component 113 to increase the log entry budget 210 accordingly.

[0049] Figure 3 This is used to manage Figure 1 FIG. 1 is a diagram of an example process of a log buffer 300 maintained by the memory subsystem 110 of FIG. 1 . The log buffer 300 is Figure 1 An example of the log buffer 114. As represented by Figure 3 Background of the example process described, Figure 1 The memory device 130 is in a write-through mode based on detecting a PLP failure at the memory device 130 .

[0050] A host command sequence 302 is shown. The host command sequence 302 includes Figure 1303A, 303B, and 303C. As shown, write command 303A points to logical block addresses (LBAs) 0 to 6; write command 303B points to LBAs 8 to 15; and write command 303C points to LBAs 0 to 31.

[0051] In this example, log buffer 300 includes 4 entries—entries 301-1, 301-2, 301-3, and 301-4. Based on the number of LBAs pointed to by command 303A, recording write command 303A requires a single entry in log buffer 300, and as shown, write command 303A is recorded in entry 301-1 (at 310). Similarly, recording write command 303B requires a single entry in log buffer 300, and as shown, write command 303B is recorded in entry 301-2 (at 320).

[0052] Given the number of LBAs pointed to by command 303C, 4 entries in the log buffer are needed to record command 303C. However, the log buffer contains only 2 unused entries—entries 301-3 and 301-4—after recording commands 303A and 303B, which is less than the entries needed to record command 303C. Figure 1 Rather than logging command 303C with an additional entry from the second log buffer, log buffer management component 113 of flushes log buffer 300 to memory device 130 (at 330) prior to logging command 303C.

[0053] As a result of flushing the logged entries for commands 303A and 303B, each of the log buffer 300 entries 301-1, 301-2, 301-3, and 301-4 are unused and available for logging command 303C. Thus, the log buffer management component 113 logs command 303C to the log buffer 300 (at 340) by filling entries 301-1, 301-2, 301-3, and 301-4 with the logical address associated with command 303C along with the corresponding physical address.

[0054] Figure 4 1 is a flow chart illustrating an example method 400 for managing a log buffer in a memory device (e.g., memory device 130) to ensure atomicity according to some embodiments of the present disclosure. The method 400 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 400 is performed by Figure 1The log buffer management component 113 of the embodiment of the present invention is executed. Although the processes are shown in a particular order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0055] The method 400 begins at operation 405, where a processing device detects a PLP failure within a memory subsystem (eg, memory subsystem 110). The processing device may detect the PLP failure based on a failure of a PLP capacitor.

[0056] At operation 410, the processing device places the memory device in write-through mode in response to detecting a PLP failure. While in write-through mode, a host system (e.g., host system 120) may send a command to the memory subsystem to write data to the memory device, but the memory subsystem does not return a completion status to the host system until the write data is saved to the memory device. The memory device remains in write-through mode until the memory device is replaced.

[0057] At operation 415, in response to the memory device being placed in write-through mode, the processing device determines an unused (available) entry count in a log buffer (e.g., log buffer 114). The processing device may maintain a log entry budget in a local memory (e.g., local memory 119) to track the unused entry count. That is, the log entry budget includes the unused entry count in the log buffer. For some embodiments, the processing device may access the log entry budget when determining the unused entry count in the log buffer. For some embodiments, the processing device may instantiate the log entry budget when the memory device is placed in write-through mode, and in doing so, the processing device may access the log buffer to determine the unused entry count in the log buffer. For some embodiments, the processing device includes a front-end component that maintains the log entry budget.

[0058] At operation 420, while in write-through mode, the processing device receives a command to write data to the memory device. The command includes write data and specifies one or more logical addresses corresponding to locations within the memory device where the write data is to be written.

[0059] At operation 425, the processing device determines the number of entries required to record the command to the log buffer. The processing device may determine the number of entries required to record the command to the log buffer based on the number of logical addresses specified in the command. For example, each entry in the log buffer may be able to record a fixed number of logical addresses and corresponding physical addresses, and thus the processing device may determine the number of entries required to record a given command based on a combination of the number of logical addresses specified by the command and the number of logical addresses that the individual log buffer entries are capable of recording.

[0060] At operation 430, the processing device determines whether the unused entry count in the log buffer includes the number of log entries required to log the command to the log buffer. If the number of log entries required to log the command to the log buffer exceeds the unused entry count in the log buffer, the processing device flushes the log buffer to the memory device (operation 435) and increases the unused entry count in the log buffer based on the log buffer being flushed (operation 440). When flushing the log buffer, the processing device writes entries from the log buffer to the memory device. Flushing the log buffer makes all entries in the log buffer available for use. Therefore, when flushing the log buffer, the unused entry count in the log buffer is updated to reflect that all entries in the log buffer are available.

[0061] Based on the unused log buffer entry count increasing or the unused entry count in the log buffer including at least the number of log entries required to log the command to the log buffer, the processing device logs the command to the log buffer (at operation 445) and reduces the unused entry count in the log buffer based on the number of entries required to log the command to the log buffer (at operation 450). That is, the processing device generates the number of entries in the log buffer corresponding to the command and subtracts the number of entries from the unused entry count. For embodiments in which the processing device includes a front-end component to maintain a log entry budget, the front-end component reduces the log entry budget based on the number of entries in the log buffer used to log the command.

[0062] For some embodiments, the processing device includes a front-end component as discussed above and a flash translation layer that maintains a log buffer. For these embodiments, to flush the log buffer, the front-end component provides one or more instructions to the flash translation layer to flush the log buffer. In response, the flash translation layer flushes the log buffer to the memory device and based on the log buffer being flushed, the flash translation layer instructs the front-end component to increase the log entry budget to reflect that all entries in the log buffer are available.

[0063] As shown, the processing device continues to service incoming host commands in the manner described above while the memory device remains in write-through mode. That is, method 400 may return to operation 420 after reducing the unused log buffer entry count at operation 450, and repeat subsequent operations of method 400 as described above for each additional command received from the host system while the memory device remains in write-through mode.

[0064] In view of the above disclosure, various examples are described below. It should be noted that one or more features of the examples, whether individually or in combination, should be considered within the disclosure of this application.

[0065] Example 1. A memory subsystem comprising: a memory device; and a processing device, which is operably coupled to the memory device and configured to perform operations including the following: detecting a power-off protection fault at the memory device; determining an unused entry count in a log buffer based on detecting the power-off protection fault; receiving a host command; determining the number of entries required to record the host command to the log buffer; determining that the unused entry count in the log buffer at least includes the number of entries required to record the host command to the log buffer; and in response to determining that the unused entry count in the log buffer at least includes the number of entries required to record the host command to the log buffer, recording the host command in the log buffer; and reducing the unused entry count based on recording the host command to the log buffer.

[0066] Example 2. The memory subsystem of example 1, wherein determining the unused entry count in the log buffer comprises accessing the log buffer to determine the unused entry count, wherein the operations further comprise initiating a log buffer entry budget based on the unused entry count.

[0067] Example 3. A memory subsystem according to any one or more of Examples 1 or 2, wherein determining the unused entry count in the log buffer includes accessing a log entry budget stored in a local memory, the log entry budget including the unused entry count in the log buffer.

[0068] Example 4. The memory subsystem of any one or more of examples 1-3, wherein reducing the unused entry count comprises reducing the log entry budget by the number of entries required to log the host command.

[0069] Example 5. A memory subsystem according to any one or more of Examples 1 to 4, wherein: the host command is a first host command; the operation further includes: receiving a second host command; determining the number of entries required to record the second host command to the log buffer; determining that the number of entries required to record the second host command to the log buffer exceeds the unused entry count in the log buffer; based on the determination that the number of entries required to record the second host command to the log buffer exceeds the unused entry count in the log buffer, flushing the log buffer to the memory device; and increasing the unused entry count in the log buffer in response to the refresh of the log buffer.

[0070] Example 6. A memory subsystem according to any one or more of Examples 1 to 5, wherein the operation further comprises recording the second host command to the log buffer based on increasing the unused entry count in the log buffer according to the flush of the log buffer.

[0071] Example 7. A memory subsystem according to any one or more of Examples 1 to 6, wherein flushing the log buffer to the memory device includes: instructing a flash translation layer to flush the log buffer to the memory device; and increasing the count based on the flushing of the log buffer includes receiving an indication from the flash translation layer to increase a log entry budget, the log entry budget including the unused entry count in the log buffer.

[0072] Example 8. The memory subsystem of any one or more of examples 1 to 7, wherein determining a number of entries required to log the host command to the log buffer comprises determining a number of logical addresses specified by the host command.

[0073] Example 9. A memory subsystem according to any one or more of Examples 1 to 8, wherein the operation further comprises: placing the memory device in a write-through mode in response to detecting the power-off protection fault, wherein the host command is received while the memory subsystem is in the write-through mode.

[0074] Example 10. The memory subsystem of any one or more of examples 1 to 9, further comprising: a power-off protection capacitor, wherein detecting the power-off protection fault comprises detecting a fault of the power-off protection capacitor.

[0075] Example 11. A method comprising: detecting a power-off protection fault at a memory device; determining an unused entry count in a log buffer based on detecting the power-off protection fault; receiving a host command; determining the number of entries required to record the host command to the log buffer; determining that the unused entry count in the log buffer at least includes the number of entries required to record the host command to the log buffer; in response to determining that the unused entry count in the log buffer at least includes the number of entries required to record the host command to the log buffer, recording the host command in the log buffer; and reducing the unused entry count by the number of entries required to record the host command to the log buffer.

[0076] Example 12. The method of example 11, wherein determining the unused entry count in the log buffer comprises accessing the log buffer to determine the unused entry count, wherein the method further comprises: initiating a log buffer entry budget based on the unused entry count.

[0077] Example 13. A method according to any one or more of Examples 11 or 12, wherein determining the unused entry count in the log buffer includes accessing a log entry budget stored in a local memory, the log entry budget including the unused entry count in the log buffer.

[0078] Example 14. The method of any one or more of examples 11-13, wherein reducing the unused entry count comprises reducing the log entry budget by the number of entries required to log the host command.

[0079] Example 15. A method according to any one or more of Examples 11 to 14, wherein: the host command is a first host command; the method further includes: receiving a second host command; determining the number of entries required to record the second host command to the log buffer; determining that the number of entries required to record the second host command to the log buffer exceeds the unused entry count in the log buffer; based on determining that the number of entries required to record the second host command to the log buffer exceeds the unused entry count in the log buffer, flushing the log buffer to the memory device; and increasing the unused entry count in the log buffer in response to the refresh of the log buffer.

[0080] Example 16. The method of any one or more of Examples 11 to 15, further comprising recording the second host command to the log buffer based on increasing the unused entry count in the log buffer according to the flushing of the log buffer.

[0081] Example 17. A method according to any one or more of Examples 11 to 16, wherein flushing the log buffer to the memory device includes instructing a flash translation layer to flush the log buffer to the memory device; and increasing the count based on the flush of the log buffer includes receiving an indication from the flash translation layer to increase a log entry budget, the log entry budget including the unused entry count in the log buffer.

[0082] Example 18. The method of any one or more of examples 11 to 17, wherein determining the number of entries required to log the host command to the log buffer comprises determining a number of logical addresses specified by the host command.

[0083] Example 19. The method of any one or more of Examples 11 to 18, further comprising: placing the memory device in a write-through mode in response to detecting the power-off protection fault, wherein the host command is received while the memory device is in the write-through mode.

[0084] Example 20. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, configure the processing device to perform operations comprising: detecting a power-off protection fault at a memory device; determining an unused entry count in a log buffer based on detecting the power-off protection fault; receiving a host command; determining the number of entries required to record the host command to the log buffer; determining that the unused entry count in the log buffer includes at least the number of entries required to record the host command to the log buffer; and in response to determining that the unused entry count in the log buffer includes at least the number of entries required to record the host command to the log buffer, recording the host command in the log buffer; and reducing the unused entry count by the number of entries required to record the host command to the log buffer.

[0085] Figure 5 An example machine in the form of a computer system 500 is illustrated within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In some embodiments, the computer system 500 may correspond to a host system (e.g., Figure 11) a host system 120 that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 110), or may be used to perform operations of the controller (e.g., execute an operating system to execute operations corresponding to Figure 1 In some embodiments, the machine may be connected (e.g., using a network) to other machines in a local area network (LAN), an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0086] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Furthermore, while a single machine is described, the term "machine" shall also be taken to include any collection of machines that individually or collectively execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0087] The example computer system 500 includes a processing device 502, a main memory 504 (e.g., ROM, flash memory, DRAM (such as SDRAM or RDRAM), etc.), a static memory 506 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 518, which communicate with each other via a bus 530.

[0088] The processing device 502 represents one or more general purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets or multiple processors implementing a combination of instruction sets. The processing device 502 may also be one or more special purpose processing devices, such as an ASIC, an FPGA, a digital signal processor (DSP), a network processor, or the like. The processing device 502 is configured to execute instructions 526 for performing the operations and steps discussed herein. The computer system 500 may further include a network interface device 508 for communicating over a network 520.

[0089] The data storage system 518 may include a machine-readable storage medium 524 (also referred to as a computer-readable medium) having stored thereon one or more sets of instructions 526 or software embodying any one or more of the methodologies or functionality described herein. The instructions 526 may also reside, completely or at least partially, within the main memory 504 and / or within the processing device 502 during execution of the instructions 526 by the computer system 500, the main memory 504 and the processing device 502 also constituting machine-readable storage media. The machine-readable storage medium 524, the data storage system 518, and / or the main memory 504 may correspond to Figure 1 Memory subsystem 110.

[0090] In one embodiment, the instructions 526 include instructions for implementing a command corresponding to a data destruction component (e.g., Figure 1 The machine-readable storage medium 524 is shown as a single medium in the example embodiment, but the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for machine execution and causing the machine to perform any one or more methodologies of the present disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but not limited to, solid-state memory, optical media, and magnetic media.

[0091] Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is herein and generally conceived to be a self-consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulation of physical quantities. Typically, but not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, primarily for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, items, numbers, or the like.

[0092] It should be borne in mind, however, that all of these and similar terms should be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may involve actions and processes of computer systems or similar electronic computing devices that manipulate and transform data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0093] The present disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the intended purpose, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. This computer program may be stored in a computer readable storage medium, such as but not limited to any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0094] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems may be used with programs according to the teachings herein, or it may prove convenient to build more specialized equipment to perform the methods. The structures for various of these systems will appear as set forth in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that various programming languages ​​may be used to implement the teachings of the present disclosure as described herein.

[0095] The present disclosure may be provided as a computer program product or software that may include a machine-readable medium having instructions stored thereon, which instructions may be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as ROM, RAM, magnetic disk storage media, optical storage media, flash memory components, and the like.

[0096] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to the present disclosure without departing from the broader scope of the examples of the present disclosure as set forth in the appended claims. Therefore, the description and drawings should be regarded as having an illustrative rather than a restrictive sense.

Claims

1. A memory subsystem comprising: Memory device; and A processing device, operatively coupled to the memory device, configured to perform operations including: detecting a power-off protection fault at the memory device; determining a count of unused entries in a log buffer based on detecting the power failure protection fault; Receive host commands; determining a number of entries required to log the host command to the log buffer; determining that the unused entry count in the log buffer includes at least the number of entries required to log the host command to the log buffer; as well as In response to determining that the unused entry count in the log buffer includes at least the number of entries required to log the host command to the log buffer, logging the host command in the log buffer; and The unused entry count is reduced based on the logging of the host command to the log buffer.

2. The memory subsystem of claim 1, wherein determining the unused entry count in the log buffer comprises accessing the log buffer to determine the unused entry count, wherein the operations further comprise initiating a log buffer entry budget based on the unused entry count. 3 . The memory subsystem of claim 1 , wherein determining an unused entry count in the log buffer comprises accessing a log entry budget stored in a local memory, the log entry budget comprising the unused entry count in the log buffer. 4 . The memory subsystem of claim 3 , wherein reducing the unused entry count comprises reducing the log entry budget by the number of entries required to log the host command.

5. The memory subsystem of claim 1 , wherein: The host command is a first host command; The operations further include: receiving a second host command; determining a number of entries required to log the second host command to the log buffer; determining that the number of entries required to log the second host command to the log buffer exceeds the unused entry count in the log buffer; flushing the log buffer to the memory device based on the determining that the number of entries required to log the second host command to the log buffer exceeds the unused entry count in the log buffer; and The unused entry count in the log buffer is incremented in response to the flush of the log buffer.

6. The memory subsystem of claim 5, wherein the operations further comprise logging the second host command to the log buffer based on the incrementing the unused entry count in the log buffer in accordance with the flushing of the log buffer.

7. The memory subsystem of claim 5, wherein said flushing said log buffer to said memory device comprises: instructing a flash translation layer to flush the log buffer to the memory device; and Increasing the count based on the flush of the log buffer comprises receiving an indication from the flash translation layer to increase a log entry budget, the log entry budget comprising the unused entry count in the log buffer.

8. The memory subsystem of claim 1, wherein determining a number of entries required to log the host command to the log buffer comprises determining a number of logical addresses specified by the host command.

9. The memory subsystem of claim 1 , wherein the operations further comprise: The memory device is placed in a write-through mode in response to detecting the power-off protection fault, wherein the host command is received while the memory subsystem is in the write-through mode.

10. The memory subsystem of claim 1, further comprising: A power-off protection capacitor is provided, wherein detecting the power-off protection fault comprises detecting a fault of the power-off protection capacitor.

11. A method comprising: detecting a power-off protection fault at a memory device; determining a count of unused entries in a log buffer based on detecting the power failure protection fault; Receive host commands; determining a number of entries required to log the host command to the log buffer; determining that the unused entry count in the log buffer includes at least a number of entries required to log the host command to the log buffer; In response to determining that the unused entry count in the log buffer includes at least the number of entries required to log the host command to the log buffer, logging the host command in the log buffer; and The unused entry count is reduced by the number of entries required to log the host command to the log buffer.

12. The method of claim 11, wherein determining the unused entry count in the log buffer comprises accessing the log buffer to determine the unused entry count, wherein the method further comprises: A log buffer entry budget is initiated based on the unused entry count.

13. The method of claim 11, wherein determining an unused entry count in the log buffer comprises accessing a log entry budget stored in a local memory, the log entry budget comprising the unused entry count in the log buffer.

14. The method of claim 13, wherein reducing the unused entry count comprises reducing the log entry budget by the number of entries required to log the host command.

15. The method of claim 11, wherein: The host command is a first host command; The method further comprises: receiving a second host command; determining a number of entries required to log the second host command to the log buffer; determining that the number of entries required to log the second host command to the log buffer exceeds the unused entry count in the log buffer; flushing the log buffer to the memory device based on determining that the number of entries required to log the second host command to the log buffer exceeds the unused entry count in the log buffer; and The unused entry count in the log buffer is incremented in response to the flush of the log buffer.

16. The method of claim 15, further comprising logging the second host command to the log buffer based on the incrementing the unused entry count in the log buffer in accordance with the flushing of the log buffer.

17. The method of claim 15, wherein: The flushing the log buffer to the memory device comprises instructing a flash translation layer to flush the log buffer to the memory device; and Increasing the count based on the flush of the log buffer comprises receiving an indication from the flash translation layer to increase a log entry budget, the log entry budget comprising the unused entry count in the log buffer.

18. The method of claim 11, wherein determining the number of entries required to log the host command to the log buffer comprises determining a number of logical addresses specified by the host command.

19. The method of claim 11, further comprising: The memory device is placed in a write-through mode in response to detecting the power-off protection fault, wherein the host command is received while the memory device is in the write-through mode.

20. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, configure the processing device to perform operations comprising: detecting a power-off protection fault at a memory device; determining a count of unused entries in a log buffer based on detecting the power failure protection fault; Receive host commands; determining a number of entries required to log the host command to the log buffer; determining that the unused entry count in the log buffer includes at least the number of entries required to log the host command to the log buffer; as well as In response to determining that the unused entry count in the log buffer includes at least the number of entries required to log the host command to the log buffer, logging the host command in the log buffer; and The unused entry count is reduced by the number of entries required to log the host command to the log buffer.

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