Semiconductor structure, manufacturing method thereof and memory system

Abstract

The embodiment of the invention provides a semiconductor structure, a manufacturing method thereof and a memory system, and the semiconductor structure comprises a stacking structure which comprises a first region, a second region and a junction region located between the first region and the second region; the stacked structure comprises gate layers and insulating layers which are alternately stacked; the gate layer comprises a first gate layer and a plurality of second gate layers located on one side of the first gate layer; a first contact structure in the junction region, extending and connected to the first gate layer; a plurality of second contact structures in the second region, respectively extending and connected to the second gate layers of different layers; wherein the size of the first contact structure in the direction perpendicular to the stacking direction of the stacking structure is different from the size of the second contact structure in the direction perpendicular to the stacking direction.

Description

Semiconductor structure and manufacturing method thereof, and memory system Technical Field

[0001] The present application relates to, but is not limited to, a semiconductor structure and a manufacturing method thereof, and a memory system. Background Art

[0002] To increase the storage density of two-dimensional memories, existing technologies have already mass-produced three-dimensional memories such as three-dimensional (3D) NAND. These memories include a core region with a memory string channel structure and a step region for extracting the gate of the memory string channel structure. The core region comprises alternating insulating layers and gate layers, while the step region includes contacts (CT) for extracting the gate layer.

[0003] As the number of stacked layers of a three-dimensional memory increases, the etching depth of the contact holes used to form contacts also increases accordingly, which places higher requirements on the etching process of the contact holes.

[0004] Summary of the Invention

[0005] According to a first aspect of the present application, a semiconductor structure is provided, comprising: a stacked structure comprising a first region, a second region and a junction region between the first region and the second region; the stacked structure comprising gate layers and insulating layers alternately stacked; the gate layers comprising a first gate layer and a plurality of second gate layers located on one side of the first gate layer; a first contact structure located in the junction region, extending and connected to the first gate layer; a plurality of second contact structures located in the second region, respectively extending and connected to second gate layers of different layers; wherein a dimension of the first contact structure along a stacking direction perpendicular to the stacking structure is different from a dimension of the second contact structure along the stacking direction perpendicular to the stacking direction.

[0006] According to a second aspect of the present application, a method for manufacturing a semiconductor structure is provided, comprising: forming a stacking structure, the stacking structure comprising a first region, a second region and a junction region between the first region and the second region; the stacking structure comprising gate layers and insulating layers alternately stacked; the gate layers comprising a first gate layer and a plurality of second gate layers located on one side of the first gate layer; forming a first contact structure in the junction region using a first process; the first contact structure extending and connected to the first gate layer; forming a plurality of second contact structures in the second region using a second process; the plurality of second contact structures extending and connected to second gate layers of different layers, respectively; wherein the first process is different from the second process.

[0007] According to a third aspect of the present application, a memory system is provided, comprising: a semiconductor structure, which is the semiconductor structure in the above-mentioned solution; and a controller connected to the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] FIG1 is a schematic diagram of an XY plane of a first semiconductor structure provided in an embodiment of the present application;

[0009] FIG2A is a schematic diagram of a YZ cross-section of the first region of the semiconductor structure of FIG1 ;

[0010] FIG2B is a schematic diagram of a BB cross-section of the semiconductor structure interface region of FIG1 ;

[0011] FIG2C is a schematic diagram of a CC cross-section of the second region of the semiconductor structure of FIG1 ;

[0012] 2D is a schematic diagram of a DD cross-section of the second region of the semiconductor structure of FIG. 1 ;

[0013] 2E is a schematic diagram of a YZ cross-section of the first region of the second semiconductor structure provided in an embodiment of the present application;

[0014] 2F is a schematic diagram of a YZ cross-section of the first region of a third semiconductor structure provided in an embodiment of the present application;

[0015] FIG3 is a schematic diagram of an XY plane of a fourth semiconductor structure provided in an embodiment of the present application;

[0016] FIG4 is a schematic diagram of a BB cross-section of the semiconductor structure junction region of FIG3 ;

[0017] FIG5 is a schematic flow chart of a method for manufacturing a semiconductor structure provided in an embodiment of the present application;

[0018] 6A to 6E are schematic diagrams of an XY plane of a manufacturing process of a stacked structure of a first semiconductor structure provided by an embodiment of the present application;

[0019] 7A to 7E are schematic diagrams of an XY plane of a manufacturing process of a stacked structure of a second semiconductor structure provided by an embodiment of the present application;

[0020] FIG8A is a schematic diagram of a YZ cross-section of the first region of the semiconductor structure of FIG6A ;

[0021] FIG8B is a schematic diagram of a BB cross-section of the semiconductor structure junction region of FIG6A;

[0022] 8C is a schematic diagram of a CC cross-section of the second region of the semiconductor structure of FIG. 6A ;

[0023] 8D is a schematic diagram of a DD cross-section of the second region of the semiconductor structure of FIG. 6A ;

[0024] 9A is a schematic diagram of a YZ cross-section of the first region of the semiconductor structure of FIG. 6E ;

[0025] FIG9B is a schematic diagram of a BB cross-section of the semiconductor structure interface region of FIG6E ;

[0026] 9C is a schematic diagram of a CC cross-section of the second region of the semiconductor structure of FIG. 6E ;

[0027] 9D is a schematic diagram of a DD cross-section of the second region of the semiconductor structure of FIG. 6E ;

[0028] FIG10 is a schematic diagram of a BB cross-section of the semiconductor structure interface region of FIG7E ;

[0029] 11A to 11F are schematic cross-sectional views of a manufacturing process of a second contact structure of a third semiconductor structure provided by an embodiment of the present application;

[0030] FIG12 is a schematic diagram of an exemplary system having a memory system according to an embodiment of the present application;

[0031] FIG13 is a schematic diagram of an exemplary memory card having a memory system according to an embodiment of the present application;

[0032] FIG. 14 is a schematic diagram of an exemplary solid-state drive having a memory system according to an embodiment of the present application.

[0033] In the accompanying drawings (which are not necessarily drawn to scale), like reference numerals may describe similar components in different views. Like reference numerals with different letter suffixes may represent different examples of similar components. The accompanying drawings generally illustrate various embodiments discussed herein by way of example and not limitation. DETAILED DESCRIPTION

[0034] To make the technical solutions and advantages of the embodiments of the present application clearer, the technical solutions of the present application will be further described in detail below with reference to the accompanying drawings and examples. Although the accompanying drawings show exemplary implementation methods of the present application, it should be understood that the present application can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0035] The following paragraphs describe the present application in more detail by way of example with reference to the accompanying drawings. The advantages and features of the present application will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are not to exact scale, and are only used to facilitate and clearly illustrate the embodiments of the present application.

[0036] It will be understood that the meanings of “on,” “over,” and “over” in this application should be interpreted in the broadest manner, such that “on” not only means being “on” something with no intervening features or layers (i.e., directly on something), but also includes being “on” something with intervening features or layers.

[0037] Furthermore, for ease of description, spatially relative terms such as "on," "over," "above," "upper," etc. may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0038] In the embodiments of this application, the term "substrate" refers to the material onto which subsequent material layers are added. The substrate itself can be patterned. The material added on top of the substrate can be patterned or can remain unpatterned. In addition, the substrate can include a variety of semiconductor materials, such as silicon, silicon germanium, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of non-conductive materials, such as glass, plastic, or sapphire wafers.

[0039] In the embodiments of the present application, the term "layer" refers to a portion of a material including an area with a thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range that is smaller than the range of a lower or upper structure. In addition, a layer may be a region of a homogeneous or inhomogeneous continuous structure having a thickness that is less than the thickness of a continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically and / or along an inclined surface. A layer may include multiple sublayers. For example, an interconnect layer may include one or more conductors and contact sublayers (wherein interconnect lines and / or via contacts are formed), and one or more dielectric sublayers.

[0040] In the embodiments of the present application, the terms "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0041] The semiconductor structure involved in the embodiments of this application is at least a portion of the structure that will be used in subsequent processes to form a final device. Here, the final device may include a memory, including but not limited to a three-dimensional memory such as 3D NAND. The following description will only use 3D NAND three-dimensional memory as an example. However, it should be noted that the description of the 3D NAND three-dimensional memory in the following embodiments is only for the purpose of illustrating this application and is not intended to limit the scope of this application.

[0042] As the number of stacked layers in three-dimensional memory devices increases, the etching depth of the contact holes used to form contacts also increases accordingly, which places higher demands on the contact hole etching process. To reduce process difficulty and simplify process steps, a self-aligned contact (SCT) structure has been proposed, in which each self-aligned contact structure is in electrical contact with the corresponding gate layer.

[0043] However, the manufacturing of SCT structures in three-dimensional memories still has the problems of high process difficulty, many steps, damage to the device structure and reduction of the device's structural stability.

[0044] 11A to 11F , a first contact structure and a plurality of second contact holes are formed in the second region, including:

[0045] Referring to Figure 11A, a plurality of first contact holes (taking the first contact holes CTH1-1, CTH1-2, and CTH1-3 as examples) penetrating the stacked structure are formed in the second area A2; wherein, the first contact hole CTH1-1 extends to the third material layer 322 above the first dielectric layer, and the first contact holes CTH1-2 and CTH1-3 extend to the insulating layer 102 above the second dielectric layer corresponding to one side of the first dielectric layer, respectively.

[0046] 11B , a spacer material layer 324 ′ is formed to cover at least the sidewalls and bottom surfaces of the plurality of first contact holes;

[0047] Referring to Figures 11C to 11D, the spacer material layer 324' and the third material layer 322 located at the bottom of the first contact hole CTH1-1 are removed in sequence, and the spacer material layer 324' and the insulating layer 102 located at the bottom of the first contact holes CTH1-2 and CTH1-3 are removed in sequence to obtain second contact holes (taking the second contact holes CTH1-11, CTH1-21, and CTH1-31 as examples).

[0048] The material of the insulating layer 102 includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, and other high-k dielectrics. The material of the insulating layer 102 can be the same as the material of the third material layer 322. The following description uses the example where both the material of the insulating layer 102 and the material of the third material layer 322 include silicon oxide.

[0049] The first contact structure and the second contact structure include a lead portion and a connecting portion; forming the first contact structure and the second contact structure (taking the first contact structure C1-1 and the second contact structures C1-2 and C1-3 as examples) includes:

[0050] 11D , a portion of the second dielectric layer 103 on the bottom surfaces of the second contact holes CTH1-21 and the second contact holes CTH1-31 is removed;

[0051] Referring to Figure 11E, a conductive material is formed on the bottom and side walls of the second contact hole CTH1-11, and a conductive material is formed at the position where the second dielectric layer is removed and on the side walls of the second contact hole; the conductive material on the bottom of the second contact hole CTH1-11 forms the connecting portion 302 of the first contact structure, and the conductive material on the side walls of the second contact hole CTH1-11 forms the lead-out portion 301 of the first contact structure; the conductive material at the position where the second dielectric layer is removed forms the connecting portion 302 of the second contact structure, and the conductive material on the side walls of the second contact hole forms the lead-out portion 301 of the second contact structure.

[0052] Referring to Figure 11A, compared with the thickness of the insulating layer 102 under the first contact holes CTH1-2 and CTH1-3, the thickness of the third material layer 322 under the first contact hole CTH1-1 is relatively thick, and it is difficult to control the thickness of the remaining third material layer 322 during the formation of the first contact hole CTH1-1.

[0053] Referring to Figures 11B to 11C, compared with the second contact holes CTH1-21 and CTH1-31 which can stop on the dielectric layer 103 under the second contact holes CTH1-21 and CTH1-31, since the thickness of the third material layer 322 under the first contact hole CTH1-1 is relatively thick, there is still a certain thickness of the third material layer 322 under the second contact hole CTH1-11, so that the second contact hole CTH1-11 cannot stop on the dielectric layer 103 under the second contact hole CTH1-11.

[0054] Referring to Figure 11D, compared with the partial removal of the dielectric layer 103 under the second contact holes CTH1-21 and CTH1-31, a space SP302 can be obtained at the position where the partial second dielectric layer on the bottom surface of the second contact hole is removed, and a certain thickness of the third material layer 322 still exists under the second contact hole CTH1-11, so that the second contact hole CTH1-11 cannot stop on the dielectric layer 103 under the second contact hole CTH1-11, and the partial dielectric layer 103 under the second contact hole CTH1-11 cannot be removed, and a space SP302 connected to the second contact hole CTH1-11 cannot be formed under the second contact hole CTH1-11.

[0055] Referring to Figure 11E, compared with the second contact structures C1-2 and C1-3 whose lead-out parts 301 and connecting parts 302 can be connected to the corresponding second gate layer through the connecting part 302, the lead-out parts 301 and connecting parts 302 of the first contact structure C1-1 cannot be connected to the corresponding first gate layer through the connecting part 302, resulting in the first gate layer being unable to or difficult to be led out by the first contact structure C1-1.

[0056] In order to solve at least one of the above-mentioned problems existing in the related art, embodiments of the present application provide a semiconductor structure and a manufacturing method thereof, and a memory system.

[0057] FIG1 is a schematic diagram of the XY plane of a first semiconductor structure provided in an embodiment of the present application. FIG2A is a schematic diagram of a YZ cross-section of a first region of the semiconductor structure of FIG1 ; FIG2B is a schematic diagram of a BB cross-section of a junction region of the semiconductor structure of FIG1 ; FIG2C is a schematic diagram of a CC cross-section of a second region of the semiconductor structure of FIG1 ; and FIG2D is a schematic diagram of a DD cross-section of the second region of the semiconductor structure of FIG1 .

[0058] FIG3 is a schematic diagram of the XY plane of the fourth semiconductor structure provided in an embodiment of the present application. FIG4 is a schematic diagram of the BB cross-section of the semiconductor structure interface region of FIG3 . The schematic diagram of the YZ cross-section of the first region of the semiconductor structure of FIG3 can be understood with reference to FIG2A , the schematic diagram of the CC cross-section of the second region of the semiconductor structure of FIG3 can be understood with reference to FIG2C , and the schematic diagram of the DD cross-section of the second region of the semiconductor structure of FIG3 can be understood with reference to FIG2D .

[0059] It should be noted that Figures 1 and 3 illustrate schematic diagrams of the XY plane corresponding to the first gate layer. To clearly illustrate the relative positional relationships of the first and second contact structures to the first and second gate layers, respectively, the projections of the first and second contact structures on the XY plane corresponding to the first gate layer are also shown in perspective. The first contact structure is connected to the first gate layer, and the second contact structure is connected to the corresponding second gate layer. The schematic diagram of the XY plane corresponding to the second gate layer can be understood with reference to the schematic diagram of the XY plane corresponding to the first gate layer.

[0060] Here and below, for ease of description in the embodiments of this application, the first and second directions are represented as two orthogonal directions parallel to the plane of the substrate (or substrate structure); the third direction is the stacking direction of the stacked structure, which is perpendicular to the plane of the substrate (or substrate structure). The first direction can be represented as the X direction in the drawings; the second direction can be represented as the Y direction in the drawings; and the third direction can be represented as the Z direction in the drawings.

[0061] With reference to FIG. 1 and FIG. 2A to FIG. 2D , and with reference to FIG. 3 and FIG. 4 , according to a first aspect of the present application, there is provided a semiconductor structure, including:

[0062] A stacked structure includes a first area A1, a second area A2, and an interface area A3 located between the first area A1 and the second area A2; the stacked structure includes gate layers and insulating layers 102 alternately stacked; the gate layer includes a first gate layer 101-1 and a plurality of second gate layers 101-2 to 101-N located on one side of the first gate layer 101-1; a first contact structure C1-1 is located in the interface area A3, extends, and is connected to the first gate layer 101-1;

[0063] A plurality of second contact structures C1-2 to C1-N are located in the second area A2 and extend and connect to the second gate layers 101-2 to 101-N of different layers respectively;

[0064] The size of the first contact structure C1 - 1 along the direction perpendicular to the stacking direction of the stacked structure is different from the sizes of the second contact structures C1 - 2 ˜ C1 -N along the direction perpendicular to the stacking direction.

[0065] Here and in the following description, the term "gate layer" includes the first gate layer and the second gate layer; the term "contact structure" includes the first contact structure and the second contact structure; and the term "dielectric layer" includes the first dielectric layer and the second dielectric layer. Here and in the following description, N is a natural number greater than or equal to 2.

[0066] In some embodiments, a dielectric layer 103 is further provided on the plane where the gate layer corresponding to the stack structure of the second area A2 is located;

[0067] 1 and 2B , the area around the location of the first contact structure C1-1 corresponds to the alternately stacked gate layers and insulating layers 102; referring to FIG1 and 2D , a portion of the area around the location of the second contact structures C1-2 to C1-N corresponds to the alternately stacked gate layers and insulating layers 102, and referring to FIG1 and 2C , the other portion corresponds to the alternately stacked dielectric layers 103 and insulating layers 102.

[0068] Exemplarily, the first contact structure C1-1 contacts the first gate layer corresponding to the area around the first contact structure C1-1; the second contact structures C1-2 to C1-N respectively contact the second gate layer corresponding to a portion around the area where the second contact structures C1-2 to C1-N are located.

[0069] In some embodiments, the semiconductor structure further comprises:

[0070] 1 and 2A , a plurality of channel structures CH penetrate the stacked structure of the first area A1 ;

[0071] A plurality of third contact structures C3 are located in the first area A1 and extend to and are connected to different channel structures CH respectively;

[0072] 1 and FIG. 2A and FIG. 2B , the first contact structure C1 - 1 and the third contact structure C3 have the same cross-sectional shape in a plane perpendicular to the stacking direction.

[0073] Exemplarily, the structures for achieving electrical connection in the first contact structure C1 - 1 and the third contact structure C3 have a solid columnar or hollow cylindrical cross-sectional shape in a plane perpendicular to the stacking direction.

[0074] The first contact structure C1-1 and the third contact structure C3 are set together to effectively control costs (for example, the first contact structure C1-1 and the third contact structure C3 can be obtained using the same mask layer (Mask), which can effectively control costs). The second gate layer 101-2~101-N is well led out by the second contact structure C1-2~C1-N, and the first gate layer 101-1 is well led out by the first contact structure C1-1.

[0075] In some embodiments, the semiconductor structure further comprises:

[0076] 1 and 2A , the select gate layer SL is located on the first gate layer 101 - 1 ;

[0077] a fourth contact structure C4 , located in the first area A1 , extending and connected to the select gate layer SL;

[0078] 1 and FIG. 2A and FIG. 2B , the first contact structure C1 - 1 and the fourth contact structure C4 have the same cross-sectional shape in a plane perpendicular to the stacking direction.

[0079] The first contact structure C1-1 and the fourth contact structure C4 are set together to effectively control costs (for example, the first contact structure C1-1 and the fourth contact structure C4 can be obtained using the same mask layer, which can effectively control costs). The second gate layer 101-2 to 101-N is well led out by the second contact structure C1-2 to C1-N, and the first gate layer 101-1 is well led out by the first contact structure C1-1.

[0080] In some embodiments, referring to FIG. 1 and FIG. 2A and FIG. 2B , a top surface of the first contact structure C1 - 1 is substantially flush with a top surface of the third contact structure C3 and / or the fourth contact structure C4 .

[0081] Exemplarily, the first contact structure C1-1, the third contact structure C3 and the fourth contact structure C4 are arranged together, so as to effectively control the cost (for example, the first contact structure C1-1, the third contact structure C3 and the fourth contact structure C4 can be obtained by using the same mask layer, which can effectively control the cost), the second gate layer 101-2~101-N is well led out by the second contact structure C1-2~C1-N, and the first gate layer 101-1 is well led out by the first contact structure C1-1.

[0082] In some embodiments, referring to FIG. 1 and FIG. 2B , FIG. 2C , and FIG. 2D , a dimension of the first contact structure C1 - 1 along a direction perpendicular to the stacking direction is smaller than a dimension of the second contact structures C1 - 2 ˜ C1 -N along the direction perpendicular to the stacking direction.

[0083] In some embodiments, referring to Figures 1 and 2B, 2C, and 2D, the size of the first contact structure C1-1 along the direction perpendicular to the stacking direction ranges from 100nm to 500nm; the size of the second contact structures C1-2 to C1-N along the direction perpendicular to the stacking direction ranges from 500nm to 3000nm.

[0084] In some embodiments, referring to FIG1 and FIG2A, FIG2B, FIG2C, and FIG2D, the material of the first contact structure C1-1 includes, but is not limited to, tungsten, cobalt, nickel, copper, aluminum, polysilicon, doped silicon, silicide, nitride, or any combination thereof. Exemplarily, the material of the first contact structure C1-1 may be tungsten. The materials of the second contact structures C1-2 through C1-N include, but are not limited to, tungsten, cobalt, nickel, copper, aluminum, polysilicon, doped silicon, silicide, nitride, or any combination thereof. Exemplarily, the material of the second contact structures C1-2 through C1-N may be tungsten.

[0085] In some embodiments, referring to FIG1 and FIG3 , the semiconductor structure further includes: a plurality of first gate line slit GSL1 structures and a second gate line slit GSL2 structure located between two adjacent first gate line slit GSL1 structures; the first gate line slit GSL1 structure extends from the first area A1 to the second area A2; the second gate line slit GSL2 structure extends from the first area A1 to the boundary area A3;

[0086] The first contact structure C1 - 1 is located on the extension line of the straight line where the second gate line gap GSL2 is located and is located near the end of the second gate line gap GSL2 structure.

[0087] Here and below, the gate line gap structure (including the first gate line gap GLS1 structure and the second gate line gap GLS2 structure) includes a gate line gap formed in the stacked structure and a filling material formed in the gate line gap, wherein the filling material may include polysilicon, silicon oxynitride, or carbon.

[0088] Compared with the first gate line gap GSL1 structure, the second gate line gap GSL2 structure is shorter, and the landing area of ​​the first contact structure C1-1 (understood as the area where the first contact structure C1-1 contacts the first gate layer 101-1) can be set at the position on the extension line EL of the second gate line gap GSL2 structure, and the area at the position on the extension line EL of the second gate line gap GSL2 structure can be effectively utilized, thereby effectively controlling costs. For example, since no pattern is set in the stacked structure at the position on the extension line EL of the second gate line gap GSL2 structure (for example, no dummy channel structure DCH / channel structure CH is set in the stacked structure at this position), or since the position on the extension line EL of the second gate line gap GSL2 structure serves as the landing area of ​​the first contact structure C1-1, the second gate line gap GSL2 can be used to form alternating stacked gate layers (including the first gate layer 101-1) and the insulating layer 102 around the position at the end of the second gate line gap GSL2 structure without changing the mask layer pattern of other related process layers. In this way, without changing the mask layer patterns of other related process layers, the area located on the extension line EL of the second gate line slit GSL2 structure is effectively utilized. The first gate layer 101-1 located at the end of the second gate line slit GSL2 structure can be used as the landing area for the first contact structure C1-1. Thus, only the mask pattern forming the first contact structure C1-1 needs to be adaptively changed to the landing area, and the first gate layer 101-1 can be well led out by the first contact structure C1-1. The second gate layers 101-2 to 101-N are well led out by the second contact structures C1-2 to C1-N, and the first gate layer 101-1 is well led out by the first contact structure C1-1.

[0089] In some embodiments, referring to FIG1 and FIG3 , the dielectric layer 103 corresponding to the stacked structure in the second area A2 is located between two adjacent first gate line gap GSL1 structures, and the gate layers corresponding to the stacked structure in the second area A2 are all located between the dielectric layer 103 and the corresponding first gate line gap GSL1 structure; the second contact structures C1-2 to C1-N are located on the extension line of the straight line where the second gate line gap GSL2 is located and between the two first gate line gap GSL1 structures; and a portion of the second contact structures C1-2 to C1-N located between the extension line and one first gate line gap GSL1 structure and another portion of the second contact structures C1-2 to C1-N located between the extension line and another first gate line gap GSL1 structure are arranged in parallel and in an alternating manner;

[0090] The second contact structures C1 - 2 ˜ C1 -N are connected to corresponding second gate layers 101 - 2 ˜ 101 -N at one side close to the first gate line gap GSL1 structure.

[0091] The second contact structures C1-2 to C1-N are evenly distributed on both sides close to the first gate line gap GSL1, which can increase the process window for forming the second contact structures C1-2 to C1-N, thereby effectively controlling the cost. The second gate layer 101-2 to 101-N is well led out by the second contact structures C1-2 to C1-N.

[0092] In some embodiments, referring to FIG3 , a dielectric layer 103 is further provided on the plane where the gate layer corresponding to the stacked structure in the junction area A3 is located; the gate layer and the dielectric layer 103 between the first gate line gap GSL1 structure and the second gate line gap GSL2 structure in the junction area A3 have an interface INF;

[0093] The interface INF is located between the first contact structure C1-1 and the second area A2; the semiconductor structure also includes at least one dummy channel structure DCH; the dummy channel structure DCH is located on the extension line of the straight line where the second gate line gap GSL2 extends and is located on at least one side of the first contact structure C1-1.

[0094] Compared with the first gate line gap GSL1 structure, the second gate line gap GSL2 structure is shorter (does not extend to the second area A2). The landing area of ​​the first contact structure C1-1 (understood as the area where the first contact structure C1-1 contacts the first gate layer 101-1) can be set at a position on the extension line EL of the second gate line gap GSL2 structure, and a virtual channel structure DCH can be provided in the stacking structure on at least one side of the first contact structure C1-1 to support the stacking structure near the landing area and prevent the stacking structure near the landing area from tilting or bending.

[0095] In some embodiments, referring to FIG. 1 , a dielectric layer 103 is further provided on the plane where the gate layer corresponding to the stacked structure in the junction area A3 is located; the gate layer and the dielectric layer 103 between the first gate line gap GSL1 structure and the second gate line gap GSL2 structure in the junction area A3 have an interface INF;

[0096] The interface INF is located between the first contact structure C1 - 1 and the first area A1 . Around the first contact structure C1 - 1 , along the extension line of the straight line where the second gate line gap GSL2 extends, are alternately stacked gate layers and insulating layers 102 .

[0097] In some embodiments, referring to FIG. 1 and FIG. 2C and FIG. 2D,

[0098] The first contact structure C1-1 extends to the first gate layer 101-1 along the stacking direction of the stack structure;

[0099] Each second contact structure C1-2~C1-N includes a lead-out portion 301 and a connecting portion 302; the lead-out portion 301 extends in a direction parallel to the stacking direction of the stacked structure, and one end is connected to a portion of the top surface of the connecting portion 302; the connecting portion 302 extends in a direction perpendicular to the stacking direction and is connected to the corresponding second gate layer 101-2~101-N.

[0100] In some embodiments, referring to FIG. 2C and FIG. 2D , the lead-out portion 301 and the connecting portion 302 are integrally formed.

[0101] In some embodiments, the first contact structure C1 - 1 includes a columnar conductive structure; and the lead-out portion 301 includes a tubular conductive structure.

[0102] FIG2E is a schematic diagram of a YZ cross-section of the first region of the second semiconductor structure provided in an embodiment of the present application. The semiconductor structure of FIG2E can be understood as a common source layer CSL obtained by subsequent processing based on FIG2A: the common source layer CSL is realized by the related process of using the gate line slits (first gate line slit GLS1 and / or second gate line slit GLS2).

[0103] Figure 2F is a schematic diagram of the YZ cross-section of the first region of the third semiconductor structure provided in an embodiment of the present application. The semiconductor structure of Figure 2F can be understood as a common source layer CSL obtained by performing subsequent processes on the basis of Figure 2A: the common source layer CSL is realized on the back side of the substrate 201. Referring to Figure 2E or Figure 2F, in some embodiments, the semiconductor structure further includes: a common source layer CSL. In some specific implementations, the common source layer CSL can be in contact with the channel layer 215 of the channel structure CH. In other specific implementations, the common source layer CSL can be in contact with the channel layer 315 of the dummy channel structure DCH. In some specific implementations, the material of the common source layer CSL includes but is not limited to tungsten, cobalt, nickel, copper, aluminum, polysilicon, doped silicon, silicide, nitride or any combination thereof. Exemplarily, the material of the common source layer CSL can be polysilicon.

[0104] In some embodiments, the first contact structure C1-1 and the second contact structure C1-2 ˜ C1-N are located on a first side of the channel structure CH, and the common source layer CSL is located on a second side of the channel structure CH. The first side and the second side are opposite sides in the extending direction of the channel structure CH.

[0105] Referring to Figure 2E or Figure 2F, in some embodiments, the first gate line gap GSL1 structure includes a common source isolation portion (not shown in Figure 2D) and a common source lead-out portion (not shown in Figure 2D) sequentially located on the sidewalls of the first gate line gap GSL1, and / or the second gate line gap GSL2 structure includes a common source isolation portion (not shown in Figure 2D) and a common source lead-out portion (not shown in Figure 2D) sequentially located on the sidewalls of the second gate line gap GSL2, wherein the common source lead-out portion extends into the common source layer CSL and contacts the common source layer CSL; the common source isolation portion is located between the gate layer and the common source lead-out portion. In some specific implementations, the material of the common source lead-out portion includes, but is not limited to, tungsten, cobalt, nickel, copper, aluminum, polysilicon, doped silicon, silicide, nitride, or any combination thereof. Exemplarily, the material of the common source lead-out portion can be polysilicon. In some specific embodiments, the material of the common source isolation portion includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, and other high dielectric constant (high-k) dielectrics. Exemplarily, the material of the common source isolation portion may be silicon oxide.

[0106] In each embodiment of the present application, the first contact structure C1-1 and the second contact structure C1-2 to C1-N are respectively arranged, and the first contact structure C1-1 and the second contact structure C1-2 to C1-N are respectively arranged in different areas (the first contact structure C1-1 is arranged in the third area A3, and the second contact structure C1-2 to C1-N are arranged in the second area A2), and the dimensions of the first contact structure C1-1 and the second contact structure C1-2 to C1-N along the direction perpendicular to the stacking direction are respectively set to be different, the second gate layer 101-2 to 101-N are well led out by the second contact structures C1-2 to C1-N, and the first gate layer 101-1 is well led out by the first contact structure C1-1.

[0107] The semiconductor structure provided in the embodiment of the present application is similar to the semiconductor structure manufactured by the manufacturing method of the semiconductor structure in the following embodiment. For the technical features not fully disclosed in the embodiment of the present application, please refer to the semiconductor structure manufactured by the manufacturing method of the following semiconductor structure for understanding, and no further details will be given here.

[0108] FIG5 is a flow chart of a method for manufacturing a semiconductor structure provided by an embodiment of the present application. Referring to FIG5 , according to a second aspect of the present application, a method for manufacturing a semiconductor structure is provided, comprising the following steps:

[0109] S501, forming a stack structure, the stack structure comprising a first region, a second region, and a boundary region between the first region and the second region; the stack structure comprising gate layers and insulating layers alternately stacked; the gate layer comprising a first gate layer and a plurality of second gate layers located on one side of the first gate layer;

[0110] S502, using a first process to form a first contact structure in the interface region; the first contact structure extends and is connected to the first gate layer;

[0111] S503, using a second process to form a plurality of second contact structures in the second region; the plurality of second contact structures respectively extend and are connected to different second gate layers;

[0112] The first process is different from the second process.

[0113] It should be understood that the steps shown in FIG5 are not exclusive, and other steps may be performed before, after or between any steps in the shown operation; the steps shown in FIG5 may be adjusted in order according to actual needs.

[0114] Figures 6A to 6E are schematic diagrams of the manufacturing process of the stacked structure of the first semiconductor structure provided in an embodiment of the present application in the XY plane. Figures 7A to 7E are schematic diagrams of the manufacturing process of the stacked structure of the second semiconductor structure provided in an embodiment of the present application in the XY plane. The steps shown in Figures 6A to 6E and 7A to 7E are not exclusive, and other steps may be performed before, after, or between any steps in the illustrated operations, and the order may be adjusted according to actual needs.

[0115] It should be noted that Figures 6A to 6D and 7A to 7D illustrate schematic diagrams of the XY plane corresponding to the first gate layer. Furthermore, to clearly illustrate the relative positional relationships between the first and second contact structures and the first and second gate layers, respectively, the projections of the first and second contact structures corresponding to the XY plane on the first gate layer are also shown. The schematic diagram of the XY plane corresponding to the second gate layer can be understood with reference to the schematic diagram of the XY plane corresponding to the first gate layer.

[0116] In some specific embodiments, the gate layers (including the first gate layer and the second gate layer) are formed simultaneously. Here and below, FIG6A to FIG6E and FIG7A to FIG7E are described using the XY plane corresponding to the position of the first gate layer as an example.

[0117] Figure 8A is a schematic diagram of the YZ cross-section of the first region of the semiconductor structure in Figure 6A or Figure 7A; Figure 8B is a schematic diagram of the BB cross-section of the junction region of the semiconductor structure in Figure 6A or Figure 7A; Figure 8C is a schematic diagram of the CC cross-section of the second region of the semiconductor structure in Figure 6A or Figure 7A; Figure 8D is a schematic diagram of the DD cross-section of the second region of the semiconductor structure in Figure 6A or Figure 7A.

[0118] Figure 9A is a schematic diagram of the YZ cross-section of the first region of the semiconductor structure in Figure 6E; Figure 9B is a schematic diagram of the BB cross-section of the junction region of the semiconductor structure in Figure 6E; Figure 9C is a schematic diagram of the CC cross-section of the second region of the semiconductor structure in Figure 6E; Figure 9D is a schematic diagram of the DD cross-section of the second region of the semiconductor structure in Figure 6E.

[0119] The schematic diagrams of the YZ cross-section of the first region of the semiconductor structure in Figures 6B to 6D, the schematic diagram of the BB cross-section of the junction region of the semiconductor structure, the schematic diagram of the CC cross-section of the second region of the semiconductor structure, and the schematic diagram of the DD cross-section of the second region of the semiconductor structure can be understood by referring to Figures 8A, 8B, 8C, and 8D, and / or Figures 9A, 9B, 9C, and 9D, respectively, and in combination with the corresponding process steps, and will not be repeated here or below.

[0120] FIG10 is a schematic diagram of a BB cross section of the semiconductor structure interface region of FIG7E . The schematic diagram of the YZ cross section of the first region of the semiconductor structure of FIG7E can be understood with reference to FIG9A , the schematic diagram of the CC cross section of the second region of the semiconductor structure of FIG7E can be understood with reference to FIG9C , and the schematic diagram of the DD cross section of the second region of the semiconductor structure of FIG7E can be understood with reference to FIG9D .

[0121] The schematic diagrams of the YZ cross-section of the first region of the semiconductor structure, the schematic diagrams of the CC cross-section of the second region of the semiconductor structure, and the schematic diagrams of the DD cross-section of the second region of the semiconductor structure in Figures 7B to 7D can be understood by referring to Figures 8A, 8C, 8D, and / or Figures 9A, 9C, 9D and the corresponding process steps respectively; the schematic diagrams of the BB cross-section of the second region of the semiconductor structure in Figures 7B to 7D can be understood by referring to Figure 8B, and / or Figure 10 and in combination with the corresponding process steps, and will not be repeated here or below.

[0122] Step S501 is executed to form a stacking structure.

[0123] 6A to 6E and 7A to 7E , in some embodiments, a stacked structure is formed, including:

[0124] forming a stacked structure comprising a first region, a second region, and a boundary region between the first region and the second region; the stacked structure comprising dielectric layers and insulating layers alternately stacked;

[0125] The dielectric layer in the first region, at least a portion of the dielectric layer in the boundary region, and at least a portion of the dielectric layer in the second region are replaced with a gate layer to obtain a stacked structure.

[0126] 6A and 8A, 8B, 8C, and 8D, a stacked structure is formed.

[0127] The stacked structure includes a plurality of alternately stacked insulating layers 102 and dielectric layers 103. The stacked structure includes a first area A1, a second area A2, and a boundary area A3 between the first area A1 and the second area A2.

[0128] 1 and 2A , in some embodiments, the first region A1 may be used to form a channel structure CH; the second region A2 may be used to form a second contact structure for leading out the second gate layer of the channel structure CH; and the junction region A3 may be used to form a first contact structure for leading out the first gate layer of the channel structure CH.

[0129] Referring to Figure 1, in some specific embodiments, the interface between the first area A1 and the junction area A3 can be an interface that passes through the end of the extension direction of the junction interface INF toward the first area A1 and extends along the Y direction; the interface between the second area A2 and the junction area A3 can be an interface that extends along the Y direction in the area between the second contact structure of the second area A2 closest to the first area A1 and the landing area of ​​the first contact structure.

[0130] Referring to Figure 3, in some specific embodiments, the interface between the first area A1 and the junction area A3 can be an interface that passes through the end of the second gate line gap GLS2 in the extension direction of the second area A2 and extends along the Y direction; the interface between the second area A2 and the junction area A3 can be an interface that extends along the Y direction in the area between the second contact structure of the second area A2 closest to the first area A1 and the junction interface INF.

[0131] In some specific embodiments, the material of the insulating layer 102 includes but is not limited to silicon oxide, silicon nitride, silicon oxynitride and other high dielectric constant (high-k) dielectrics; the material of the dielectric layer 103 includes but is not limited to nitride, silicon carbide, silicon and silicon germanium. In a specific embodiment, the dielectric layer 103 can be formed of silicon nitride (Si3N4); the insulating layer 102 can be formed of silicon oxide (SiO2), so that the stacked structure formed is a nitride-oxide (NO) stack. In some embodiments, the insulating layer 102 and the dielectric layer 103 can have the same thickness as each other or different thicknesses. In subsequent processes, at least a portion of the dielectric layer 103 can be removed, and the gate metal material can be filled in the removed position to form a first gate layer and a second gate layer (refer to Figures 9A to 9D above). The first gate layer and the second gate layer can include metal tungsten (W).

[0132] In some specific implementations, the insulating layer 102 and the dielectric layer 103 can be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or other processes.

[0133] In some specific embodiments, the stacked structure may be formed on a substrate structure SUBS, and the substrate structure SUBS may have a main surface (XY plane in the drawings) extending in a first direction and a second direction that are horizontal directions.

[0134] In some embodiments, the substrate structure SUBS can be selected based on the actual needs of the device. The substrate structure SUBS is a composite stacked structure, including a pad oxide layer 202, a bottom polysilicon layer 203, a buffer oxide layer 204, and a top polysilicon layer 205 stacked in sequence on a substrate 201 along a third direction (the Z direction in the drawings). The material of the substrate 201 may include a silicon (Si) substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate; the material of the pad oxide layer 202 may include silicon oxide, the material of the bottom polysilicon layer 203 may include polysilicon, the material of the buffer oxide layer 204 may include silicon oxide, and the material of the top polysilicon layer 205 may include polysilicon. In some specific implementations, the pad oxide layer 202 , the bottom polysilicon layer 203 , the buffer oxide layer 204 , and the top polysilicon layer 205 on the substrate 201 may be formed by a PVD process, a CVD process, or an ALD process.

[0135] The substrate structure SUBS formed in this way is suitable for performing epitaxial growth of silicon on the back side of the substrate 201 to form a silicon epitaxial layer (Selective Epitaxial Growth, SEG) in subsequent processes, and for implementing the extraction of the common source layer CSL (see Figures 2A to 2D above) on the back side of the substrate 201.

[0136] In some embodiments, the bottom polysilicon layer 203 can be removed through the gate line gaps (the first gate line gap GLS1 and / or the second gate line gap GLS2), and a portion of the blocking dielectric layer 212, the charge trapping layer 213, and the tunneling dielectric layer 214 (ONO film) of the channel structure CH can be removed to expose a portion of the channel layer 215 of the channel structure CH. Silicon epitaxial growth is then performed on the retained bottom polysilicon layer 203 to form a silicon epitaxial layer, thereby achieving a common source layer CSL in contact with the channel layer 215 of the channel structure CH. The resulting common source layer CSL can refer to the semiconductor structure of FIG. 2E .

[0137] In other embodiments, the substrate 201, the pad oxide layer 202, and a portion of the bottom polysilicon layer 203 can be removed sequentially from the back side of the substrate 201, as well as a portion of the blocking dielectric layer 212, the charge trapping layer 213, and the tunneling dielectric layer 214 (ONO film) of the channel structure CH, to expose a portion of the channel layer 215 of the channel structure CH. Silicon epitaxial growth is then performed on the retained bottom polysilicon layer 203 to form a silicon epitaxial layer, thereby forming a common source layer CSL in contact with the channel layer 215 of the channel structure CH. The resulting common source layer can refer to the semiconductor structure of FIG. 2F .

[0138] In some embodiments, the channel structure CH includes a blocking dielectric layer 212, a charge trapping layer 213, a tunneling dielectric layer 214, a channel layer 215, and a filling layer 216, which are sequentially stacked along the radial direction of the channel hole. In some specific embodiments, the blocking dielectric layer 212, the charge trapping layer 213, the tunneling dielectric layer 214, and the channel layer 215 are formed in this order along the sidewalls and bottom surface of the storage channel hole. The blocking dielectric layer 212 is used to block the outflow of charge from the storage layer and may be made of silicon oxide. The charge trapping layer 213 is used to capture and store charge and may be made of silicon nitride. Electrons from the channel layer 215 can tunnel into the charge trapping layer 213 through the tunneling dielectric layer 214 and may be made of silicon oxide. The channel layer 215 may be made of polysilicon. The filling layer 216 may be made of either silicon oxide or polysilicon, which is equivalent to replacing the filling layer with the same material as the channel layer 215. In some specific embodiments, the blocking dielectric layer 212 , the charge trapping layer 213 , the tunneling dielectric layer 214 , and the channel layer 215 are referred to as an ONOP film.

[0139] Referring to FIG8A , an embodiment of the present application provides a stacked structure including a first sub-stacked structure and a second sub-stacked structure formed on the first sub-stacked structure. A channel hole CHH in the stacked structure is formed in two steps: a first sub-channel hole CHH1 is etched in the first sub-stacked structure, and a second sub-channel hole CHH2 is etched in the second sub-stacked structure formed on the first sub-stacked structure. The first sub-channel hole CHH1 and the second sub-channel hole CHH2 are connected to form the channel hole CHH. The channel hole CHH in the memory device shown in FIG8A should not be construed as limiting the process for forming the channel hole CHH. In some specific embodiments, the process for forming the channel hole CHH is not limited thereto. The channel hole CHH can be formed in two steps or more steps, depending on actual needs. For example, the more dielectric layers and insulating layers alternately stacked in the stacked structure, the more sub-stacked structures (such as the first sub-stacked structure and the second sub-stacked structure, etc.) the stacked structure needs to comprise. Accordingly, the channel hole CHH in the stacked structure can be formed in more steps.

[0140] In some implementations, the channel hole CHH is formed by a photolithography-etching (LE) process.

[0141] Here and below, the etching (or removal) process used may include a wet etching process, a dry etching process, etc. For example, a plasma etching process. The deposition (or filling) process used may include a PVD process, a CVD process, or an ALD process. For example, a plasma enhanced chemical vapor deposition (PECVD) process is used.

[0142] 6A to 6E and 7A to 7E exemplarily illustrate two methods for obtaining a stacked structure, and the method for forming a stacked structure is not limited thereto.

[0143] 6A , 6B, 6C, 6D, and 6E, a stacked structure is formed.

[0144] 6A , in some embodiments, gate line gaps are formed in the stacked structure, and the gate line gaps include a plurality of first gate line gaps GLS1 and a second gate line gap GLS2 located between two adjacent first gate line gaps; the first gate line gaps GLS1 extend from the first area A1 to the second area A2; and the second gate line gaps GLS2 extend from the first area A1 to the boundary area A3.

[0145] Herein and hereinafter, the gate line slits (including the first gate line slit GLS1 and the second gate line slit GLS2 ) include gate line trenches formed in the stacked structure and filling materials formed in the gate line trenches, wherein the filling materials may include polysilicon, silicon oxynitride, or carbon.

[0146] 6B , in some embodiments, removing a portion of the dielectric layer 103 in the interface area A3 includes:

[0147] A second mask layer Mask2 is formed to cover the first area A1; and a portion of the dielectric layer 103 in the junction area A3 and a portion of the dielectric layer 103 in the second area A2 are removed together with the second gate line gap GLS2 in the junction area A3 and the first gate line gap GLS1 in the junction area A3 and the second area A2.

[0148] It should be noted that after forming the second mask layer Mask2 and before removing part of the dielectric layer 103 , it is necessary to remove the filling materials at the second gate line gap GLS2 in the junction area A3 and the first gate line gap GLS1 in the junction area A3 and the second area A2 .

[0149] Thus, a space SP1 is formed at the location of the dielectric layer 103 partially removed by the second gate line gap GLS2 in the junction area A3, and a space SP2 is formed at the location of the dielectric layer 103 partially removed by the first gate line gap GLS1 in the junction area A3 and the second area A2.

[0150] 6C , in some embodiments, removing the dielectric layer 103 in the first area A1 includes:

[0151] A fourth mask layer Mask4 is formed, and the fourth mask layer Mask4 covers the boundary area A3 and the second area A2; and the dielectric layer 103 of the first area A1 is removed by using the first gate line gap GLS1 and the second gate line gap GLS2 of the first area A1.

[0152] It should be noted that after forming the fourth mask layer Mask4 and before removing part of the dielectric layer 103 , the filling materials at the second gate line gap GLS2 and the first gate line gap GLS1 in the first area A1 need to be removed.

[0153] In this way, a space SP3 is formed at the position of the removed dielectric layer 103 in the first area A1.

[0154] It should be noted that before forming the fourth mask layer Mask4, it is necessary to form a filling material in the space SP1, the space SP2, the second gate line gap GLS2 in the junction area A3, and the first gate line gap GLS1 in the junction area A3 and the second area A2. The filling material may include polysilicon, silicon oxynitride, or carbon.

[0155] In some embodiments, the second mask layer Mask2 and the fourth mask layer Mask4 are complementary patterns. In some specific embodiments, the second mask layer Mask2 and the fourth mask layer Mask4 can be formed by exposing positive photoresist and negative photoresist respectively using one mask.

[0156] 6D , in some embodiments, the fourth mask layer Mask4 is removed, and the filling materials at the space SP1, the space SP2, the second gate line gap GLS2 at the junction area A3, and the first gate line gap GLS1 at the junction area A3 and the second area A2 are removed to obtain the interconnected space SP1, space SP2, and space SP3.

[0157] Here, the spaces SP1, SP2, and SP3 that are interconnected may be positions corresponding to the first gate layer and the second gate layer.

[0158] 6E , in some embodiments, conductive material is filled in the interconnected spaces SP1 , SP2 , and SP3 to obtain a first gate layer and a second gate layer.

[0159] It should be noted that, herein and hereinafter, the term "conductive material" includes, but is not limited to, tungsten, cobalt, nickel, copper, aluminum, polysilicon, doped silicon, silicide, nitride, or any combination thereof. Exemplarily, the conductive material includes, but is not limited to, tungsten. Exemplarily, the conductive material includes, but is not limited to, titanium nitride. Exemplarily, the conductive material includes, but is not limited to, polysilicon.

[0160] The materials of the first gate layer and the second gate layer include tungsten.

[0161] Furthermore, a filling material is formed at the second gate line gap GLS2 and the first gate line gap GLS1 , wherein the filling material may include polysilicon, silicon oxynitride, or carbon.

[0162] In this way, the dielectric layer in the first area A1 , at least a portion of the dielectric layer in the boundary area A3 , and at least a portion of the dielectric layer 103 in the second area A2 are replaced with the gate layer to obtain a stacked structure.

[0163] 7A , 7B, 7C, 7D, and 7E, a stacked structure is formed.

[0164] Referring to Figure 7A, in some embodiments, gate line gaps are formed in the stacked structure, and the gate line gaps include multiple first gate line gaps GLS1 and second gate line gaps GLS2 located between two adjacent first gate line gaps; the first gate line gaps GLS1 extend from the first area A1 to the second area A2; the second gate line gaps GLS2 extend from the first area A1 to the boundary between the junction area A3 and the first area A1.

[0165] Here, the gate line slits (including the first gate line slit GLS1 and the second gate line slit GLS2 ) include gate line trenches formed in the stacked structure and filling materials formed in the gate line trenches, wherein the filling materials may include polysilicon, silicon oxynitride, or carbon.

[0166] 7B , in some embodiments, removing a portion of the dielectric layer 103 in the interface area A3 includes:

[0167] A sixth mask layer Mask6 is formed to cover the first area A1 ; a portion of the dielectric layer 103 in the junction area A3 and a portion of the dielectric layer 103 in the second area A2 are removed together with the first gate line gap GLS1 in the second area A2 and the junction area A3 .

[0168] In some embodiments, the sixth mask layer Mask6 may cover the first area A1 or the first area A1 and a portion of the boundary area A3. Here and below, the sixth mask layer Mask6 covering the first area A1 and a portion of the boundary area A3 is used as an example for description.

[0169] It should be noted that after forming the sixth mask layer Mask6 and before removing a portion of the dielectric layer 103 , it is necessary to remove the filling material at the first gate line gap GLS1 in a portion of the boundary area A3 and the second area A2 .

[0170] In this way, a space SP2 is formed at a location where a portion of the dielectric layer 103 is removed through a portion of the boundary area A3 and the first gate line gap GLS1 of the second area A2.

[0171] 7C , in some embodiments, removing a portion of the dielectric layer 103 in the interface area A3 includes:

[0172] A third mask layer Mask3 is formed to cover the second area A2; a portion of the dielectric layer 103 in the junction area A3 is removed together with the dielectric layer 103 in the first area A1 using the first gate line gap GLS1 and the second gate line gap GLS2 between the first area A1 and the junction area A3.

[0173] In some embodiments, the third mask layer Mask3 may cover the second area A2, or may cover the second area A2 and a portion of the boundary area A3. Here and below, the third mask layer Mask3 covering the second area A2 and a portion of the boundary area A3 is used as an example for description.

[0174] It should be noted that after forming the third mask layer Mask3 and before removing part of the dielectric layer 103 , it is necessary to remove the filling material at the second gate line gap GLS2 in the first area A1 and at part of the boundary area A3 and the first gate line gap GLS1 in the first area A1 .

[0175] In this way, a space SP3 is formed at the position where the dielectric layer 103 of the first area A1 is removed, and a space SP1 is formed at the position where the dielectric layer 103 of the partial boundary area A3 is removed, thereby obtaining the space SP1 and the space SP3 connected to each other.

[0176] It should be noted that before forming the third mask layer Mask3, a filling material needs to be formed in the space SP2, the void, the boundary area A3 and the first gate line gap GLS1 of the second area A2. The filling material may include polysilicon, silicon oxynitride or carbon.

[0177] In some embodiments, the sixth mask layer Mask6 and the third mask layer Mask3 have complementary patterns. In some specific embodiments, the sixth mask layer Mask6 and the third mask layer Mask3 can be formed by exposing positive photoresist and negative photoresist respectively using one mask.

[0178] 7D , in some embodiments, the third mask layer Mask3 is removed, and the filling material in the space SP2 , part of the boundary area A3 , and the first gate line gap GLS1 in the second area A2 is removed to obtain interconnected spaces SP1 , SP2 , and SP3 .

[0179] Here, the spaces SP1, SP2, and SP3 that are interconnected may be positions corresponding to the first gate layer and the second gate layer.

[0180] 7E , in some embodiments, conductive material is filled in the interconnected spaces SP1 , SP2 , and SP3 to obtain a first gate layer and a second gate layer.

[0181] The materials of the first gate layer and the second gate layer include tungsten.

[0182] Furthermore, a filling material is formed at the second gate line gap GLS2 and the first gate line gap GLS1 , wherein the filling material may include polysilicon, silicon oxynitride, or carbon.

[0183] In this way, the dielectric layer in the first area A1 , at least a portion of the dielectric layer in the boundary area A3 , and at least a portion of the dielectric layer 103 in the second area A2 are replaced with the gate layer to obtain a stacked structure.

[0184] 7A , 7B, 7C, 7D, and 7E, in some embodiments, a portion of the dielectric layer 103 in the interface region A3 is removed together with the dielectric layer 103 in the first region A1 ; the method further includes:

[0185] Before removing part of the dielectric layer 103 in the junction area A3, at least one dummy channel structure DCH is formed around the location of the first contact structure; the dummy channel structure DCH is located on the extension line EL of the straight line where the second gate line gap GLS2 extends and is located on at least one side of the location of the first contact structure.

[0186] In some embodiments, the dummy channel structure DCH is not used or is disabled for implementing a storage function.

[0187] In some embodiments, the dummy channel structure DCH is located on an extension line EL of the straight line where the second gate line slit GLS2 extends and is located on both sides of the position where the first contact structure is located.

[0188] Exemplarily, the dummy channel structure DCH is located on an extension line EL of the straight line extending in the direction of the second gate line slit GLS2 and on both sides of the first contact structure, and is located in the gate layer. The projection of the dummy channel structure DCH within the plane where the gate layer is located is located on the gate layer. Exemplarily, the projection of the dummy channel structure DCH within the plane where the gate layer is located can also be located on the dielectric layer 103.

[0189] In some embodiments, the dummy channel structure DCH can be manufactured using the same process as the channel structure CH. For example, FIG8B shows a dummy channel structure DCH in a memory device provided in an embodiment of the present application. The dummy channel structure DCH can be understood with reference to the aforementioned channel structure CH (for example, the channel layer 315 of the dummy channel structure DCH can be understood with reference to the channel layer 215 of the channel structure CH), and no further details will be given here.

[0190] Compared with the first gate line gap, the second gate line gap is shorter (does not extend to the second area), and a landing area of ​​the first contact structure (understood as the area where the first contact structure contacts the first gate layer) can be set at a position on the extension line of the second gate line gap, and a virtual channel structure can be provided in the stacking structure on at least one side of the first contact structure to support the stacking structure near the landing area and prevent the stacking structure near the landing area from tilting or bending.

[0191] Step S502 is executed to form a first contact structure.

[0192] 9A and 9B , in some embodiments, the method further includes:

[0193] 9A , a plurality of channel structures CH of the stacked structure penetrating the first region and a plurality of third contact structures C3 extending and connected to different channel structures CH are formed;

[0194] 9B , in the process of forming the plurality of third contact structures C3 , the first contact structure C1 - 1 is formed.

[0195] 9A and 9B , in some embodiments, the method further includes:

[0196] 9A , a select gate layer SL and a fourth contact structure C4 extending and connected to the select gate layer SL are formed on at least the first gate layer 101 - 1 in the first region;

[0197] 9B , during the process of forming the fourth contact structure C4 , the first contact structure C1 - 1 is formed.

[0198] The select gate layer SL and part of the channel structure CH constitute a select transistor SG.

[0199] 9A and 9B , in some embodiments, a first process is used to form a first contact structure C1 - 1 , including:

[0200] Using the first mask layer, a first contact hole (not shown in FIG9B ) extending to a portion of the top surface of the first gate layer 101-1, a third contact hole (not shown in FIG9A ) extending to a portion of the top surface of the selection gate layer SL, and a fourth contact hole (not shown in FIG9A ) extending to a portion of the top surface of the selection gate layer SL are formed; conductive materials are respectively filled in the first contact hole and the third contact hole / the fourth contact hole to form a first contact structure C1-1 and a third contact hole C3 / the fourth contact hole C4.

[0201] In some embodiments, a first material layer 328 is formed on the select gate layer SL to protect the select gate layer SL. The first material layer 328 includes silicon nitride.

[0202] In some embodiments, the first material layer 328 forms an opening for forming a landing area for forming the fourth contact hole C4 (the area where the fourth contact hole C4 contacts the select gate layer SL), a second material layer 330 covers the first material layer 328 and the select gate layer SL, and the third contact hole C3 / fourth contact hole C4 are formed in the second material layer 330. The material of the second material layer 330 includes silicon oxide.

[0203] It can be understood that the first contact structure C1-1 and the third contact hole C3 can be formed using the same mask layer, the first contact structure C1-1 and the fourth contact hole C4 can be formed using the same mask layer, and the first contact structure C1-1, the third contact hole C3 and the fourth contact hole C4 can be formed using the same mask layer, which can effectively control costs.

[0204] Exemplarily, when the dimensions of the first contact structure C1-1, the third contact hole C3 and the fourth contact hole C4 along the direction perpendicular to the stacking direction range from 100nm to 500nm, the first contact structure C1-1, the third contact hole C3 and the fourth contact hole C4 can be formed using the same mask layer.

[0205] While the second gate layers 101 - 2 ˜ 101 -N are well led out by the second contact structures C1 - 2 ˜ C1 -N, the first gate layer 101 - 1 is well led out by the first contact structure C1 - 1 .

[0206] In some embodiments, the first contact structure C1 - 1 may be formed using a separate mask layer.

[0207] For example, when the difference in size between the first contact structure C1-1 and the third contact hole C3 along the direction perpendicular to the stacking direction is greater than 500 nm, or when the difference in size between the first contact structure C1-1 and the fourth contact hole C4 along the direction perpendicular to the stacking direction is greater than 500 nm, the first contact structure C1-1 can be formed using an independent mask layer to ensure that the first gate layer 101-1 is well led out by the first contact structure C1-1.

[0208] 6E and 9B, 7E and 10, in some embodiments,

[0209] A gate line gap is formed in the stacked structure, and the gate line gap includes a plurality of first gate line gaps and a second gate line gap GLS2 located between two adjacent first gate line gaps GLS1; the first gate line gap GLS1 extends from the first region to the second region; the second gate line gap GLS2 extends from the first region to the boundary region;

[0210] Forming a first contact structure C1-1 includes:

[0211] A first contact structure C1 - 1 is formed on an extension line EL of the straight line where the second gate line slit GLS2 is located and near an end of the second gate line slit GLS2 .

[0212] Compared with the first gate line gap GSL1, the second gate line gap GSL2 is shorter (does not extend to the second area A2), and the landing area of ​​the first contact structure C1-1 (understood as the area where the first contact structure C1-1 contacts the first gate layer 101-1) can be set at a position on the extension line EL of the second gate line gap GSL2. While the second gate layers 101-2 to 101-N are well led out by the second contact structures C1-2 to C1-N, the first gate layer 101-1 is well led out by the first contact structure C1-1.

[0213] In some specific embodiments, the material of the first contact structure C1-1 includes, but is not limited to, tungsten, cobalt, nickel, copper, aluminum, polysilicon, doped silicon, silicide, nitride, or any combination thereof. Exemplarily, the material of the first contact structure C1-1 may be tungsten.

[0214] Step S503 is executed to form a second contact structure.

[0215] 6E and 9D , and 7E , in some embodiments, the dielectric layer 103 corresponding to the stacked structure in the second area A2 is located between two adjacent first gate line gaps GLS1 , and the gate layers corresponding to the stacked structure in the second area A2 (including the first gate layer 101 - 1 and the second gate layers 101 - 2 to 101 -N) are all located between the dielectric layer and the corresponding first gate line gaps GLS1 ;

[0216] Forming the second contact structures C1-2 to C1-N includes:

[0217] Second contact structures C1-2 to C1-N are formed between the extension line EL of the straight line where the second gate line slit GLS2 is located and the two first gate line slits GLS1; and a portion of the second contact structures C1-2 to C1-N located between the extension line EL and one first gate line slit GLS1 is arranged in parallel and staggered with another portion of the second contact structures C1-2 to C1-N located between the extension line EL and another first gate line slit GLS1;

[0218] The second contact structures C1 - 2 ˜ C1 -N are connected to the corresponding second gate layers 101 - 2 ˜ 101 -N at one side thereof close to the first gate line gap GLS1 .

[0219] Here, N is a natural number greater than or equal to 2.

[0220] The second contact structures C1-2 to C1-N are evenly distributed on both sides close to the first gate line gap GSL1, which can increase the process window for forming the second contact structures C1-2 to C1-N. The second gate layers 101-2 to 101-N are well led out by the second contact structures C1-2 to C1-N.

[0221] 6D to 6E , or, referring to FIG. 7D to 7E , in some embodiments, the dielectric layer 103 includes a first dielectric layer and a plurality of second dielectric layers located on one side of the first dielectric layer;

[0222] Forming a gate layer (including a first gate layer 101-1 and a second gate layer 101-2 to 101-N) and a plurality of second contact structures C1-2 to C1-N, including: forming a plurality of second contact holes in the second region; the plurality of second contact holes respectively extending to different second dielectric layers;

[0223] Depositing a conductive material in the gate gap of the first region, the gate gap of the junction region and the second region and the plurality of second contact holes to obtain a gate layer and a plurality of second contact structures;

[0224] or,

[0225] Conductive material is deposited in the gate gap of the first region, in the boundary region and in the gate gap of the second region to obtain a gate layer; and conductive material is deposited in the plurality of second contact holes to obtain a plurality of second contact structures.

[0226] The first dielectric layer and the first gate are in the same layer, and the plurality of second dielectric layers on one side of the first dielectric layer and the corresponding second gates are in the same layer.

[0227] For example, referring to FIG6D , after obtaining the interconnected spaces SP1, SP2, and SP3, or during the process of forming the spaces SP1, SP2, and SP3, the filling materials of the plurality of second contact holes are removed to obtain the plurality of second contact holes interconnected with the spaces SP1, SP2, and SP3; referring to FIG6E , a conductive material is deposited in the gate gaps of the first region, the junction region, the gate gaps of the second region, and the plurality of second contact holes to obtain a gate layer and a plurality of second contact structures C1-2 to C1-N.

[0228] In this way, the plurality of second contact structures and the corresponding gate layer are formed integrally, which can save process steps.

[0229] Exemplarily, referring to Figure 6D, after obtaining the interconnected spaces SP1, space SP2, and space SP3, the filling material of the multiple second contact holes is retained; and after filling the interconnected spaces SP1, space SP2, and space SP3 with conductive material to obtain the first gate layer and the second gate layer, the filling material of the multiple second contact holes is removed to obtain multiple second contact holes.

[0230] 6E , a conductive material is deposited in the plurality of second contact holes to obtain a plurality of second contact structures C1 - 2 ˜ C1 -N.

[0231] In some specific embodiments, the material of the plurality of second contact structures C1-2 to C1-N includes, but is not limited to, tungsten, cobalt, nickel, copper, aluminum, polysilicon, doped silicon, silicide, nitride, or any combination thereof. Exemplarily, the material of the plurality of second contact structures C1-2 to C1-N may be tungsten.

[0232] In this way, the plurality of second contact structures and the corresponding gate layers are formed in separate steps, which can reduce the process difficulty.

[0233] 11A to 11F are cross-sectional schematic diagrams illustrating the manufacturing process of the second contact structure of the third semiconductor structure provided in an embodiment of the present application. Here, FIG11F can be understood as a CC cross-sectional schematic diagram of the second region of the semiconductor structure of FIG6E.

[0234] 11A to 11F , in some embodiments, forming a plurality of second contact holes in the second region includes:

[0235] 11A , a plurality of first contact holes (taking first contact holes CTH1 - 2 to CTH1 - 3 as an example) penetrating the stacked structure are formed in the second area A2 ; the plurality of first contact holes extend to the insulating layer 102 on different layers of the second dielectric layer, respectively.

[0236] 11B , a spacer material layer 324 ′ is formed to cover at least the sidewalls and bottom surfaces of the plurality of first contact holes;

[0237] 11C to 11D , the spacer material layer 324 ′ and the insulating layer 102 at the bottom of the plurality of first contact holes are removed in sequence to obtain second contact holes (taking the second contact holes CTH1-21 to CTH1-31 as examples); wherein the bottom surfaces of the second contact holes expose the corresponding second dielectric layer.

[0238] In some embodiments, the second contact structure includes a lead portion 301 and a connecting portion 302 ; forming the second contact structure (taking the second contact structures C1-2 to C1-3 as an example) includes:

[0239] 11D , a portion of the second dielectric layer at the bottom surface of the second contact hole is removed;

[0240] 11E , a conductive material is formed at the position where the second dielectric layer is removed and on the sidewalls of the second contact hole; the conductive material at the position where the second dielectric layer is removed forms a connecting portion 302 , and the conductive material on the sidewalls of the second contact hole forms an extraction portion 301 .

[0241] In some specific embodiments, the material of the lead portion 301 and the material of the connection portion 302 include, but are not limited to, tungsten, cobalt, nickel, copper, aluminum, polysilicon, doped silicon, silicide, nitride, or any combination thereof. For example, the material of the lead portion 301 and the material of the connection portion 302 may be tungsten.

[0242] Here, a portion of the second dielectric layer is removed from the bottom surface of the second contact hole to form a space SP302. Space SP302 (see FIG11D ) is connected to the second contact holes CTH1-21 to CTH1-31 (see FIG11C ). The resulting lead portion 301 and connecting portion 302 (see FIG11E ) are integrally formed.

[0243] Thus, the connection portion 302 of the second contact structure contacts the corresponding second gate layer. For example, with reference to FIG10D , the connection portion 302 of the second contact structure C1 -N contacts the corresponding second gate layer 101 -N.

[0244] The semiconductor structure obtained by the manufacturing method of the semiconductor structure provided in the embodiment of the present application is similar to the semiconductor structure in the above-mentioned embodiment. For the technical features not fully disclosed in the embodiment of the present application, please refer to the above-mentioned embodiment for understanding, and no further details will be given here.

[0245] According to a third aspect of the present application, a memory system is provided, comprising:

[0246] A semiconductor structure, wherein the semiconductor structure is the semiconductor structure of any one of the above embodiments;

[0247] A controller is connected to the semiconductor structure.

[0248] Here, the semiconductor structure can be a memory or a part of a memory. The following is a detailed description using the semiconductor structure as a memory as an example.

[0249] FIG12 shows a block diagram of an exemplary system 500 with memory according to some aspects of the present application. System 500 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device with storage therein. As shown in FIG12 , system 500 may include a host 508 and a memory system 502, and the memory system 502 has one or more memories 504 and a memory controller 506. The host 508 can be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 508 can be configured to send data to the memory 504 or receive data from the memory 504.

[0250] Memory 504 can be any memory disclosed herein. As described in detail below, memory 504 (e.g., NAND flash memory (e.g., three-dimensional (3D) NAND flash memory)) can have reduced leakage current from driver transistors (e.g., string drivers) coupled to unselected word lines during erase operations, which allows for further size reduction of the driver transistors.

[0251] According to some embodiments, the memory controller 506 is coupled to the memory 504 and the host 508 and is configured to control the memory 504. The memory controller 506 can manage data stored in the memory 504 and communicate with the host 508. In some embodiments, the memory controller 506 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 506 is designed to operate in a high duty cycle environment, such as an SSD or an embedded multimedia card (eMMC), which is used as data storage for mobile devices such as smartphones, tablet computers, laptop computers, etc., as well as enterprise storage arrays.

[0252] The memory controller 506 can be configured to control operations of the memory 504, such as read, erase, and program operations. The memory controller 506 can also be configured to manage various functions related to data stored or to be stored in the memory 504, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 506 is also configured to process error correction code (ECC) on data read from or written to the memory 504. The memory controller 506 can also perform any other suitable functions, such as formatting the memory 504. The memory controller 506 can communicate with an external device (e.g., a host 508) according to a specific communication protocol. For example, the memory controller 506 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Mini Interface (SCSI) protocol, Enhanced MiniDisk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, Firewire protocol, etc.

[0253] The memory controller 506 and the one or more memories 504 can be integrated into various types of storage devices, for example, included in the same package (e.g., a universal flash storage (UFS) package or an eMMC package). In other words, the memory system 502 can be implemented and packaged into different types of terminal electronic products.

[0254] In one example as shown in FIG13 , the memory controller 506 and the single memory 504 can be integrated into a memory card 602. The memory card 602 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. The memory card 602 may also include a memory card connector 604 that couples the memory card 602 to a host (e.g., the host 508 in FIG12 ).

[0255] In another example, as shown in FIG14 , the memory controller 506 and the plurality of memories 504 can be integrated into an SSD 606. The SSD 606 can also include an SSD connector 608 that couples the SSD 606 to a host (e.g., the host 508 in FIG12 ). In some embodiments, the storage capacity and / or operating speed of the SSD 606 is greater than the storage capacity and / or operating speed of the memory card 602 (as shown in FIG13 ).

[0256] The features disclosed in the several method or device embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0257] Those skilled in the art will appreciate that the above-described embodiments are specific examples of implementing the present application. In actual applications, various modifications may be made to the embodiments in form and detail without departing from the spirit and scope of the present application. Any modifications or substitutions that can be readily conceived by those skilled in the art within the technical scope disclosed in the present application shall be included within the scope of protection of the present application. Industrial Applicability

[0258] Embodiments of the present application provide a semiconductor structure, a method for manufacturing the same, and a memory system. The semiconductor structure comprises a first contact structure and a second contact structure, each of which is separately disposed. The first contact structure is disposed in a third region, and the second contact structure is disposed in a second region. Furthermore, the first contact structure and the second contact structure are configured to have different dimensions perpendicular to the stacking direction. The second gate layer is effectively led out by the second contact structure, and the first gate layer is effectively led out by the first contact structure.

Claims

1. A semiconductor structure comprising: A stacked structure, comprising a first region, a second region and a junction region between the first region and the second region; the stacked structure comprises gate layers and insulating layers alternately stacked; the gate layers comprise a first gate layer and a plurality of second gate layers located on one side of the first gate layer; a first contact structure, located in the junction region, extending and connected to the first gate layer; A plurality of second contact structures, located in the second region, respectively extending and connected to different layers of the second gate layer; The dimension of the first contact structure along a direction perpendicular to the stacking direction of the stacked structure is different from the dimension of the second contact structure along a direction perpendicular to the stacking direction.

2. The semiconductor structure according to claim 1, wherein: A dielectric layer is also provided on the plane where the gate layer corresponding to the stacked structure of the second region is located; The area around the location of the first contact structure corresponds to the alternately stacked gate layer and the insulating layer; a portion of the area around the location of the second contact structure corresponds to the alternately stacked gate layer and the insulating layer, and another portion corresponds to the alternately stacked dielectric layer and the insulating layer.

3. The semiconductor structure according to claim 1 or 2, wherein: The semiconductor structure further comprises: A plurality of channel structures penetrating the stacked structure of the first region; A plurality of third contact structures, located in the first region, respectively extending and connected to different channel structures; The first contact structure and the third contact structure have the same cross-sectional shape in a plane perpendicular to the stacking direction.

4. The semiconductor structure according to any one of claims 1 to 3, wherein: The semiconductor structure further comprises: A selection gate layer, located on the first gate layer; a fourth contact structure, located in the first region, extending and connected to the select gate layer; The first contact structure and the fourth contact structure have the same cross-sectional shape in a plane perpendicular to the stacking direction.

5. The semiconductor structure according to claim 3 or 4, wherein: A top surface of the first contact structure is substantially flush with a top surface of the third contact structure and / or a top surface of the fourth contact structure.

6. The semiconductor structure according to claim 3 or 4, wherein: A dimension of the first contact structure along a direction perpendicular to the stacking direction is smaller than a dimension of the second contact structure along a direction perpendicular to the stacking direction.

7. The semiconductor structure according to claim 2, wherein: The semiconductor structure further includes: a plurality of first gate line gap structures and a second gate line gap structure located between two adjacent first gate line gap structures; the first gate line gap structure extends from the first region to the second region; the second gate line gap structure extends from the first region to the boundary region; The first contact structure is located on the extension line of the straight line where the second gate line gap is located and is located near the end of the second gate line gap structure.

8. The semiconductor structure according to claim 7, wherein: The dielectric layer corresponding to the stacked structure in the second region is located between two adjacent first gate line gap structures, and the gate layers corresponding to the stacked structure in the second region are all located between the dielectric layer and the corresponding first gate line gap structure; the second contact structure is located on the extension line of the straight line where the second gate line gap is located and between the two first gate line gap structures; and a portion of the second contact structure located between the extension line and one of the first gate line gap structures and another portion of the second contact structure located between the extension line and another of the first gate line gap structures are arranged in parallel and staggered manner; A side of the second contact structure close to the first gate line gap structure is connected to the corresponding second gate layer.

9. The semiconductor structure according to claim 7 or 8, wherein: A dielectric layer is also provided on the plane where the gate layer corresponding to the stacked structure in the junction area is located; the gate layer and the dielectric layer between the first gate line gap structure and the second gate line gap structure in the junction area have an interface; The interface is located between the first contact structure and the second region; the semiconductor structure further includes at least one dummy channel structure; the dummy channel structure is located on the extension line of the straight line where the second gate line gap extends and is located on at least one side of the first contact structure; or, The interface is located between the first contact structure and the first region; the first contact structure is surrounded by gate layers and insulating layers alternately stacked on an extension line of a straight line along the extension direction of the second gate line gap.

10. The semiconductor structure according to claim 1, wherein: The first contact structure extends to the first gate layer along the stacking direction of the stack structure; Each of the second contact structures includes a lead-out portion and a connecting portion; the lead-out portion extends in a direction parallel to the stacking direction of the stacking structure, and one end is connected to a portion of the top surface of the connecting portion; the connecting portion extends in a direction perpendicular to the stacking direction and is connected to the corresponding second gate layer.

11. A method for manufacturing a semiconductor structure, comprising: forming a stacked structure, the stacked structure comprising a first region, a second region, and a boundary region between the first region and the second region; The stacked structure comprises gate layers and insulating layers alternately stacked; the gate layers comprise a first gate layer and a plurality of second gate layers located on one side of the first gate layer; Using a first process, forming a first contact structure in the junction area; the first contact structure extends and is connected to the first gate layer; A second process is used to form a plurality of second contact structures in the second region; the plurality of second contact structures respectively extend and are connected to the second gate layers at different layers; The first process is different from the second process.

12. The manufacturing method according to claim 11, wherein: The method further comprises: forming a plurality of channel structures penetrating the stacked structure of the first region and a plurality of third contact structures extending and connected to different channel structures; Wherein, during the process of forming the plurality of third contact structures, the first contact structure is formed.

13. The manufacturing method according to claim 11 or 12, wherein: The method further comprises: forming a selection gate layer and a fourth contact structure extending and connected to the selection gate layer at least on the first gate layer of the first region; Wherein, during the process of forming the fourth contact structure, the first contact structure is formed.

14. The manufacturing method according to claim 12 or 13, wherein: The first contact structure is formed by using a first process, including: A first mask layer is used to form a first contact hole extending to a portion of the top surface of the first gate layer, a third contact hole extending to a portion of the top surface of the selection gate layer, and a fourth contact hole extending to a portion of the top surface of the selection gate layer; and conductive materials are respectively filled in the first contact hole and the third contact hole / the fourth contact hole to form the first contact structure and the third contact hole / the fourth contact hole.

15. The manufacturing method according to claim 11, wherein: Forming the stacked structure includes: Forming a stacked structure, comprising a first region, a second region and a boundary region between the first region and the second region; the stacked structure comprises dielectric layers and insulating layers alternately stacked; The dielectric layer in the first region, at least part of the dielectric layer in the boundary region, and at least part of the dielectric layer in the second region are replaced with the gate layer to obtain the stacked structure.

16. The manufacturing method according to claim 15, wherein: The stacked structure is provided with gate line gaps, the gate line gaps comprising a plurality of first gate line gaps and a second gate line gap located between two adjacent first gate line gaps; the first gate line gaps extend from the first region to the second region; The second gate line gap extends from the first region to the boundary region; The forming of the first contact structure comprises: The first contact structure is formed on an extension line of the straight line where the second gate line gap is located and at a position close to an end of the second gate line gap.

17. The manufacturing method according to claim 16, wherein: The dielectric layer corresponding to the stacked structure in the second region is located between two adjacent first gate line gaps, and the gate layers corresponding to the stacked structure in the second region are all located between the dielectric layer and the corresponding first gate line gaps; The forming of the second contact structure comprises: The second contact structure is formed on an extension line of the straight line where the second gate line gap is located and between two of the first gate line gaps; Furthermore, a portion of the second contact structure located between the extension line and one of the first gate line gaps and another portion of the second contact structure located between the extension line and another of the first gate line gaps are arranged in parallel and staggered; A side of the second contact structure close to the first gate line gap is connected to the corresponding second gate layer.

18. The manufacturing method according to claim 16 or 17, wherein: Removing part of the dielectric layer in the interface area includes: forming a second mask layer, the second mask layer covering the first area; removing a portion of the dielectric layer in the junction area and a portion of the dielectric layer in the second area together by using the second gate line gap in the junction area and the first gate line gap in the junction area and the second area; or, A third mask layer is formed, the third mask layer covers the second area; and a portion of the dielectric layer in the junction area is removed together with the dielectric layer in the first area by using the first gate line gap between the first area and the junction area and the second gate line gap between the first area and the junction area.

19. The manufacturing method according to claim 18, wherein: Part of the dielectric layer in the interface area is removed together with the dielectric layer in the first area; the method further comprises: Before removing part of the dielectric layer in the junction area, at least one dummy channel structure is formed around the location of the first contact structure; the dummy channel structure is located on the extension line of the straight line where the second gate line gap extends and on at least one side of the location of the first contact structure.

20. A memory system, wherein: include: A semiconductor structure, wherein the semiconductor structure is the semiconductor structure according to any one of claims 1 to 10; A controller is connected to the semiconductor structure.

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