Light emitting pixel structure system for improved light emission efficiency and method of manufacturing the same

Abstract

The application discloses a pixel structure for improving luminous efficiency. The pixel structure comprises a pixel lens, a negative electrode pad layer, a conductive semiconductor layer, a quantum well, an isolation layer, a positive electrode layer, a dielectric layer and an integrated circuit (IC) chip layer from top to bottom, and the quantum well is arranged in the conductive semiconductor layer. A three-side covering reflection layer is arranged between the lower surface of the conductive semiconductor layer and the top of the positive electrode layer. The conductive semiconductor layer comprises an inverted trapezoidal semiconductor part and a continuous planarization layer. The inclined surfaces on both sides of the inverted trapezoidal semiconductor part converge in the direction of the pixel lens and reflect the light emitted by the quantum well. And the negative electrode pad layer is arranged on the continuous planarization layer.

Description

TECHNICAL FIELD

[0001] The present application relates generally to the field of display technology, and in particular to a light emitting pixel structure for reducing light blocking effect and improving light reflection efficiency and a manufacturing process thereof. BACKGROUND

[0002] Display technology is becoming increasingly important in today's commercial electronic devices. These display panels are widely used in fixed large screens such as liquid crystal display televisions (LCD TVs) and organic light emitting diode televisions (OLED TVs), as well as portable electronic devices such as laptops, smartphones, tablets and wearable electronic devices.

[0003] Light emitting diode (LED) chips generally include organic light emitting diode (OLED) chips, mini light emitting diode (sub-millimeter light emitting diode) chips, or micro LED (micron light emitting diode) chips, etc. LEDs are widely used in the lighting field. As LED display screens gradually penetrate into the high-end market, the light emitting efficiency requirements of LED display screen devices are also increasingly high.

[0004] Pixels are composed of small blocks of images, and the small blocks have clear positions and are assigned color values, and the color and position of the small blocks determine the appearance of the image. Pixels can be regarded as indivisible units or elements in the entire image. Indivisible means that pixels cannot be further cut into smaller units or elements that exist in a single color unit. Each dot matrix image contains a certain number of pixels, which determine the size of the image presented on the screen.

[0005] Some embodiments disclose a light emitting diode unit including a plurality of pixels for a display and a display device having the light emitting diode unit. The embodiment discloses (1) a plurality of pixels, wherein each pixel includes a first light emitting unit, a second light emitting unit, and a third light emitting unit, and each unit includes a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer, respectively; (2) the third light emitting unit is electrically connected to the first light emitting unit, so that the first light emitting unit is independently driven by the third light emitting unit; (3) a second wavelength converter that converts the wavelength of light emitted from the second light emitting unit; and (4) a third wavelength converter that converts the wavelength of light emitted from the third light emitting unit, wherein the third wavelength converter converts the wavelength of light to a longer wavelength than the second wavelength converter, the second light emitting unit has a light emitting area larger than the light emitting area of the first light emitting unit, and the third light emitting unit has a light emitting area larger than the light emitting area of the second light emitting unit. Since the light emitting diode unit including a plurality of pixels is used, the light emitting unit can be easily attached to the substrate.

[0006] However, the pixel structure in these embodiments has the following technical problem. Since the light emitted by the light emitting unit is emitted to the periphery of the light emitting unit, the light emitted by the display device or the near-eye augmented reality (AR) device can be limited to the light emitted by the light emitting unit toward the lens direction. At the same time, a light blocking situation can exist between the light emitting unit and the lens, so that the brightness of the light emitted by the light emitting unit received by the lens accounts for only 50% or less of the light emitted by the light emitting unit in the pixel. Therefore, the working efficiency of the light emitting unit is low, and needs to be improved.

[0007] Therefore, it is desirable to provide a light emitting structure for a display panel that solves the above-mentioned drawbacks and the like. SUMMARY

[0008] There is a need for improved display device designs that improve upon and help solve the problems and drawbacks of conventional display systems as described above. In particular, there is a need for display panels with improved light efficiency and better images.

[0009] The present application relates to the technical field of display, and discloses a pixel structure for reducing light blocking effect and improving light reflection efficiency and a manufacturing process of the pixel structure. The technical problem of low light conversion efficiency of the current pixel light emitting unit is solved.

[0010] The present application includes, but is not limited to, the following exemplary embodiments.

[0011] Some exemplary embodiments of the present application include a micro light emitting pixel structure. The micro light emitting pixel structure includes: a conductive semiconductor layer, wherein the conductive semiconductor layer has an inverted trapezoidal shape and includes a continuous planarization layer at the top of the inverted trapezoidal shape; a quantum well layer for light emission, wherein the quantum well layer is within the conductive semiconductor layer; a three-side covering reflection layer below the conductive semiconductor layer, wherein the material of the three-side covering reflection layer is Ag; a negative electrode pad layer electrically connected to the conductive semiconductor layer; a positive electrode layer electrically connected to the conductive semiconductor layer; and an integrated circuit (IC) chip layer electrically connected to the positive electrode layer.

[0012] Some exemplary embodiments of the present application include a micro light emitting pixel structure. The micro light emitting pixel structure includes: a conductive semiconductor layer, wherein the conductive semiconductor layer has an inverted trapezoidal shape; a quantum well layer for light emission, wherein the quantum well layer is within the conductive semiconductor layer; a three-side covering reflection layer below the conductive semiconductor layer, wherein the material of the three-side covering reflection layer is Ag; an isolation layer between the conductive semiconductor layer and the three-side covering reflection layer, wherein the material of the isolation layer is Al 2O3 or Si 3N4; a negative electrode pad layer electrically connected to the conductive semiconductor layer; a positive electrode layer electrically connected to the conductive semiconductor layer; and an integrated circuit (IC) chip layer electrically connected to the positive electrode layer.

[0013] In some example embodiments or any combination of the example embodiments of the micro light emitting pixel structure, the three-side covered reflective layer includes: a middle conductive section in contact with the positive electrode layer and the conductive semiconductor layer; two side reflective sections in contact with the isolation layer; and two edge reflective sections in contact with the isolation layer; wherein the three-side covered reflective layer forms an inverted trapezoidal shape around the quantum well layer.

[0014] In some example embodiments or any combination of the example embodiments of the micro light emitting pixel structure, the quantum well layer is enclosed within the inverted trapezoidal shape of the conductive semiconductor layer, such that light from the quantum well is focused towards the top direction of the light emitting pixel structure.

[0015] In some example embodiments or any combination of the example embodiments of the micro light emitting pixel structure, the isolation layer forms an inverted trapezoidal shape around the quantum well layer.

[0016] In some example embodiments or any combination of the example embodiments of the micro light emitting pixel structure, the conductive semiconductor layer includes a continuous planarization layer on top of the inverted trapezoidal shape.

[0017] In some example embodiments or any combination of the example embodiments of the micro light emitting pixel structure, the continuous planarization layer covers the entire surface of the micro light emitting pixel structure and extends to adjacent micro light emitting pixel structures.

[0018] In some example embodiments or any combination of the example embodiments of the micro light emitting pixel structure, the micro light emitting pixel structure further includes an isolation layer between the conductive semiconductor layer and the three-side covered reflective layer, wherein the material of the isolation layer is AI2O3 or Si3N4.

[0019] In some example embodiments or any combination of the example embodiments of the micro light emitting pixel structure, a negative electrode pad layer is formed above the continuous planarization layer and is hollowed in the area above the quantum well, such that the light emitted by the quantum well is not blocked by the negative electrode pad layer.

[0020] In some example embodiments or any combination of the example embodiments of the micro light emitting pixel structure, the micro light emitting pixel structure further includes a dielectric layer between the three-side covered reflective layer and the IC chip layer, wherein the dielectric layer includes a top dielectric layer made of Si3N4 covering the surface of the three-side covered reflective layer and a bottom dielectric layer made of SiO2.

[0021] In some example embodiments or any combination of the example embodiments of the micro light emitting pixel structure, the positive electrode layer includes an upper epitaxial positive electrode and a bottom chip positive electrode, the upper epitaxial positive electrode is located within the dielectric layer, and the bottom chip positive electrode is located within the IC chip layer.

[0022] In some example embodiments of the micro light emitting pixel structure or any combination of the example embodiments, the IC chip layer includes a top chip dielectric layer and a bottom chip dielectric layer.

[0023] In some example embodiments of the micro light emitting pixel structure or any combination of the example embodiments, the IC chip layer including the bottom chip anode is in contact with the dielectric layer including the top epitaxial anode.

[0024] In some example embodiments of the micro light emitting pixel structure or any combination of the example embodiments, the micro light emitting pixel structure further includes a pixel lens located above the conductive semiconductor layer.

[0025] Some example embodiments of the present disclosure include a method of manufacturing a micro light emitting pixel structure, the method comprising: providing an epitaxial wafer including a conductive semiconductor layer and a quantum well layer for light emission, wherein the quantum well layer is within the conductive semiconductor layer; etching the conductive semiconductor layer with the quantum well layer into an inverted trapezoidal shape; forming an isolation layer on a bottom surface of the conductive semiconductor layer, wherein a material of the isolation layer is AI2O3 or Si3N4; forming a three-sided coverage reflective layer on a bottom surface of a middle conductive portion of the three-sided coverage reflective layer, wherein a material of the three-sided coverage reflective layer is Ag; forming a first anode layer on a bottom surface of the middle conductive portion of the three-sided coverage reflective layer; bonding an integrated circuit (IC) chip layer to the first anode layer; and forming a cathode pad layer on an upper surface of the conductive semiconductor layer.

[0026] In some example embodiments of the method of manufacturing a micro light emitting pixel structure or any combination of the example embodiments, the method further includes, after forming the three-sided coverage reflective layer and before forming the first anode layer, forming a dielectric layer between the three-sided coverage reflective layer and the IC chip layer, wherein the dielectric layer includes a top dielectric layer made of Si3N4 covering a surface of the three-sided coverage reflective layer, and a bottom dielectric layer made of SiO2.

[0027] In some example embodiments of the method of manufacturing a micro light emitting pixel structure or any combination of the example embodiments, etching the conductive semiconductor layer with the quantum well layer further includes: leaving a continuous planarization layer on a top portion of the inverted trapezoidal shape in the conductive semiconductor layer.

[0028] In some example embodiments of the method of manufacturing a micro light emitting pixel structure or any combination of the example embodiments, the epitaxial wafer includes a sapphire substrate layer, and after bonding the IC chip layer and before forming the cathode pad layer, the method further includes removing the sapphire substrate layer.

[0029] In some example embodiments or any combination of example embodiments of the method of fabricating a micro light emitting pixel structure, forming the dielectric layer includes etching the dielectric layer to form an opening for depositing the first positive electrode layer.

[0030] In some example embodiments or any combination of example embodiments of the method of fabricating a micro light emitting pixel structure, forming the dielectric layer includes etching the dielectric layer to form an opening for depositing the first positive electrode layer.

[0031] In some example embodiments or any combination of example embodiments of the method of fabricating a micro light emitting pixel structure, bonding includes aligning bonding the IC chip layer embedded with the second positive electrode layer to the bottom surface of the dielectric layer embedded with the first positive electrode layer, wherein the first positive electrode layer is an upper epitaxial positive electrode and the second positive electrode layer is a system-on-chip positive electrode.

[0032] In some example embodiments or any combination of example embodiments of the method of fabricating a micro light emitting pixel structure, forming the negative electrode pad layer includes using a lift-off process to form a hollow shape in the negative electrode pad layer in a region above the quantum well such that light emitted from the quantum well is not blocked by the negative electrode pad layer.

[0033] In some example embodiments or any combination of example embodiments of the method of fabricating a micro light emitting pixel structure, the method further includes forming a pixel lens over the conductive semiconductor layer after forming the negative electrode pad layer, and aligning with the hollow shape in the negative electrode pad.

[0034] To solve the problem of low light efficiency conversion in traditional light emitting units, the present application achieves the purpose of improving light efficiency through the design inside the pixel structure.

[0035] In some example embodiments, the present application provides the following technical aspects:

[0036] In some embodiments, a pixel structure for reducing light blocking effects and improving light reflection efficiency includes, from top to bottom or from outside to inside, a pixel lens, a negative electrode pad layer, a conductive semiconductor layer, a quantum well, an isolation layer, a positive electrode layer, a dielectric layer, and an integrated circuit (IC) chip layer, wherein the quantum well is arranged in the conductive semiconductor layer.

[0037] In some embodiments, a three-sided covering reflective layer is arranged between a lower surface of the conductive semiconductor layer and a top of the positive electrode layer, and the three-sided covering reflective layer covers and conforms to a shape of a bottom surface of the conductive semiconductor layer, a side surface, and an upper surface, respectively.

[0038] In some embodiments, the conductive semiconductor layer includes an inverted-trapezoidal semiconductor portion and a continuous planarization layer. The quantum well is located inside the inverted-trapezoidal semiconductor portion. The inverted-trapezoidal semiconductor portion is divided into a P-GaN portion at the bottom and an N-GaN portion at the top in the horizontal direction of the quantum well. The inclined surfaces (inclined sides of the inverted trapezoid) on both sides of the inverted-trapezoidal semiconductor portion converge and reflect the light emitted by the quantum well to the direction of the pixel lens. The continuous planarization layer between multiple pixels is configured to be continuous as a whole. The top surface of the continuous planarization layer is provided with a negative electrode pad layer, so that the negative electrode pad layer and the conductive semiconductor layer are not located on the same planar layer. The positive electrode layer is arranged in the dielectric layer, and the dielectric layer and the IC chip layer are in aligned connection.

[0039] According to the above structure disclosed herein, the light emitted by the quantum well is reflected by the three-side covering reflection layer, and the light rays from the side of the quantum well facing away from the surface of the pixel lens are reflected back to the pixel lens, so that the utilization efficiency of the light emitted by the quantum well is greatly improved. At the same time, by using the inclined surfaces of the inverted-trapezoidal semiconductor portion to reflect the light emitted by the quantum well to both sides of the pixel lens, the light emitted by the quantum well to both sides of the pixel lens can also be converged and collected in the direction towards the pixel lens, thereby further improving the utilization efficiency of the light emitted by the quantum well. In addition, using the continuous planarization layer structure design, the negative electrode pad layer can be arranged at any position of the continuous planarization layer. In some embodiments, the negative electrode pad layer can be arranged at a position where the quantum well is not blocked to emit light to the pixel lens, so that the negative electrode pad layer does not block the light, and the efficiency of the pixel lens collecting light is further improved.

[0040] In some embodiments, the three-side covering reflection layer includes a conductive portion, a side reflection portion, and an edge reflection portion. The upper surface of the conductive portion is attached to the conductive semiconductor layer, and the lower surface of the conductive portion is attached to the positive electrode layer. The upper surface of the side reflection portion and the upper surface of the edge reflection portion are both attached to the isolation layer, and the lower surface of the side reflection portion is attached to the dielectric layer.

[0041] In some embodiments, the conductive portion has a main reflection effect, and the side reflection portion has a residual light reflection effect, and the isolation layer is a transparent layer.

[0042] In some embodiments, the three-side covering reflection layer is or includes an Ag layer formed by electron beam evaporation or thermal evaporation.

[0043] In some embodiments, a good reflection effect is achieved by using the Ag layer, and the reflectivity of Ag is the highest among the reflection materials.

[0044] In some embodiments, the isolation layer is configured as Al 2O3 or Si 3N4.

[0045] In some embodiments, the negative electrode pad layer is hollow, the hollow portion of the negative electrode pad layer is provided with a pixel lens, and the main body portion of the negative electrode pad layer is arranged at a position on the upper surface of the continuous planarization layer, rather than a position that blocks light rays toward the pixel lens.

[0046] According to the structure disclosed herein, light rays from the quantum well toward the lens direction of the pixel lens are not blocked due to the positioning of the negative electrode pad layer.

[0047] In some embodiments, the dielectric layer includes a Si3N4 layer structure on the top and a SiO2 layer structure on the bottom, and the Si3N4 layer structure covers and attaches the surfaces of the three-side covering reflective layer. The positive electrode includes an epitaxial positive electrode and a chip positive electrode, and the epitaxial positive electrode is arranged in a penetrating configuration in the Si3N4 layer structure and the SiO2 layer structure, and the chip positive electrode is arranged in the IC chip layer.

[0048] In some embodiments, the IC chip layer includes a chip dielectric layer on the top and a chip electric board on the bottom, and the chip positive electrode is arranged in a penetrating configuration in the chip dielectric layer, the top of the chip positive electrode is connected to the epitaxial positive electrode by alignment bonding, and the bottom of the chip positive electrode is electrically connected to the chip electric board.

[0049] Due to the fact that the Ag three-side covering reflective layer is arranged in the pixel structure and a conventional pixel process is used to manufacture the pixel structure, Ag layer loss can occur, which further causes internal short circuit of the pixel structure. In some embodiments, the alignment bonding connection structure and process of the chip dielectric layer and the dielectric layer are used to achieve non-short circuit installation of the IC chip layer.

[0050] In some embodiments, the positive electrode layer is configured as a Cu column.

[0051] In some example embodiments, the following technical aspects are disclosed herein:

[0052] In some embodiments, based on the internal structure of the pixel, a pixel structure manufacturing process for reducing light blocking effect and improving light reflection efficiency is provided. The pixel structure manufacturing process includes the following process steps:

[0053] Step 1: select an epitaxial wafer, which in some embodiments includes a sapphire layer on the top surface and a conductive semiconductor layer on the bottom, with quantum wells in the middle of the conductive semiconductor layer;

[0054] Step 2: semiconductor etching;

[0055] Substep 2-1 of Step 2: etching the conductive semiconductor layer inside the epitaxial wafer to form an inverted trapezoidal semiconductor portion with an inverted trapezoidal shape, with the quantum well inside the inverted trapezoidal semiconductor portion;

[0056] Step 3: Isolation layer deposition and patterned etching;

[0057] Sub-step 3-1 of Step 3: Forming the isolation layer on the bottom surface of the conductive semiconductor layer;

[0058] Sub-step 3-2 of Step 3: Etching the isolation layer after the deposition is completed and etching to form an opening at the bottom of the inverted-trapezoidal semiconductor portion for depositing the conductive portion that three-side covers the reflective layer;

[0059] Step 4: Three-side covering reflective layer deposition and patterned etching;

[0060] Sub-step 4-1 of Step 4: Forming the three-side covering reflective layer by deposition on the bottom surface of the isolation layer;

[0061] Sub-step 4-2 of Step 4: Trimming to form the shape of the three-side covering reflective layer;

[0062] Step 5: Dielectric layer deposition and patterned etching;

[0063] Sub-step 5-1 of Step 5: Forming the dielectric layer by deposition on the lower surface of the three-side covering reflective layer;

[0064] Sub-step 5-2 of Step 5: Etching and trimming to form the shape of the dielectric layer;

[0065] Step 6: Positive electrode deposition and polishing;

[0066] Sub-step 6-1 of Step 6: Depositing and forming the positive electrode layer;

[0067] Sub-step 6-2 of Step 6: Performing a polishing operation on the positive electrode layer;

[0068] Step 7: Alignment bonding;

[0069] Sub-step 7-1 of Step 7: Connecting the IC chip layer to the bottom surface of the dielectric layer with an alignment bonding process;

[0070] Step 8: Removing the sapphire layer;

[0071] Step 9: Deposition and patterning of the negative electrode pad layer;

[0072] Sub-step 9-1 of Step 9: Depositing and forming the negative electrode pad layer;

[0073] Sub-step 9-2 of Step 9: Patterning the negative electrode pad layer to form a hollow shape;

[0074] Step 10: Lens deposition and patterning;

[0075] Sub-step 10-1 of Step 10: Depositing a layer structure that forms a pixel lens;

[0076] Sub-step 10-2 of step 10: patterning the layer structure of the pixel lens to form a lens shape.

[0077] By this technical solution, a novel pixel structure can be manufactured by using the technology.

[0078] In some embodiments, the epitaxial wafer in step 1 includes a sapphire layer, a conductive semiconductor layer, and a quantum well as an initial material for the pixel structure process, wherein the conductive semiconductor layer includes a P-type material such as a P-GaN material layer at the bottom of the quantum well and an N-type material such as an N-GaN material layer at the top of the quantum well.

[0079] In some embodiments, the process of etching the conductive semiconductor layer in the epitaxial wafer in step 2 is an inductively coupled plasma (ICP) semiconductor etching process, and the inverted trapezoidal or bowl-shaped pattern is formed by etching.

[0080] In some embodiments, the process of forming the isolation layer in step 3 is an atomic layer deposition (ALD) process, and the etching process of the deposited isolation layer implements an ICP etching process.

[0081] In some embodiments, the process of forming the three-side covered reflective layer in step 4 is a physical vapor deposition (PVD) process of electron beam evaporation or thermal evaporation, and the process of etching the three-side covered reflective layer implements a lift-off process to etch and trim to form the shape.

[0082] In some embodiments, the process of forming the dielectric layer in step 5 is implemented by a chemical vapor deposition (CVD) process method, and the etching and trimming to form the shape of the dielectric layer are implemented by an ICP semiconductor etching process.

[0083] In some embodiments, the positive electrode layer is formed by implementing an electroplating deposition process in step 6, and the positive electrode layer is polished by a chemical mechanical polishing (CMP) process.

[0084] In some embodiments, the sapphire layer on the upper surface of the epitaxial wafer is lifted off by a laser lift-off process in step 8.

[0085] In some embodiments, the negative electrode pad layer is formed by a PVD deposition of a physical vapor deposition process of electron beam evaporation or thermal evaporation in step 9, and the negative electrode pad layer is lifted off to form a hollow shape by implementing a lift-off process.

[0086] In some embodiments, the process in step 10 is a CVD deposition process to form the layer structure of the pixel lens, and an ICP semiconductor etching process is implemented on the layer structure of the pixel lens to form the pixel lens with a lens shape.

[0087] In general, the system and method disclosed herein has the following advantages and improvements:

[0088] (1) The light emitted by the quantum well is reflected by the three-side covering reflective layer, and the light on the side of the quantum well opposite to the pixel lens is reflected back to the pixel lens, so that the utilization efficiency of the light emitted by the quantum well is greatly improved.

[0089] (2) By using the inclined surface of the inverted trapezoidal semiconductor part to reflect the light emitted by the quantum well to both sides of the pixel lens, the light emitted by the quantum well to both sides of the pixel lens can also be collected and collected in the direction towards the pixel lens, and the utilization efficiency of the light emitted by the quantum well is further improved.

[0090] (3) By utilizing the continuous planarization layer structure design, the negative electrode pad layer is arranged at any position of the continuous planarization layer. Therefore, the position of the negative electrode pad layer can be arranged at a position where the quantum well is not blocked to emit light to the pixel lens, so that the negative electrode pad layer does not block light, and the efficiency of the pixel lens collecting light is further improved. At the same time, the negative electrode pad layer and the mesa (i.e. the epitaxial wafer, which includes a conductive semiconductor layer, and the conductive semiconductor layer includes a quantum well as an intermediate layer) are not in one planar layer, so the short circuit between the negative electrode pad layer and the three-side covering reflective layer is not easy to occur. The positioning of the negative electrode pad layer realizes the diffusion of current from the top of the pixel structure to the mesa. The positioning of the negative electrode pad layer can further prevent interference between adjacent pixels.

[0091] (4) Since the three-side covering reflective layer of Ag forms a three-side covering pattern in the processing technology, when connecting the three-side covering reflective layer to the IC chip layer, the alignment bonding process is implemented, and the epitaxial positive electrode and the chip positive electrode are aligned one by one, and then bonded and connected.

[0092] (5) The continuous planarization layer between multiple pixels realizes a continuous design, which plays a role in protecting Ag and facilitating current diffusion.

[0093] (6) An isolation layer of Al2O3 or Si3N4 material is provided to isolate the three-side covering reflective layer and the conductive semiconductor layer including the quantum well. Selecting Al2O3 as the isolation layer can prevent the diffusion of Ag, because Al2O3 has fewer lattice defects compared to other traditional materials. Selecting Si3N4 as the isolation layer can prevent the diffusion of Ag, because Si3N4 has fewer lattice defects compared to other traditional materials.

[0094] (7) A novel structure design is implemented, which divides the dielectric layer into a Si3N4 layer structure at the top and a SiO2 layer structure at the bottom, wherein the Si3N4 layer structure covers and is attached to the surface of the Ag reflective layer.

[0095] It should be noted that the embodiments described above can be combined with any of the other embodiments described herein. The features and advantages described in the specification are not all inclusive, and many additional features and advantages will be apparent to one of ordinary skill in the art in view of the drawings, specification, and claims. Moreover, it should be noted that the language used in the specification has been principally selected for readability and instructional purposes and can not have been selected to delineate or circumscribe the inventive subject matter. BRIEF DESCRIPTION OF DRAWINGS

[0096] So that the application can be more readily understood, a more particular description will be rendered by reference to a variety of embodiments, some of which are illustrated in the accompanying drawings. Understanding that these drawings depict only the related art and are not therefore the subject of the application, the description that follows is intended to be a complete and inclusive description of the application, and will be taken in conjunction with the accompanying drawings.

[0097] For convenience, "up" is used to refer to the substrate or circuit board being away from the light emitting structure, "down" refers to toward the substrate, and other directional terms such as top, bottom, above, below, under, beneath, and the like are interpreted accordingly.

[0098] Figure 1 is an exemplary cross-sectional schematic of an overall structure of a pixel structure according to some embodiments of the present embodiment.

[0099] Figure 2 is an exemplary top view schematic of a pixel structure according to some embodiments of the present embodiment.

[0100] Figure 3 is an exemplary structure schematic of step 1 in a pixel structure manufacturing process according to some embodiments of the present embodiment.

[0101] Figure 4 is an exemplary structure schematic of step 2 in a pixel structure manufacturing process according to some embodiments of the present embodiment.

[0102] Figure 5 is an exemplary structure schematic of step 3 in a pixel structure manufacturing process according to some embodiments of the present embodiment.

[0103] Figure 6 is an exemplary structure schematic of step 4 in a pixel structure manufacturing process according to some embodiments of the present embodiment.

[0104] Figure 7 is an exemplary structure schematic of step 5 in a pixel structure manufacturing process according to some embodiments of the present embodiment.

[0105] Figure 8 is an exemplary structure schematic of step 6 in a pixel structure manufacturing process according to some embodiments of the present embodiment.

[0106] Figure 9 is an exemplary structure diagram of step 7 in the pixel structure manufacturing process according to some embodiments of the present embodiment.

[0107] Figure 10 is an exemplary structure diagram of step 8 in the pixel structure manufacturing process according to some embodiments of the present embodiment.

[0108] Figure 11 is an exemplary structure diagram of step 9 in the pixel structure manufacturing process according to some embodiments of the present embodiment.

[0109] Figure 12 is an exemplary structure diagram of step 10 in the pixel structure manufacturing process according to some embodiments of the present embodiment.

[0110] The drawings include the following component identifications: 1, pixel lens; 2, negative electrode pad layer; 3, conductive semiconductor layer; 3-1, inverted trapezoidal semiconductor portion; 3-11, P-GaN portion; 3-12, N-GaN portion; 3-2, continuous planarization layer; 4, quantum well; 5, isolation layer; 6, positive electrode layer; 6-1, epitaxial positive electrode; 6-2, chip positive electrode; 7, dielectric layer; 7-1, Si3N4 layer structure; 7-2, SiO2 layer structure; 8, IC chip layer; 8-1, dielectric layer of chip; 8-2, chip electrical board; 9, three-side covering reflective layer; 9-1, conductive portion; 9-2, side reflective portion; and 9-3, edge reflective portion.

[0111] In accordance with common practice the various features illustrated in the drawings can not be drawn to scale. Therefore, the dimensions of the various features can be arbitrarily expanded or reduced for the clarity of illustration. Moreover, some of the drawings can not depict all of the components of a given system, method or device. Finally, like reference numerals can be used to denote like features throughout the specification and figures. DETAILED DESCRIPTION

[0112] Numerous specific details are described herein to provide a thorough understanding of example embodiments shown in the drawings. However, some embodiments can be practiced without many of the specific details, and the scope of the claims should not be limited to the features and aspects specifically described herein. Furthermore, well-known processes, components, and materials have not been described in detail in order to avoid unnecessarily obscuring the pertinent aspects of the embodiments described herein.

[0113] Figure 1 is an exemplary cross-sectional diagram of the overall structure of a pixel structure according to some embodiments of the present embodiment.

[0114] Figure 2is an exemplary top view schematic of a pixel structure according to some embodiments of the present embodiments.

[0115] In some embodiments, in Figure 1 and Figure 2 A pixel structure configured to reduce light blocking effect and improve reflection efficiency is shown in FIGS. 1-8. Pitch refers to the distance between the centers of adjacent pixels on a display panel. In some embodiments, the pitch can vary from about 40 microns to about 20 microns, to about 10 microns, and / or preferably to about 5 microns or less. Many efforts have been made to reduce the pitch. When determining the pitch specification, the individual pixel area is fixed.

[0116] The structure includes, from the outside (top) to the inside (bottom), a pixel lens 1, a negative electrode pad layer 2, a conductive semiconductor layer 3, a quantum well 4, an isolation layer 5, a positive electrode layer 6, a dielectric layer 7, and an IC chip layer 8. And the quantum well 4 is arranged inside the conductive semiconductor layer 3. The conductive semiconductor layer 3 is made of GaN semiconductor material, and the positive electrode layer 6 is configured as a Cu column. The overall working principle is described as follows. The quantum well 4 serves as a light emitting unit. The negative electrode pad layer 2 and the positive electrode layer 6 are respectively grounded and connected to the electrical signal on the IC chip layer 8. And the electrical signal is transmitted inside the pixel through the negative electrode pad layer 2 and the positive electrode layer 6, thereby providing a driving signal for the quantum well 4, and controlling whether the quantum well 4 emits light. Therefore, the signal control command of the IC chip layer 8 enters the inside of the pixel structure through the positive electrode layer 6.

[0117] Compared with the conventional pixel structure, the present application provides improved internal details of the pixel structure, so the processing technology for manufacturing the pixel structure is also different, the purpose is to improve the collection efficiency of the light emitted by the quantum well 4 in the pixel structure. In some embodiments, specifically, a three-sided covering reflection layer 9 is arranged between the lower surface of the conductive semiconductor layer 3 and the top of the positive electrode layer 6, wherein the three-sided covering reflection layer 9 includes a conductive part 9-1, a side reflection part 9-2, and an edge reflection part 9-3. The upper surface of the conductive part 9-1 is in contact with the conductive semiconductor layer 3, and the lower surface of the conductive part 9-1 is in contact with the positive electrode layer 6. The upper surface of the side reflection part 9-2 and the upper surface of the edge reflection part 9-3 are both in contact with the isolation layer 5, and the lower surface of the side reflection part 9-2 and the lower surface of the edge reflection part 9-3 are both in contact with the dielectric layer 7. In some embodiments, as shown in FIG. 9, the three-sided covering reflection layer 9 is arranged on the lower surface of the conductive semiconductor layer 3, and the conductive part 9-1 is in contact with the conductive semiconductor layer 3, and the side reflection part 9-2 and the edge reflection part 9-3 are arranged on the isolation layer 5. Figure 1As shown, the three-sided reflective layer 9 is symmetrical with side reflective portions 9-2 and edge reflective portions 9-3 on both sides of the three-sided reflective layer 9. In this embodiment, the three-sided reflective layer 9 is or includes an Ag layer formed by electron beam evaporation or thermal evaporation, but other reflective material layers may also be used. Since Ag has the best reflective effect, Ag is used as a reflective layer material. However, since Ag is a material that diffuses very easily during etching, Ag is generally not used as a reflective layer in the internal structure of pixel devices. In this invention, the reflective layer structure of Ag and its pixel processing technology are described herein.

[0118] In some embodiments, the light emitted by the quantum well 4 is reflected by the three-sided reflective layer 9, and the light from the side of the quantum well 4 facing away from the pixel lens 1 is reflected back to the pixel lens 1, thereby greatly improving the utilization efficiency of the light emitted by the quantum well 4.

[0119] In some embodiments, the conductive semiconductor layer 3 comprises two parts: an inverted trapezoidal semiconductor portion 3-1 and a continuous planarization layer 3-2. Since the quantum well 4 is located inside the inverted trapezoidal semiconductor portion 3-1, the inclined surface 3-1B of the inverted trapezoidal semiconductor portion 3-1 collects the light emitted from the quantum well 4 and reflects it towards the pixel lens 1. Therefore, by using the inclined surface of the inverted trapezoidal semiconductor portion 3-1 to reflect the light emitted from the quantum well 4 on both sides of the pixel lens 1, the light emitted from both sides of the pixel lens 1 can also be converged and collected in the direction of the pixel lens 1, further improving the utilization efficiency of the light emitted from the quantum well 4. The inverted trapezoidal semiconductor portion 3-1 is divided into a bottom portion 3-11 and a top portion 3-12 along the horizontal direction of the quantum well 4, and the quantum well 4 isolates the bottom portion 3-11 from the top portion 3-12. In some embodiments, the bottom portion 3-11 is a layer comprising a P-type conductive semiconductor material such as P-GaN or PI nGaP, and the top portion 3-12 is a layer comprising an N-type conductive semiconductor material such as N-GaN or NI nGaP. In some embodiments, a transparent thin conductive film of indium tin oxide (ITO) is deposited on top of the conductive semiconductor layer 3. In some other embodiments, the positions of the P-type and N-type materials can be switched, and the positions of the positive electrode layer and the negative electrode layer can be switched.

[0120] Furthermore, in some embodiments, the negative electrode pad layer 2 is configured as follows: Figure 1 and Figure 2The hollow shape is shown. The hollow part of the negative electrode pad layer 2 is disposed and aligned with the pixel lens 1, and the main part of the negative electrode pad layer 2 is arranged at the upper surface position of the continuous planarization layer 3-2, rather than at the position that blocks the light rays towards the pixel lens 1. The main part of the negative electrode pad layer 2 protrudes from the upper surface position of the continuous planarization layer 3-2. Therefore, by the design of the continuous planarization layer 3-2, the negative electrode pad layer 2 can be arranged at the position where the quantum well 4 emits light to the pixel lens 1, so that the negative electrode pad layer 2 does not block the light, and further improves the efficiency of the pixel lens 1 to collect light. In some embodiments, as shown Figure 1 The mesa is formed by an epitaxial wafer, which is (or includes) a conductive semiconductor layer 3 with a quantum well 4 in the middle. The mesa is a kind of light-emitting PN junction. At the same time, the negative electrode pad layer and the mesa are not in one planar layer, so that the short circuit between the negative electrode pad layer and the three-side covering reflective layer 9 is less likely to occur.

[0121] In some example embodiments, the isolation layer 5 between the mesa and the three-side covering reflective layer 9 and the dielectric layer 7 is configured as a layer of Al 2O3 or Si 3N4 material manufactured by deposition and etching.

[0122] Since the Ag three-side covering reflective layer 9 is arranged in the pixel structure, when a conventional pixel manufacturing process is used to manufacture the pixel structure, it will cause the Ag layer to be lost, thereby further causing an internal short circuit of the pixel structure. In some embodiments, in the present application, the dielectric layer 7 includes a double-layer structure of a top Si 3N4 layer structure 7-1 and a bottom SiO2 layer structure 7-2, the Si 3N4 layer structure 7-1 covers and contacts the surface of the three-side covering reflective layer 9. The positive electrode layer 6 includes an epitaxial positive electrode 6-1 and a chip positive electrode 6-2, while the epitaxial positive electrode 6-1 is continuously arranged in the Si 3N4 layer structure 7-1 and the SiO2 layer structure 7-2, and the chip positive electrode 6-2 is arranged in the IC chip layer 8. At the same time, the IC chip layer 8 is wrapped with a top chip dielectric layer 8-1 and a bottom chip electric plate 8-2. When the chip positive electrode 6-2 penetrates the chip dielectric layer 8-1, the top of the chip positive electrode 6-2 is connected to the epitaxial positive electrode 6-1 by a bonding according to the position alignment, and the bottom of the chip positive electrode 6-2 is electrically connected with the chip electric plate 8-2. The two electrodes, the epitaxial positive electrode 6-1 and the chip positive electrode 6-2, are located on two wafers before bonding, and form a combination after bonding. The positive electrode layer 6 is configured as a Cu column. In some embodiments, according to the above structure arrangement and connection mode, the manufacturing of the pixel structure can be realized, i.e. the reflective layer forms a three-side covering pattern in the manufacturing process, and then is connected in a subsequent stage by using an alignment bonding process.

[0123] According to the structure design of the pixel inside described above, the embodiment provides a pixel structure manufacturing process for reducing light blocking effect and improving light reflection efficiency. The process includes the following processing steps:

[0124] Step 1: Selecting an epitaxial wafer. Figure 3 is an exemplary structure schematic diagram of step 1 in the pixel structure manufacturing process according to some embodiments of the present embodiment. According to Figure 3 , an epitaxial wafer including a sapphire layer 10, a conductive semiconductor layer 3', and a quantum well 4' is selected as the initial material by the pixel structure manufacturing process. In some embodiments, the conductive semiconductor layer 3' includes a P-GaN material layer at the bottom of the quantum well 4' and an N-GaN material layer at the top of the quantum well 4'.

[0125] Step 2: Semiconductor etching. Figure 4 is an exemplary structure schematic diagram of step 2 in the pixel structure manufacturing process according to some embodiments of the present embodiment. According to Figure 4 , an ICP semiconductor etching process is used to etch the conductive semiconductor layer 3' in the epitaxial wafer Figure 3 to form an inverted-trapezoidal semiconductor portion 3-1 in an inverted-trapezoidal shape and a continuous planarization layer 3-2. And the etched quantum well 4 is located inside the inverted-trapezoidal semiconductor portion 3-1. The inverted-trapezoidal semiconductor portion 3-1 is etched to form a P-GaN portion 3-11 at the bottom and an N-GaN portion 3-12 at the top in the horizontal direction of the quantum well 4.

[0126] Step 3: Isolation layer deposition and patterned etching. Figure 5 is an exemplary structure schematic diagram of step 3 in the pixel structure manufacturing process according to some embodiments of the present embodiment. According to Figure 5 , the method includes two sub-steps: (A) depositing an ALD layer on the bottom surface of the conductive semiconductor layer 3 by a deposition process to form an isolation layer 5 (the original shape of the deposited isolation layer 5 is not shown in Figure 5 ), wherein the isolation layer 5 is deposited by using Al 2O3 or Si 3N4 material; and (B) etching the deposited isolation layer 5 to form the isolation layer 5 with openings shown in Figure 5 , and etching the bottom of the inverted-trapezoidal semiconductor portion 3-1 by using an ICP etching process to form openings for depositing the conductive portion 9-1 of the three-side covered reflection layer 9 (not fully shown in Figure 5 ).

[0127] Step 4: Three-side covered reflection layer deposition and patterned etching. Figure 6 is an exemplary structure schematic diagram of step 4 in the pixel structure manufacturing process according to some embodiments of the present embodiment. According to Figure 6The method includes two sub-steps: (A) forming a three-side covered reflective layer 9 on the bottom surface of the isolation layer 5 using an e-beam evaporation or thermal evaporation PVD process (the original shape of the reflective layer 9 after deposition is not shown in Figure 6 ). In this embodiment, Ag material is used as the reflective layer 9; and (B) etching and shaping the three-side covered reflective layer 9 by using a lift-off process.

[0128] Step 5: Dielectric layer deposition and patterned etching. Figure 7 is an exemplary structure schematic of Step 5 in the pixel structure fabrication process according to some embodiments of the present embodiment. According to Figure 7 , the method includes two sub-steps: (A) forming a dielectric layer 7 on the lower surface of the three-side covered reflective layer 9 by using a CVD deposition process (the original shape of the dielectric layer 7 after deposition is not shown in Figure 7 ), where the dielectric layer 7 is divided into a double-layer structure of a top Si3N4layer structure 7-1 and a bottom SiO2layer structure 7-2, as shown in Figure 1 ; and (B) etching and shaping the dielectric layer 7 by using an ICP semiconductor etching process to leave space for the positive electrode layer 6.

[0129] Step 6: Positive electrode deposition and polishing. Figure 8 is an exemplary structure schematic of Step 6 in the pixel structure fabrication process according to some embodiments of the present embodiment. According to Figure 8 , the method includes two sub-steps: (A) depositing the positive electrode layer 6 by using an electroplating deposition method, i.e., depositing to form an epitaxial positive electrode 6-1; and (B) polishing operation on the epitaxial positive electrode 6-1 by using a CMP polishing process.

[0130] Step 7: Alignment bonding. Figure 9 is an exemplary structure schematic of Step 7 in the pixel structure fabrication process according to some embodiments of the present embodiment. According to Figure 9 , the bottom surface of the dielectric layer 7 is connected to the IC chip layer 8 by using an alignment bonding process, where the epitaxial positive electrode 6-1 and the chip positive electrode 6-2 are aligned and bonded to each other. Alignment bonding is usually performed between wafers that have patterns on each surface. In some embodiments, the sapphire layer 10 and the IC chip layer 8 both have patterned electrodes (copper) and SiO2on their surfaces. To achieve the alignment bonding between them, the electrodes from the two wafers are well aligned face-to-face. Then, the two wafers are contacted and form an initial bonding. The bonding is completed by the following annealing process, which enhances the bonding strength of the contact between copper and copper and SiO2and SiO2.

[0131] Step 8: Removing the sapphire layer 10. Figure 10is an exemplary structure schematic diagram of step 8 in the pixel structure manufacturing process according to some embodiments of the present embodiment. According to Figure 10 , the sapphire layer 10 on the upper surface of the epitaxial wafer is peeled off by a laser lift-off process.

[0132] Step 9: Negative electrode pad layer deposition and patterning. Figure 11 is an exemplary structure schematic diagram of step 9 in the pixel structure manufacturing process according to some embodiments of the present embodiment. According to Figure 11 , the method includes two sub-steps: (A) using a PVD process for electron beam evaporation or thermal evaporation to form the negative electrode pad layer 2 (the original shape of the negative electrode pad layer 2 after PVD is not shown in Figure 11 ); and (B) forming a hollow shape by peeling off the negative electrode pad layer 2 using a peeling process.

[0133] Step 10: Lens deposition and patterning. Figure 12 is an exemplary structure schematic diagram of step 10 in the pixel structure manufacturing process according to some embodiments of the present embodiment. According to Figure 12 , the method includes two sub-steps: (A) using a CVD deposition process to form the layer structure of the pixel lens 1 (the original shape of the pixel lens 1 layer after deposition is not shown in Figure 12 ); and (B) etching the layer structure of the pixel lens 1 to form the lens-shaped pixel lens 1 by using an ICP semiconductor etching process. In another example, the lens 1 is formed by self-assembly through a CVD deposition process by directly forming a lens shape on the underlying structure without etching. In some examples, the lens 1 is aligned with the hollow shape. For example, from a vertical perspective, the edges of the lens 1 and the edges of the hollow shape are substantially aligned with each other.

[0134] The dimensions used in the manufacturing process follow the micro-LED product pixel structure design. In some embodiments, the following size design is implemented, for example, the diameter of the circular portion of the pixel lens 1 is 3.2±0.8 μm, the bottom thickness of the pixel lens 1 (e.g. excluding the focal lens portion) is 1±1 μm, the top width of the inverted trapezoidal semiconductor portion 3-1 is 2.05 μm to 3.8 μm, the thickness of the continuous planarization layer 3-2 is 0.01 μm to 0.2 μm, the diameter of the epitaxial positive electrode 6-1 and the chip positive electrode 6-2 is 1 μm, the height of the negative electrode pad layer 2 is 100 nm to 1 μm, the thickness of the isolation layer 5 is 10 nm to 200 nm, and other dimensions are designed according to the design requirements of the product.

[0135] In the manufacturing process of the pixel structure, the present application relates to some special processing methods. The methods include the following processes: ICP semiconductor etching process, ALD process, PVD process, LIFT-OFF process, CVD process, electroplating deposition process, CMP polishing process, alignment bonding process and laser stripping process. Those skilled in the art can understand these technical methods.

[0136] Those skilled in the art should understand that the pixel structure is not limited by the above structure, and can include more or fewer components than the illustrated components, or can combine some components, or can use different components.

[0137] The above description is only an embodiment of the present application, and the present application is not limited thereto. Modifications, equivalent replacements and improvements made without departing from the concept and principle of the present application shall belong to the protection scope of the present application.

[0138] Further embodiments further include various subsets of the above-described embodiments, including combinations of such subsets with each other or with other embodiments Figures 1 to 12 The illustrated embodiments.

[0139] While the detailed description contains many specifics, these should not be construed as limiting the scope of the application but merely as illustrating different examples and aspects of the application. It should be appreciated that the scope of the application includes other embodiments not discussed in detail above. For example, the above-described methods can be applied to the integration of functional devices other than LEDs and control circuitry other than pixel drivers for OLEDs. Examples of non-LED devices include vertical cavity surface emitting lasers (VCSELs), photodetectors, microelectromechanical systems (MEMS), silicon photonic devices, power electronic devices, and distributed feedback lasers (DFBs). Examples of other control circuitry include current drivers, voltage drivers, transimpedance amplifiers, and logic circuits.

[0140] The foregoing description of disclosed embodiments is provided as an enabling teaching of the application. Various modifications will be apparent to those skilled in the art from this description and will be encompassed within the spirit of the application. Therefore, the application is not intended to be limited to the embodiments shown herein but is to be accorded the full scope consistent with the principles and novel features disclosed herein.

[0141] The features of the present application can be implemented in a computer program product such as a storage medium (media) or computer readable storage medium (media) having stored thereon instructions that can be used to program a processing system to perform any of the features presented herein. A storage medium can include any available memory or storage medium, including both volatile and nonvolatile media, removable and nonremovable media implemented in any available technology that is used to non- transitorily store information such as computer readable instructions, data structures, program modules, and / or other data. Storage media can further include, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information in a non-transitory fashion. The term "non-transitory" simply means that the results generated by the processing system should not be lost if the power is removed from the processing system. The term should not be interpreted

[0142] The features of the present application, which are stored on any of the machine readable medium (media), can be incorporated in software and / or firmware in whole or in part, and can be employed in hardware, software, and / or firmware applications such as program code, in combination with firmware and / or software applications or use by themselves as standalone software and / or firmware applications.

[0143] It should be understood that, although terms such as "first," "second," and the like can be used herein to describe various elements or steps, these elements or steps should not be limited by these terms. These terms are only used to distinguish one element or step from another.

[0144] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the claims. As used in the description of the embodiments and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It also should be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0145] The term "if can be understood to mean "when" or "in response to a determination that" or "in response to detecting" depending on the context. Similarly, the phrase "if it is determined [that the predicate condition]" or "if [the predicate condition]" or "when [the predicate condition]" can be understood to mean "upon a determination" or "in response to a determination" or "in response to detecting" that the predicate condition, depending on the context.

[0146] The above description has been presented for the purpose of illustration and description. It is not intended to be exhaustive or to limit the claims to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the claims be limited not by this detailed description, but rather by the claims themselves as interpreted in accordance with established doctrines of patent law.

Claims

1. A micro light emitting pixel structure, characterized by, comprising: a conductive semiconductor layer, wherein the conductive semiconductor layer has an inverted-trapezoidal shape, and comprises a continuous layer at the top of the inverted-trapezoidal shape; a quantum well layer for light emission, wherein the quantum well layer is within the conductive semiconductor layer; a three-side covered reflective layer under the conductive semiconductor layer, wherein the material of the three-side covered reflective layer is Ag; a negative electrode pad layer electrically connected to the conductive semiconductor layer; and a positive electrode layer electrically connected to the conductive semiconductor layer, wherein the negative electrode pad layer is formed above the continuous layer and is hollowed out in the area above the quantum well, so that the light emitted from the quantum well is not blocked by the negative electrode pad layer.

2. A micro light emitting pixel structure, characterized by, comprising: a conductive semiconductor layer, wherein the conductive semiconductor layer has an inverted-trapezoidal shape; a quantum well layer for light emission, wherein the quantum well layer is within the conductive semiconductor layer; a three-side covered reflective layer under the conductive semiconductor layer, wherein the material of the three-side covered reflective layer is Ag; an isolation layer between the conductive semiconductor layer and the three-side covered reflective layer, wherein the material of the isolation layer is Al2O3 or Si3N4; a negative electrode pad layer electrically connected to the conductive semiconductor layer; and a positive electrode layer electrically connected to the conductive semiconductor layer, wherein the conductive semiconductor layer comprises a continuous layer at the top of the inverted-trapezoidal shape, wherein the negative electrode pad layer is formed above the continuous layer and is hollowed out in the area above the quantum well, so that the light emitted from the quantum well is not blocked by the negative electrode pad layer.

3. The micro light emitting pixel structure of claim 1, wherein, further comprising an isolation layer between the conductive semiconductor layer and the three-side covered reflective layer, wherein the material of the isolation layer is Al2O3 or Si3N4.

4. The micro light emitting pixel structure according to claim 1 or 2, wherein, wherein the conductive semiconductor layer comprises a P-type conductive semiconductor material layer and an N-type conductive semiconductor material layer.

5. The micro light emitting pixel structure according to claim 4, wherein: the P-type conductive semiconductor material layer is a P-GaN layer or a P-InGaP layer; and / or the N-type conductive semiconductor material layer is an N-GaN layer or an N-InGaP layer.

6. The micro light emitting pixel structure according to claim 2 or 3, wherein, wherein the three-side covered reflective layer comprises: a middle conductive part in contact with the positive electrode layer and the conductive semiconductor layer; two side reflective parts in contact with the isolation layer; and two edge reflective parts in contact with the isolation layer; wherein the three-side covered reflective layer forms an inverted-trapezoidal shape around the quantum well layer.

7. The micro light emitting pixel structure according to claim 1 or 2, wherein, wherein the quantum well layer is enclosed within the inverted-trapezoidal shape of the conductive semiconductor layer, so that the light from the quantum well is focused towards the top direction of the light emitting pixel structure.

8. The micro light emitting pixel structure according to claim 2 or 3, wherein: the isolation layer forms an inverted-trapezoidal shape around the quantum well layer; and the isolation layer is a continuous layer with at least one opening at the bottom of the inverted-trapezoidal shape.

9. The micro light emitting pixel structure of claim 1 or 2, wherein, the continuous layer covers the entire surface of the micro light emitting pixel structure and extends to the adjacent micro light emitting pixel structure.

10. The micro light emitting pixel structure of claim 1 or 2, wherein, further comprising an integrated circuit (IC) chip layer electrically connected to the positive electrode layer.

11. The micro light emitting pixel structure of claim 10, wherein, further comprising a dielectric layer between the tri-mirror reflective layer and the IC chip layer, wherein the dielectric layer comprises a top dielectric layer made of Si3N4 covering a surface of the tri-mirror reflective layer and a bottom dielectric layer made of SiO2.

12. The micro light emitting pixel structure of claim 11, wherein, the positive electrode layer comprises an upper epitaxial positive electrode within the dielectric layer and a bottom chip positive electrode within the IC chip layer.

13. The micro light emitting pixel structure of claim 10, wherein, the IC chip layer comprises an upper chip dielectric layer and a bottom chip electrical board.

14. The micro light emitting pixel structure of claim 11, wherein, the IC chip layer comprising a bottom chip positive electrode is in contact with the dielectric layer comprising an upper epitaxial positive electrode.

15. The micro light emitting pixel structure of claim 1 or 2, wherein, further comprising a pixel lens over the conductive semiconductor layer.

16. The micro light emitting pixel structure of claim 1 or 2, wherein, the continuous layer is a continuous planarization layer.

17. The micro light emitting pixel structure of claim 1 or 2, wherein, the positive electrode layer is configured as a Cu pillar.

18. A method of fabricating a micro light emitting pixel structure, characterized by, comprising: providing an epitaxial wafer comprising a conductive semiconductor layer and a quantum well layer for light emission, wherein the quantum well layer is within the conductive semiconductor layer; etching the conductive semiconductor layer with the quantum well layer into an inverted trapezoidal shape; forming an isolation layer on a bottom surface of the conductive semiconductor layer, wherein a material of the isolation layer is Al2O3 or Si3N4; forming a tri-mirror reflective layer on a bottom surface of the isolation layer, wherein a material of the tri-mirror reflective layer is Ag; forming a first positive electrode layer on a bottom surface of a middle conductive portion of the tri-mirror reflective layer; bonding an integrated circuit (IC) chip layer to the first positive electrode layer; and forming a negative electrode pad layer on an upper surface of the conductive semiconductor layer, the negative electrode pad layer being formed over a continuous layer and being hollowed out in an area over the quantum well such that light emitted from the quantum well is not blocked by the negative electrode pad layer.

19. The method of claim 18, wherein, further comprising forming a dielectric layer between the tri-mirror reflective layer and the IC chip layer after forming the tri-mirror reflective layer and before forming the first positive electrode layer, wherein the dielectric layer comprises a top dielectric layer made of Si3N4 covering a surface of the tri-mirror reflective layer and a bottom dielectric layer made of SiO2.

20. The method of claim 18, wherein, etching the conductive semiconductor layer with the quantum well layer further comprises leaving a continuous layer on a top of the inverted trapezoidal shape in the conductive semiconductor layer.

21. The method of claim 18, wherein, the epitaxial wafer comprises a sapphire substrate layer, and after bonding the IC chip layer and before forming the negative electrode pad layer, the method further comprises removing the sapphire substrate layer.

22. The method of claim 18, wherein, forming the isolation layer comprises etching the isolation layer to form an opening for depositing the middle conductive portion of the tri-mirror reflective layer on the bottom surface of the conductive semiconductor layer through the opening.

23. The method of claim 19, wherein, forming the dielectric layer comprises etching the dielectric layer to form an opening for depositing the first positive electrode layer.

24. The method of claim 19, wherein, bonding comprises aligning bonding the IC chip layer with a second positive electrode layer embedded therein to a bottom surface of the dielectric layer with the first positive electrode layer embedded therein, wherein the first positive electrode layer is an upper epitaxial positive electrode and the second positive electrode layer is a bottom chip positive electrode.

25. The method of claim 18, wherein, Forming the negative electrode pad layer includes forming a hollow shape in the negative electrode pad layer in a region above the quantum well using a lift-off process such that light emitted from the quantum well is not blocked by the negative electrode pad layer.

26. The method of claim 25, wherein, Further comprising forming a pixel lens over the conductive semiconductor layer after forming the negative electrode pad layer and in alignment with the hollow shape in the negative electrode pad layer.

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