A test method, device, equipment and medium

Abstract

The embodiment of the present invention discloses a test method, device, equipment and medium, the method comprising: obtaining a configuration file and test information of a preset clock tree; determining the clock configuration path of the preset clock tree according to the configuration file, determining the input clock of the circuit board to be tested according to the clock configuration path, the clock identifier and the input clock of the preset clock tree; generating a test script according to the input clock and test parameters of the circuit board to be tested, and testing the circuit board to be tested through the test script. The technical solution provided by the present invention can accurately determine the input clock of the circuit board to be tested and improve the circuit board testing efficiency.

Description

Technical Field

[0001] The present invention relates to the field of circuit boards, and in particular to a testing method, device, equipment and medium. Background Art

[0002] Integrated circuit boards are widely used in various electronic devices. The performance of the board itself is crucial to the overall performance of the device. Before mass production, the board needs to be tested and screened to test whether the performance of the board meets the design requirements. Among them, electrical performance testing is an important part of circuit board performance testing, which is mainly used to describe and evaluate the stability and reliability of the circuit board in different modes and electrical environments.

[0003] At the same time, the circuit board needs to ensure that it has a specific clock signal to meet its time domain requirements. Therefore, the circuit board needs to be tested for the clock signal before use. However, the current testing method requires manual input of the clock signal of the circuit board to be tested, which cannot achieve automatic batch testing and is inefficient. Summary of the invention

[0004] The present invention provides a testing method, device, equipment and medium. Through the technical solution of the present application, the input clock of a circuit board to be tested can be accurately determined, thereby improving the testing efficiency of the circuit board.

[0005] In a first aspect, an embodiment of the present invention provides a testing method, comprising:

[0006] Obtain a configuration file and test information of a preset clock tree, wherein the preset clock tree includes leaf nodes and non-leaf nodes, the leaf nodes represent the circuit board to be tested, the configuration file includes a clock identifier, the clock identifier is used to determine whether the next-level node of the non-leaf node inherits the clock, and the test information includes the input clock and test parameters of the preset clock tree;

[0007] Determine a clock configuration path of the preset clock tree according to the configuration file, and determine an input clock of the circuit board to be tested according to the clock configuration path, a clock identifier and an input clock of the preset clock tree;

[0008] A test script is generated according to the input clock and test parameters of the circuit board to be tested, and the circuit board to be tested is tested by using the test script.

[0009] In a second aspect, an embodiment of the present invention provides a testing device, including:

[0010] An acquisition module, used to acquire a configuration file and test information of a preset clock tree, wherein the preset clock tree includes leaf nodes and non-leaf nodes, the leaf nodes represent the circuit board to be tested, the configuration file includes a clock identifier, the clock identifier is used to determine whether the next-level node of the non-leaf node inherits the clock, and the test information includes the input clock and test parameters of the preset clock tree;

[0011] A clock determination module, used to determine a clock configuration path of the preset clock tree according to the configuration file, and determine an input clock of the circuit board to be tested according to the clock configuration path, a clock identifier and an input clock of the preset clock tree;

[0012] The test module is used to generate a test script according to the input clock and test parameters of the circuit board to be tested, and test the circuit board to be tested through the test script.

[0013] In a third aspect, an embodiment of the present invention provides an electronic device, the electronic device comprising:

[0014] at least one processor; and,

[0015] a memory communicatively connected to the at least one processor; wherein,

[0016] The memory stores a computer program that can be executed by the at least one processor. The computer program is executed by the at least one processor so that the at least one processor can perform any one of the testing methods described in the embodiments of the present invention.

[0017] In a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement any one of the test methods described in the embodiments of the present invention when executed.

[0018] The embodiment of the present invention provides a test method, device, equipment and medium, the method comprising: obtaining a configuration file and test information of a preset clock tree, wherein the preset clock tree comprises leaf nodes and non-leaf nodes, the leaf nodes represent circuit boards to be tested, the configuration file comprises a clock identifier, the clock identifier is used to determine whether the next-level node of the non-leaf node inherits the clock, and the test information comprises the input clock and test parameters of the preset clock tree; determining the clock configuration path of the preset clock tree according to the configuration file, determining the input clock of the circuit board to be tested according to the clock configuration path, the clock identifier and the input clock of the preset clock tree; generating a test script according to the input clock and test parameters of the circuit board to be tested, and testing the circuit board to be tested through the test script. Specifically, the clock configuration path of the preset clock tree can be determined through the configuration file, and the input clock of each circuit board to be tested can be accurately determined through the clock configuration path. The technical solution of the present invention can accurately determine the input clock of the circuit board to be tested, thereby improving the test efficiency of the circuit board. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0020] Figure 1 A flow chart of a testing method provided in Embodiment 1 of the present invention;

[0021] Figure 2 A flow chart of a testing method provided in Embodiment 2 of the present invention;

[0022] Figure 3 A schematic diagram of clock transmission provided by an embodiment of the present invention;

[0023] Figure 4 A schematic diagram of power on and off provided by an embodiment of the present invention;

[0024] Figure 5 A schematic diagram of the structure of a testing device provided in Embodiment 3 of the present invention;

[0025] Figure 6 A schematic diagram of the structure of an electronic device provided for implementing the fourth embodiment of the present invention. DETAILED DESCRIPTION

[0026] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0027] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0028] It should be noted that the collection, storage, use, processing, transmission, provision and disclosure of user personal information involved in the technical solution of the present disclosure are in compliance with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0029] Embodiment 1

[0030] Figure 1 A flowchart of a testing method provided in Embodiment 1 of the present invention is provided. The embodiment of the present invention can be specifically applicable to the case of testing an FPGA (Field-Programmable Gate Array) circuit board, and is particularly applicable to the case of performing clock testing on the circuit board. The method can be executed by a testing device, which is implemented by software and / or hardware and configured in a server or a computer.

[0031] like Figure 1 As shown, including:

[0032] Step 110, obtain the configuration file and test information of the preset clock tree, wherein the preset clock tree includes leaf nodes and non-leaf nodes, the leaf nodes represent the circuit board to be tested, the configuration file includes a clock identifier, the clock identifier is used to determine whether the next-level node of the non-leaf node inherits the clock, and the test information includes the input clock and test parameters of the preset clock tree.

[0033] Among them, the preset clock tree is used to manage the clock signals of the root node, child node and leaf node in the clock tree. The non-leaf nodes in the clock tree may include clock sources, dividers and multipliers and other devices. Further, the configuration file of the preset clock tree can be obtained by a specific method, and the specific generation method is not limited here. Furthermore, the input clock of the preset clock tree is generated by the root node or obtained from the upper end, and then transmitted through the connection path of the clock tree until it reaches the leaf node, thereby completing the clock configuration of the leaf node. In the layer-by-layer transmission process, the input clock of the next-level node of the non-leaf node may be different from the input clock of the non-leaf node. Therefore, the clock identifier is used to determine whether to perform clock inheritance, that is, the non-leaf node needs to determine whether to change the input clock to the next-level node through the clock identifier. The test parameters may include the connection relationship of each circuit board to be tested, IP address, file path, test parameters and clock frequency of this test and other information.

[0034] Specifically, the test data and test requirements of this test can be determined by acquiring the configuration file and test information. Furthermore, the input clock of the circuit board to be tested in this test task can be determined according to the configuration file by the method of the embodiment of the present invention.

[0035] Step 120: Determine a clock configuration path of the preset clock tree according to the configuration file, and determine an input clock of the circuit board to be tested according to the clock configuration path, a clock identifier and an input clock of the preset clock tree.

[0036] The clock configuration path is the path where the input clock of the preset clock tree is transmitted according to the connection path of the preset clock tree and finally reaches the leaf node. The input clock of the preset clock tree needs to extend the clock configuration path, configure the input clock of each node on the clock configuration path, and finally determine the input clock of the circuit board to be tested.

[0037] Specifically, the input clock of the next-level node corresponding to the clock identifier can be determined through the clock identifier of the node on the clock configuration path, and the input clock of the circuit board to be tested can be finally determined by determining the input clock layer by layer.

[0038] Step 130: Generate a test script according to the input clock and test parameters of the circuit board to be tested, and test the circuit board to be tested using the test script.

[0039] Optionally, generating a test script according to the input clock and test parameters of the circuit board to be tested includes:

[0040] Acquire a script template corresponding to the preset clock tree, wherein the script template includes a circuit board identifier of a circuit board to be tested represented by a leaf node of the target clock tree;

[0041] According to the circuit board identifier of the circuit board to be tested, determining the filling position of the circuit board to be tested corresponding to the script template and the test parameters for the circuit board to be tested in the test information;

[0042] The script template is filled in according to the input clock and test parameters of the circuit board to be tested to generate a test script.

[0043] Specifically, the script template is a preset template, which includes the test code of this test task. It is necessary to fill the script template with content according to the specific requirements of this test task, and then generate a test script. The circuit board identifier is the specific information of the circuit board, such as the circuit board ID, number or IP address. At the same time, since the test parameters of different test tasks are different, it is also necessary to fill the test parameters for the circuit board to be tested into the corresponding position of the script template according to the circuit board identifier, and then generate a test script. Among them, the test parameters can include the time, clock frequency, test path and other parameters of this test.

[0044] It should be noted that the test script also includes information about the power-on and power-off process during the test, and the test script can be used to complete the power-on and power-off tests on multiple circuit boards to be tested.

[0045] An embodiment of the present invention provides a test method, which includes: obtaining a configuration file and test information of a preset clock tree, wherein the preset clock tree includes leaf nodes and non-leaf nodes, the leaf nodes represent a circuit board to be tested, the configuration file includes a clock identifier, the clock identifier is used to determine whether the next-level node of the non-leaf node inherits the clock, and the test information includes the input clock and test parameters of the preset clock tree; determining the clock configuration path of the preset clock tree according to the configuration file, and determining the input clock of the circuit board to be tested according to the clock configuration path, the clock identifier and the input clock of the preset clock tree; generating a test script according to the input clock and test parameters of the circuit board to be tested, and testing the circuit board to be tested through the test script. Specifically, the clock configuration path of the preset clock tree can be determined through the configuration file, and the input clock of each circuit board to be tested can be accurately determined through the clock configuration path. The technical solution of the present invention can accurately determine the input clock of the circuit board to be tested, thereby improving the test efficiency of the circuit board.

[0046] Embodiment 2

[0047] Figure 2A flowchart of a test method provided for Embodiment 2 of the present invention, this embodiment specifically defines a method for determining the clock configuration path of the preset clock tree according to the configuration file, and determining the input clock of the circuit board to be tested according to the clock configuration path, the clock identifier and the input clock of the preset clock tree.

[0048] like Figure 2 As shown, including:

[0049] Step 210, obtain the configuration file and test information of the preset clock tree, wherein the preset clock tree includes leaf nodes and non-leaf nodes, the leaf nodes represent the circuit board to be tested, the configuration file includes a clock identifier, the clock identifier is used to determine whether the next-level node of the non-leaf node inherits the clock, and the test information includes the input clock and test parameters of the preset clock tree.

[0050] Step 220: determine the child node of the root node according to the path identifier of the root node; determine the child node of the child node according to the path identifier of the child node, until the child node of the child node is a leaf node, and determine the connection path from the root node to the leaf node as the clock configuration path of the leaf node.

[0051] Among them, the configuration file also includes the path identifier of the non-leaf node of the preset clock tree, and the path identifier is used to determine the connection path of the non-leaf node, and the non-leaf node includes a root node and a child node.

[0052] Specifically, the configuration file of the preset clock tree includes the path identifier of each non-leaf node, and the path identifier is used to determine the connection path of the non-leaf node. For example, the path identifier may be the node serial number of the next-level node. Furthermore, the node connected to the non-leaf node can be determined based on the path identifier of the non-leaf node, and then the connection path of the non-leaf node can be determined. The starting point of the connection path is the root node, and the end point is the leaf node. Furthermore, the connection path from the root node to the leaf node can be determined as the clock configuration path of the leaf node.

[0053] Step 230: Determine the input clock of the preset clock tree as the input clock of the root node.

[0054] Optionally, the input clock of the root node may be generated by a clock source preconfigured by the root node, and may also be input to an upper-level input terminal of the root node.

[0055] Step 240: Determine the input clock of each node on the clock configuration path of the leaf node according to the input clock and clock identifier of the root node.

[0056] Specifically, based on the clock configuration path of the leaf node, it can be determined whether the next-level node of the non-leaf node needs clock inheritance according to the clock identifiers of the non-leaf nodes at each level. If the clock identifier of the non-leaf node indicates clock retention, the input clock of the non-leaf node is determined as the input clock of the next-level node; if the clock identifier of the non-leaf node indicates clock resetting, the input clock of the child node is re-adjusted through the clock board of the child node, and the re-adjusted clock is used as the input clock of the next-level node.

[0057] Since the input clock of the next-level node of a non-leaf node needs to be transmitted by the non-leaf node, and the input clock of the next-level node may be different from that of the leaf node, clock retention can be understood as the non-leaf node does not need to change its own input clock and can directly input it into the next-level node. Clock re-adjustment can be understood as the non-leaf node needs to readjust the clock of the next-level node and then use the re-adjusted clock as the input clock of the next-level node.

[0058] Optionally, the re-adjustment operation may include dividing or multiplying the input clock of the child node, which may be performed by a frequency divider or frequency multiplier configured in the child node, and in this way, the input clock may be changed, thereby finally making the input clock of the non-leaf node meet the requirements.

[0059] Figure 3 A schematic diagram of clock transmission provided by an embodiment of the present invention. Specifically, GCLK is a root node, and clock signals clk1 and clk2 can be sent to GCLK2 and GCLK3 respectively. Further, GCLK2 performs clock retention for the clock signal of circuit board MB1, that is, clk1 input to GCLK2 is sent to MB1, but GCLK3 performs a readjustment operation for the clock signal of MB2, readjusts clk2 to clk3, and uses clk3 as the input clock of MB2.

[0060] Step 250: Generate a test script according to the input clock and test parameters of the circuit board to be tested.

[0061] Step 260: Execute the test script to input the input clock of the circuit board to be tested into the circuit board to be tested.

[0062] Step 270: Receive a status response returned by the circuit board to be tested in response to the input clock.

[0063] After the input clock is sent to the circuit board to be tested, the circuit board to be tested will return a specific status response to the input clock to determine whether the clock signal completes the preset task or whether an error occurs.

[0064] Step 280: Determine an abnormal test circuit board according to the status response and the alarm condition.

[0065] Specifically, the status response may include a response time, a response code, etc. Therefore, the alarm condition may be whether the status response is received within a preset time period or the response code of the status response is a preset alarm code. Further, if the status response triggers the alarm condition, the circuit board to be tested corresponding to the status response is determined as an abnormal test circuit board.

[0066] Step 290: Determine the associated circuit boards of the abnormal test circuit board according to the communication connection relationship of each circuit board to be tested, and stop the test work of the abnormal test circuit board and the associated circuit boards.

[0067] Specifically, since the current equipment requires multiple circuit boards to be tested to work simultaneously, each circuit board to be tested has data association. Therefore, if one of the circuit boards to be tested is an abnormal test circuit board, the associated circuit boards of the abnormal test circuit board may also have data errors, affecting the test results. Therefore, it is necessary to stop the testing of the abnormal test circuit board and the associated circuit boards at the same time.

[0068] Furthermore, the test script also includes a program script for performing power-on and power-off tests on the circuit board to be tested. Figure 4 A schematic diagram of power on and off provided in an embodiment of the present invention, specifically, the system first scans all PDU (Power Distribution Unit, PDU) boards, performs power-on operations in sequence, and ensures that all power distribution units (can start normally and provide stable power support for the system. Specifically, after each PDU is powered on, the system will execute the result detection script to check whether the power-on operation is successful. If an error is detected, the system will stop the operation and exit the process. After the device is powered on, the system executes the result detection script again to detect to ensure the correctness of the operation. Further, after power-on, the clock frequency of the global clock board or the local main clock board will be set, the input clock of each circuit board will be determined, and the circuit board will be tested for clock to ensure that the clock signal of the system is synchronized. After the system sets the clock, it executes the result detection script to confirm whether the clock setting is correct. During the test, the system downloads the design file to all circuit boards according to the test information. After downloading the design file, the system runs the result detection script again to ensure that the design file is correctly loaded into the FPGA. Further, after completing the power-on test, the system executes the power-off operation of the circuit board to be tested, turns off the power of each PDU in turn, and determines whether it is powered off normally through the result detection script.

[0069] Optionally, the test task may also include clock frequency verification: checking whether the actual frequency of the clock signal is consistent with the value defined in the test information. File path verification: verifying whether the loaded FPGA BIN file path matches the test information definition.

[0070] The embodiment of the present invention provides a test method, which can determine the clock configuration path of the preset clock tree through the configuration file, and can accurately determine the input clock of each circuit board to be tested through the clock configuration path. The technical solution of the present invention can accurately determine the input clock of the circuit board to be tested, thereby improving the test efficiency of the circuit board. Furthermore, the test script also includes a script for powering on and off the circuit board to be tested, which can realize automatic powering on and off of the circuit board to be tested, thereby improving the test efficiency.

[0071] The present application also provides a specific embodiment of circuit board testing. In the generation stage of the test script, a power management script for controlling the power supply of the circuit board to be tested will also be generated, including control commands for the PDU and power board of the circuit board to be tested. In the power-on process, the system will first detect and control the power-on status of all PDUs and generate corresponding power-on scripts; at the same time, the customized power board is scanned and detected, and a power-on control command is generated to support users to insert customized scripts, that is, in the process of power-on and power-off script execution, multiple customized scripts can be executed sequentially / synchronously, such as the test script (clock configuration script) for clock detection described in the embodiment of the present invention and the FPGA file loading script in the circuit board test process. Further, in each step of the script in real time, error detection of the test results will be performed and a record log will be generated. If a certain step fails, the system will immediately stop the subsequent operation and generate an error log for the user to check. This mechanism ensures the smooth progress of the entire power-on and power-off process, avoiding system failures due to operational errors.

[0072] Specifically, the abnormality check and stop mechanism runs through all the processes of script execution, including: covering three modules: power management, clock configuration, and FPGA file loading. This mechanism realizes real-time monitoring of abnormal status through means such as device response detection, configuration consistency verification, log analysis, and abnormal pattern recognition. Once an abnormality is found, the system will terminate the current task and record relevant information.

[0073] Specifically, abnormal inspection includes:

[0074] (1) Device response detection on the circuit board to be tested: Timeout detection: If the device does not respond to the ACK (Acknowledge character) signal within the specified time, it is judged as abnormal. Error status code detection: If the status code returned by the device does not meet the expectations (such as the FPGA loading status is not successful), it is recorded as an abnormality. Connectivity verification: Check whether the device connection is normal, for example, confirm whether the device is accessible through the ping command.

[0075] (2) About the consistency check of test parameters: The system will compare the current device status with the expected value in the test information to ensure that the device configuration meets the design requirements: Clock frequency check: Check whether the actual frequency of the clock signal is consistent with the value defined in the test information. File path check: Verify whether the loaded FPGA BIN file path matches the test information.

[0076] (3) Log analysis and abnormal pattern identification: By recording log information in real time during task execution, the system can identify potential abnormal patterns: Repeated error pattern: The same command fails to execute multiple times. Unparsed command: The system cannot recognize certain configuration commands, resulting in task interruption. Dependency error: The upstream device that the downstream device depends on is not successfully configured.

[0077] Specifically, regarding exception handling:

[0078] (1) Test stop: Once an abnormality is detected, the system will immediately terminate the subsequent operations of the current task to prevent the problem from spreading. For example, if the PDU fails to power on, the power-on operation of all downstream devices will be terminated. If the FPGA file fails to load, the file loading tasks of other FPGAs will be stopped.

[0079] (2) Exception information recording: The system will record the details of the exception in the log file to facilitate user troubleshooting. The recorded content includes: Timestamp: Marks the time when the exception occurred. Device information: IP address and type of the abnormal device (such as PDU, clock board, FPGA). Task information: The specific command executed and its parameters. Exception details: such as timeout, status code mismatch or file path error.

[0080] Furthermore, the beneficial effects of the embodiments of the present invention can be described from the following aspects:

[0081] Fully automated operation:

[0082] The present invention greatly reduces the complexity and error rate of manual operation by generating and executing power-on and power-off scripts with one click. In the prior art, operators need to manually configure the power supply, clock and file loading of each FPGA circuit board step by step. The present invention parses XML (eXtensible Markup Language) or similar format configuration files to automatically generate bash or bat scripts suitable for different operating systems, thus automating the entire process. This automation not only reduces manual intervention and the risk of errors, but also improves the overall efficiency of system configuration.

[0083] Efficient multi-board and multi-device management:

[0084] In the prior art, the management of multi-board systems usually relies on semi-automatic tools or manual configuration, which is time-consuming and error-prone. The present invention supports the parallel operation of multiple boards and multiple devices, and significantly improves the efficiency of power-on and power-off operations of the system by automatically detecting the status of each circuit board and generating corresponding control scripts. The configuration of multiple circuit boards and devices can be completed in a short time, effectively reducing the time cost of system startup and shutdown, and adapting to complex verification environments.

[0085] Enhanced system reliability:

[0086] The present invention introduces an automatic detection and judgment mechanism for script execution results, ensuring the accuracy of each operation step and the stability of the system. In the prior art, the results after script execution usually cannot be fed back in real time, and it is difficult for operators to find and correct errors in time. The present invention ensures that all configurations are completed correctly by monitoring the execution of each step of the operation in real time. If an abnormality occurs, the operation is stopped immediately and a log is recorded to avoid system failures caused by operation errors.

[0087] Flexible and scalable configuration capabilities:

[0088] The present invention allows users to easily adjust system configurations by simply modifying configuration files to support customized needs. This flexibility enables the system to be customized according to different application scenarios to meet diverse needs. Users can also insert custom commands into automatically generated scripts to further enhance the system's expansion capabilities.

[0089] Cross-platform compatibility:

[0090] The script generated by the present invention is compatible with different operating systems, such as Windows and Linux. This cross-platform compatibility enables the system to run stably in different operating environments. Existing partial automation tools often lack support for multiple operating systems, while the script generation method of the present invention ensures consistency and reliability in multiple operating system environments, greatly enhancing the adaptability of the system. This versatility enables the method of the present invention to be promoted and applied in different FPGA verification systems, with good adaptability and portability.

[0091] Reduce costs and reduce processes:

[0092] Through comprehensive automation and efficient parallel operation, the present invention significantly reduces the time cost and human resource investment of manual operation. In the prior art, the manual configuration and verification process is complicated and lengthy, while the automated process of the present invention reduces unnecessary operation steps, making the configuration and verification process of the entire system smoother. At the same time, by reducing configuration errors, the present invention also reduces the debugging and repair costs caused by errors. These effects are directly reflected in the shortening of project cycles and the reduction of development costs, which are particularly important for large-scale FPGA verification systems.

[0093] Embodiment 3

[0094] Figure 5 This is a schematic diagram of the structure of a test device provided in Embodiment 3 of the present invention. Figure 5 As shown, the device comprises:

[0095] An acquisition module 310 is used to acquire a configuration file and test information of a preset clock tree, wherein the preset clock tree includes leaf nodes and non-leaf nodes, the leaf nodes represent the circuit board to be tested, the configuration file includes a clock identifier, the clock identifier is used to determine whether the next-level node of the non-leaf node inherits the clock, and the test information includes the input clock and test parameters of the preset clock tree;

[0096] A clock determination module 320, configured to determine a clock configuration path of the preset clock tree according to the configuration file, and determine an input clock of the circuit board to be tested according to the clock configuration path, a clock identifier and an input clock of the preset clock tree;

[0097] The testing module 330 is used to generate a test script according to the input clock and test parameters of the circuit board to be tested, and test the circuit board to be tested through the test script.

[0098] An embodiment of the present invention provides a testing device, which can determine the clock configuration path of a preset clock tree through a configuration file, and can accurately determine the input clock of each circuit board to be tested through the clock configuration path. The technical solution of the present invention can accurately determine the input clock of the circuit board to be tested, thereby improving the testing efficiency of the circuit board.

[0099] Optionally, the clock determination module 320 includes:

[0100] A clock configuration path determination unit and an input clock determination unit.

[0101] A clock configuration path determination unit, comprising:

[0102] A subnode determining subunit, which determines a subnode of the root node according to a path identifier of the root node;

[0103] The clock configuration path determination subunit determines the child node of the child node according to the path identifier of the child node, until the child node of the child node is a leaf node, and determines the connection path from the root node to the leaf node as the clock configuration path of the leaf node.

[0104] The input clock determination unit includes:

[0105] A root node input clock determination subunit, used to determine the input clock of the preset clock tree as the input clock of the root node;

[0106] The input clock determination subunit is used to determine the input clock of each node on the clock configuration path of the leaf node according to the input clock and clock identifier of the root node.

[0107] Optionally, the input clock determination subunit is specifically used to determine the input clock of the non-leaf node as the input clock of the next-level node based on any clock configuration path. If the clock identifier of the non-leaf node represents clock retention, the input clock of the non-leaf node is determined as the input clock of the next-level node; if the clock identifier of the non-leaf node represents clock re-adjustment, the input clock of the child node is re-adjusted through the clock board of the child node, and the re-adjusted clock is used as the input clock of the next-level node.

[0108] Optionally, the input clock determination subunit is specifically used to: divide or multiply the input clock of the sub-node to generate a re-adjusted clock.

[0109] Optionally, the test module 330 includes: a test script generation unit and a test unit.

[0110] The test script generation unit includes:

[0111] A template determination subunit, configured to obtain a script template corresponding to the preset clock tree, wherein the script template includes a circuit board identifier of a circuit board to be tested represented by a leaf node of the target clock tree;

[0112] A content determination subunit, configured to determine, according to a circuit board identifier of the circuit board to be tested, a filling position of the script template corresponding to the circuit board to be tested and a test parameter for the circuit board to be tested in the test information;

[0113] The generating subunit is used to fill in the script template and generate a test script according to the input clock and test parameters of the circuit board to be tested.

[0114] The test unit includes:

[0115] An execution subunit, configured to execute the test script and input the input clock of the circuit board to be tested into the circuit board to be tested;

[0116] A receiving subunit, configured to receive a status response returned by the circuit board to be tested in response to the input clock;

[0117] an abnormality determination subunit, for determining an abnormal test circuit board according to the state response and the alarm condition;

[0118] The closing subunit is used to determine the associated circuit boards of the abnormal test circuit board according to the communication connection relationship of each circuit board to be tested, and stop the test work of the abnormal test circuit board and the associated circuit boards.

[0119] The testing device provided in the embodiment of the present invention can execute the testing method provided in any embodiment of the present invention, and has the functional modules and beneficial effects corresponding to the execution method.

[0120] Embodiment 4

[0121] Figure 6 A schematic diagram of the structure of an electronic device 10 provided for implementing the fourth embodiment of the present invention. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices (such as helmets, glasses, watches, etc.) and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or required herein.

[0122] like Figure 6 As shown, the electronic device 10 includes at least one processor 11, and a memory connected to the at least one processor 11, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc., wherein the memory stores a computer program that can be executed by at least one processor, and the processor 11 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 12 or the computer program loaded from the storage unit 18 to the random access memory (RAM) 13. In the RAM 13, various programs and data required for the operation of the electronic device 10 can also be stored. The processor 11, the ROM 12, and the RAM 13 are connected to each other through a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0123] A number of components in the electronic device 10 are connected to the I / O interface 15, including: an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a disk, an optical disk, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0124] The processor 11 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The processor 11 executes the various methods and processes described above, such as the test method.

[0125] In some embodiments, the test method may be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as a storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 10 via the ROM 12 and / or the communication unit 19. When the computer program is loaded into the RAM 13 and executed by the processor 11, one or more steps of the test method described above may be performed. Alternatively, in other embodiments, the processor 11 may be configured to execute the test method in any other appropriate manner (e.g., by means of firmware).

[0126] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0127] Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when the computer program is executed by the processor, the functions / operations specified in the flow chart and / or block diagram are implemented. The computer program may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0128] In the context of the present invention, a computer-readable storage medium may be a tangible medium that may contain or store a computer program for use by or in combination with an instruction execution system, device or equipment. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or equipment, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0129] To provide interaction with a user, the systems and techniques described herein may be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or trackball) through which the user can provide input to the electronic device. Other types of devices may also be used to provide interaction with the user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form (including acoustic input, voice input, or tactile input).

[0130] The systems and techniques described herein may be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0131] A computing system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The client and server relationship is generated by computer programs running on the corresponding computers and having a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system to solve the defects of difficult management and weak business scalability in traditional physical hosts and VPS services.

[0132] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0133] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A testing method, characterized in that: include: Obtain a configuration file and test information of a preset clock tree, wherein the preset clock tree includes leaf nodes and non-leaf nodes, the leaf nodes represent the circuit board to be tested, the configuration file includes a clock identifier, the clock identifier is used to determine whether the next-level node of the non-leaf node inherits the clock, and the test information includes the input clock and test parameters of the preset clock tree; Determine a clock configuration path of the preset clock tree according to the configuration file, and determine an input clock of the circuit board to be tested according to the clock configuration path, a clock identifier and an input clock of the preset clock tree; A test script is generated according to the input clock and test parameters of the circuit board to be tested, and the circuit board to be tested is tested by using the test script.

2. The method according to claim 1, characterized in that The configuration file also includes a path identifier of a non-leaf node of a preset clock tree, wherein the path identifier is used to determine a connection path of the non-leaf node, and the non-leaf node includes a root node and a child node; The step of determining a clock configuration path of the preset clock tree according to the configuration file includes: Determine the child nodes of the root node according to the path identifier of the root node; The child node of the child node is determined according to the path identifier of the child node, until the child node of the child node is a leaf node, and the connection path from the root node to the leaf node is determined as the clock configuration path of the leaf node.

3. The method according to claim 2, characterized in that The step of determining the input clock of the circuit board to be tested according to the clock configuration path, the clock identifier and the input clock of the preset clock tree comprises: Determine the input clock of the preset clock tree as the input clock of the root node; According to the input clock and clock identifier of the root node, the input clock of each node on the clock configuration path of the leaf node is determined.

4. The method according to claim 3, characterized in that The next level node includes a child node or a leaf node; The step of determining the input clock of each node on the clock configuration path of the leaf node according to the input clock and the clock identifier of the root node includes: Based on any clock configuration path, if the clock identifier of the non-leaf node indicates clock retention, the input clock of the non-leaf node is determined as the input clock of the next-level node; If the clock identification of the non-leaf node is characterized by clock resetting, the input clock of the child node is re-adjusted through the clock board of the child node, and the re-adjusted clock is used as the input clock of the next-level node.

5. The method according to claim 4, characterized in that The re-adjusting the input clock of the sub-node by the clock board of the sub-node includes: The input clock of the sub-node is divided or multiplied to generate a re-adjusted clock.

6. The method according to claim 1, characterized in that The step of generating a test script according to the input clock and test parameters of the circuit board to be tested includes: Acquire a script template corresponding to the preset clock tree, wherein the script template includes a circuit board identifier of a circuit board to be tested represented by a leaf node of the target clock tree; According to the circuit board identifier of the circuit board to be tested, determining the filling position of the circuit board to be tested corresponding to the script template and the test parameters for the circuit board to be tested in the test information; The script template is filled in according to the input clock and test parameters of the circuit board to be tested to generate a test script.

7. The method according to claim 1, characterized in that The test information also includes the communication connection relationship of each circuit board to be tested. The testing of the circuit board to be tested by using the test script includes: Executing the test script to input the input clock of the circuit board to be tested into the circuit board to be tested; receiving a status response returned by the circuit board to be tested in response to the input clock; Determine an abnormal test circuit board based on the status response and alarm conditions; According to the communication connection relationship of each circuit board to be tested, the associated circuit board of the abnormal test circuit board is determined, and the test work of the abnormal test circuit board and the associated circuit boards is stopped.

8. A testing device, characterized in that: include: An acquisition module, used to acquire a configuration file and test information of a preset clock tree, wherein the preset clock tree includes leaf nodes and non-leaf nodes, the leaf nodes represent the circuit board to be tested, the configuration file includes a clock identifier, the clock identifier is used to determine whether the next-level node of the non-leaf node inherits the clock, and the test information includes the input clock and test parameters of the preset clock tree; A clock determination module, used to determine a clock configuration path of the preset clock tree according to the configuration file, and determine an input clock of the circuit board to be tested according to the clock configuration path, a clock identifier and an input clock of the preset clock tree; The test module is used to generate a test script according to the input clock and test parameters of the circuit board to be tested, and test the circuit board to be tested through the test script.

9. An electronic device, characterized in that: The electronic device comprises: at least one processor; and, a memory communicatively connected to the at least one processor; wherein, The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can perform the testing method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the testing method according to any one of claims 1 to 7 when executed.

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