Built-in test circuit, isolated gate drive chip, test platform and method

Abstract

The present application relates to a built-in test circuit, an isolated gate driver chip, a test platform and a method. The built-in test circuit of the present application includes: a low-voltage side test circuit, which is constructed in the low-voltage side die of the isolated gate driver chip, and is used to generate a test signal and provide it to the low-voltage side signal transceiver channel in the low-voltage side die, so as to determine the low-voltage side signal according to the test signal through the low-voltage side signal transceiver channel and transmit the output to the high-voltage side die of the isolated gate driver chip to obtain a return signal; and the test result is obtained based on the test signal and the return signal; and a high-voltage side test circuit, which is constructed in the high-voltage side die of the isolated gate driver chip, and is used to convert the high-voltage side signal and return it to the low-voltage side die. The present application can realize the built-in self-test of the chip, reduce the test cost, and improve the test efficiency.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a built-in test circuit, an isolated gate drive chip, a test platform and a method. Background Art

[0002] Isolated gate driver chips (also called isolated gate drivers or isolated gate drivers) are mainly used to drive power devices such as power transistors and MOSFETs (metal oxide semiconductor field effect transistors, MOS tubes for short), and have the characteristics of electrical isolation, high and low voltage isolation, high-speed response and low power consumption. The working principle of isolated gate driver chips is to transmit low-voltage control signals to the high-voltage end through the sending circuit, receiving circuit and high-voltage isolation capacitor inside the chip to control the on and off state of the power device.

[0003] At present, the test of isolated gate driver chips is mainly the final test (FT), which is the test performed after the chip is packaged. The test platform needs to use independent equipment such as PCB test board, signal generator, power module, etc., which leads to complex test process, high cost, low efficiency and long test time. Summary of the invention

[0004] In view of this, embodiments of the present application provide a built-in test circuit, an isolated gate driver chip, a wafer, a test platform and a test method to solve at least one problem existing in the background technology.

[0005] In a first aspect, an embodiment of the present application provides a built-in test circuit, which is applied to an isolated gate driver chip. The built-in test circuit includes:

[0006] A low-voltage side test circuit is constructed in the low-voltage side die of the isolated gate driver chip, and is used to generate a test signal and provide it to the low-voltage side signal transceiver channel in the low-voltage side die, so that the low-voltage side signal is determined according to the test signal through the low-voltage side signal transceiver channel and transmitted to the high-voltage side die of the isolated gate driver chip, so that the high-voltage side signal transceiver channel in the high-voltage side die determines the high-voltage side signal according to the low-voltage side signal and returns it to the low-voltage side die; and determines the return signal according to the high-voltage side signal; and based on the test signal and the return signal, checks and determines the test result of the isolated gate driver chip; and

[0007] The high-voltage side test circuit is constructed in the high-voltage side die of the isolated gate driver chip, and is used to convert the high-voltage side signal and transmit and output it to the high-voltage side signal transceiver channel to return it to the low-voltage side die.

[0008] In combination with the first aspect, in an optional implementation,

[0009] The low voltage side test circuit comprises:

[0010] A signal generator, used for generating the test signal;

[0011] a low-voltage side receiver, configured to obtain a return low-frequency signal determined according to the high-voltage side signal, and convert the return low-frequency signal into a return signal corresponding to the test signal; and

[0012] A checker, configured to generate and output a first result signal to indicate that the isolated gate driver chip works normally when the test signal and the return signal satisfy a preset corresponding relationship; and to generate and output a second result signal to indicate that the isolated gate driver chip works abnormally when the test signal and the return signal do not satisfy the preset corresponding relationship;

[0013] And / or, the high-voltage side test circuit comprises:

[0014] The high-voltage side transmitter is used to obtain the high-voltage side signal and convert the high-voltage side signal into an intermediate signal for returning to the low-voltage side test circuit so that the low-voltage side test circuit obtains the return signal.

[0015] In combination with the first aspect, in an optional implementation,

[0016] The low voltage side test circuit also includes:

[0017] A low-voltage side controller, at least used to control the signal generator to generate the test signal; and control the checker to compare the test signal and the return signal to obtain a test result of the isolated gate driver chip;

[0018] And / or, the high-voltage side test circuit further includes:

[0019] The high-voltage side controller is at least used to control the high-voltage side transmitter to obtain the high-voltage side signal and convert the high-voltage side signal into an intermediate signal.

[0020] In combination with the first aspect, in an optional implementation,

[0021] The built-in test circuit also includes:

[0022] A first pin is used to obtain a test start enable signal and provide it to the low-voltage side test circuit to control the isolated gate drive chip to enter a test phase;

[0023] A second pin, used for outputting the test result;

[0024] Wherein, the first pin and the second pin are constructed in the low-voltage side tube core.

[0025] In a second aspect, an embodiment of the present application provides an isolated gate driver chip, wherein the isolated gate driver chip includes a low-voltage side die and a high-voltage side die;

[0026] Among them, the isolated gate drive chip also includes a built-in test circuit as described in the first aspect; the built-in test circuit includes a low-voltage side test circuit constructed in the low-voltage side die and a high-voltage side test circuit constructed in the high-voltage side die.

[0027] In conjunction with the second aspect, in an optional implementation,

[0028] The isolated gate driver chip further includes a low-voltage side signal transceiver channel constructed in the low-voltage side tube core and a high-voltage side signal transceiver channel constructed in the high-voltage side tube core;

[0029] The low-voltage side signal transceiver channel is at least used to determine a test high-frequency signal according to a test signal provided by the low-voltage side test circuit, and transmit the test high-frequency signal; receive a return high-frequency signal, and determine a return low-frequency signal according to the return high-frequency signal, so that the low-voltage side test circuit determines a return signal according to the return low-frequency signal;

[0030] The high-voltage side signal transceiver channel is at least used to receive the test high-frequency signal, and determine the high-voltage side signal based on the test high-frequency signal, so that the high-voltage side test circuit determines the intermediate signal based on the high-voltage side signal; and determines the return high-frequency signal based on the intermediate signal, and transmits the return high-frequency signal.

[0031] In a third aspect, an embodiment of the present application provides a wafer, wherein the wafer includes one or more dies;

[0032] Wherein, the crystal grains are used to form the isolated gate driving chip as described in the second aspect.

[0033] In a fourth aspect, an embodiment of the present application provides a test platform, the test platform comprising a power supply, a multimeter, and the isolated gate drive chip as described in the second aspect;

[0034] The power supply is used to supply power to the isolated gate drive chip;

[0035] The multimeter is used to read the test result output by the isolated gate drive chip.

[0036] In a fifth aspect, an embodiment of the present application provides a test platform, the test platform comprising a test probe and the wafer as described in the third aspect;

[0037] The test probes include a first short-circuit probe group, a second short-circuit probe group, a first signal probe, a second signal probe, a first power supply probe, and a second power supply probe;

[0038] The first short-circuit probe group includes a pair of short-circuit probes for connecting a channel between a low-voltage side modem and a high-voltage side modem in any one of the dies forming the isolated gate drive chip on the wafer; the second short-circuit probe group includes a pair of short-circuit probes for connecting another channel between the low-voltage side modem and the high-voltage side modem;

[0039] The first signal probe is used to provide a test start enable signal to a first pin of the die;

[0040] The second signal probe is used to obtain a test result output by a second pin of the die;

[0041] The first power probe is used to supply power to the low voltage side die of the die;

[0042] The second power probe is used to supply power to the high-voltage side die of the die.

[0043] In a sixth aspect, an embodiment of the present application provides a testing method, the testing method comprising:

[0044] The low voltage side test circuit generates and outputs a test signal;

[0045] The low-voltage side signal transceiver channel generates a low-voltage side signal according to the test signal and transmits it for output;

[0046] The high-voltage side signal transceiver channel generates and outputs a high-voltage side signal according to the low-voltage side signal;

[0047] The high-voltage side test circuit converts the high-voltage side signal and transmits it to the high-voltage side signal transceiver channel for output;

[0048] The low-voltage side test circuit obtains the signal transmitted by the high-voltage side signal transceiver channel through the low-voltage side signal transceiver channel and determines a return signal based on the signal; and based on the test signal and the return signal, checks and determines the test result of the isolated gate drive chip.

[0049] The beneficial effects of the technical solution provided by the embodiment of the present application include: by constructing a low-voltage side test circuit in the low-voltage side die of the isolated gate driver chip and a high-voltage side test circuit in the high-voltage side die, that is, a chip-built-in test circuit, the chip's built-in self-test can be realized, thereby avoiding the use of expensive signal generators and other equipment, which can greatly reduce the test cost. It can also be applied to on-wafer testing in the CP stage, automatically detect, and by reserving a test PAD (pin) on the die, the test result can also be output to the test PAD, so that the voltage of the test PAD can be directly measured to determine whether the chip is defective, thereby simplifying the test result judgment process, improving test efficiency and shortening test time.

[0050] Additional aspects and advantages of the embodiments of the present application will be given in part in the description below and in part will become apparent from the description below or will be learned through the practice of the embodiments of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The drawings are not necessarily drawn to scale, and local features may be enlarged or reduced to more clearly show the details of the local features. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0052] Figure 1 A schematic diagram of a principle block diagram of a specific example of a test platform in the related art;

[0053] Figure 2 A schematic diagram of a principle block diagram of a specific example of a built-in test circuit in an embodiment of the present application;

[0054] Figure 3 A schematic diagram of a specific example of a signal flow in an embodiment of the present application;

[0055] Figure 4 It is a schematic diagram of a principle block diagram of a specific example of an isolated gate driver chip in an embodiment of the present application.

[0056] Figure 5 It is a schematic diagram of a principle block diagram of another specific example of an isolated gate driver chip in an embodiment of the present application;

[0057] Figure 6 It is a schematic diagram of a principle block diagram of another specific example of the isolated gate driving chip in the embodiment of the present application;

[0058] Figure 7 A schematic diagram of a principle block diagram of a specific example of a wafer in an embodiment of the present application;

[0059] Figure 8 A schematic diagram of a principle block diagram of a specific example of a test platform in an embodiment of the present application;

[0060] Fig. 9 A schematic diagram of a principle block diagram of another specific example of a test platform in an embodiment of the present application;

[0061] Fig.10 A schematic diagram of a principle block diagram of a specific example of the testing method in the embodiment of the present application. DETAILED DESCRIPTION

[0062] In order to make the technical solutions and beneficial effects of the present invention more clearly understandable, the following is a detailed description by listing specific embodiments. The drawings are not necessarily drawn to scale, and local features may be enlarged or reduced to more clearly show the details of the local features; unless otherwise defined, the technical and scientific terms used herein have the same meanings as those in the technical field to which this application belongs.

[0063] The embodiments of the present application are not exhaustive, but are only illustrative of some embodiments, and are not intended to be a specific limitation on the scope of protection of the present application. In the absence of contradiction, each step in a certain embodiment can be implemented as an independent embodiment, and the steps can be arbitrarily combined. For example, in a certain embodiment, the solution after removing some steps can also be implemented as an independent embodiment, and the order of the steps in a certain embodiment can be arbitrarily exchanged. In addition, the optional implementations in a certain embodiment can be arbitrarily combined; in addition, the embodiments can be arbitrarily combined, for example, some or all of the steps of different embodiments can be arbitrarily combined, and a certain embodiment can be arbitrarily combined with the optional implementations of other embodiments.

[0064] In each embodiment of the present application, unless otherwise specified or there is a logical conflict, the terms and / or descriptions between the embodiments are consistent and can be referenced to each other. The technical features in different embodiments can be combined to form a new embodiment based on their internal logical relationships.

[0065] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments and are not intended to limit the present application.

[0066] In the embodiments of the present application, unless otherwise specified, elements expressed in the singular form, such as "a", "an", "the", "above", "said", "aforementioned", "this", etc., may mean "one and only one", or "one or more", "at least one", etc. For example, when using articles such as "a", "an", "the" in English in translation, the noun after the article may be understood as a singular expression or a plural expression.

[0067] In the embodiments of the present application, "plurality" refers to two or more.

[0068] In some embodiments, the terms "at least one", "one or more", "a plurality of", "multiple", etc. can be used interchangeably.

[0069] The prefixes such as "first" and "second" in the embodiments of the present application are only used to distinguish different description objects, and do not constitute restrictions on the position, order, priority, value or content of the description objects. The statement of the description object refers to the description in the context of the claims or embodiments, and should not constitute unnecessary restrictions due to the use of prefixes. For example, the numerical value of the description object is not limited by the ordinal number, and can be one or more. Take "first device" as an example, where the numerical value of "device" can be one or more. In addition, the objects modified by different prefixes can be the same or different. For example, if the description object is "device", the "first device" and the "second device" can be the same device or different devices, and their types can be the same or different.

[0070] In some embodiments, the term "connection" may indicate that an electrical signal or data is transmitted between a connected end and a connected end, and may be understood as "electrical connection", "communication connection", etc. "Connection" may be a direct connection between two components, an indirect connection established through other components, internal communication between two components, or any other possible connection form.

[0071] In some embodiments, terms such as "greater than", "greater than or equal to", "not less than", "more than", "more than or equal to", "not less than", "higher than", "higher than or equal to", "not less than", "above", and "exceed" can be replaced with each other, and terms such as "less than", "less than or equal to", "not greater than", "less than", "less than or equal to", "no more than", "lower than", "lower than or equal to", "not higher than", and "below" can be replaced with each other.

[0072] In some embodiments, high voltage and low voltage, or high voltage and low voltage, may be relative values, and are not limited to absolute values. High frequency and low frequency may be relative values, and are not limited to absolute values.

[0073] This specification provides method operation steps such as embodiments or flow charts, but may include more or fewer operation steps based on conventional or non-creative labor. The order of steps listed in the embodiments is only one way of executing the order of many steps and does not represent the only execution order. When the actual device, system or server product is executed, it can be executed in the order of the method shown in the embodiments or the drawings or in parallel (for example, in a parallel processor or multi-threaded processing environment).

[0074] Figure 1 A schematic diagram of a specific example of a test platform in the related art is shown. As shown in the figure, the test platform 100 of the isolated gate driver chip (hereinafter referred to as "chip") includes a signal generator (FunctionGenerator), one or more power supplies (Power Supply), one or more oscilloscopes (Oscilloscope), a PCB circuit board 104 and a connecting cable, which are used to perform performance testing on the chip 101 to be tested. The chip 101 includes a low-voltage side die (LV Die) and a high-voltage side die (HV Die) connected by wires.

[0075] The PCB circuit board 104 is provided with a terminal 103 and a chip pad, and a trace connecting the chip pad and the terminal 103. The chip pad is used to connect the pin 102 of the chip 101 to be tested. The terminal 103 includes a signal input terminal, a power supply terminal, a signal output terminal, etc., which can be a pin row or a PIN pin, etc. The signal input terminal is used to receive a test signal provided to the low-voltage side die. The power supply terminal is used to receive a power supply signal. The signal output terminal includes a first signal output terminal and a second signal output terminal; the first signal output terminal is used to output a first output signal determined and output by the high-voltage side die according to the test signal; the second signal output terminal is used to output a second output signal determined and output by the low-voltage side die according to the test signal.

[0076] The signal generator is connected to the signal input terminal through a connecting cable, and finally connected to the input terminal of the low-voltage side die through the wiring on the PCB circuit board 104, so as to generate and output a test signal.

[0077] The power source is connected to the power supply end through a connecting cable, and finally connected to the power supply input end of the chip 101 through the wiring on the PCB circuit board 104, so as to supply power to the chip 101.

[0078] The first oscilloscope is connected to the first signal output terminal through a connecting cable, and finally connected to the signal output terminal of the high-voltage side die through a trace on the PCB circuit board 104, for observing the output signal of the high-voltage side of the chip.

[0079] The second oscilloscope is connected to the second signal output terminal through a connecting cable, and finally connected to the signal output terminal of the low-voltage side die through the wiring on the PCB circuit board 104, for observing the output signal of the low-voltage side of the chip.

[0080] During the test, not only the chip 101 to be tested needs to be connected to the PCB circuit board 104 first, but also the signal transmitter, oscilloscope and other equipment need to be connected to the PCB circuit board 104, and the test result needs to be manually judged based on the waveform displayed by the oscilloscope.

[0081] It can be seen that the test process of using the test platform 100 to perform performance testing on the chip 101 to be tested is complicated; and at least an expensive signal generator and an oscilloscope are required; and manual judgment of the test results is required, which results in high cost, low test efficiency, and long time. In addition, the packaged chip 101 cannot be tested in the wafer testing (Chip Probing, abbreviated as CP, which is a test performed before chip packaging) stage.

[0082] To this end, an embodiment of the present application provides a built-in test circuit that can be applied to an isolated gate driver chip. Figure 2 The schematic diagram of the principle block diagram of a specific example of the built-in test circuit in the embodiment of the present application is shown. As shown in the figure, the built-in test circuit 200 includes:

[0083] A low-voltage side test circuit 200_1 is constructed in the low-voltage side die (LV Die) of the isolated gate driver chip, and is used to generate a test signal and provide it to the low-voltage side signal transceiver channel in the low-voltage side die, so that the low-voltage side signal is determined according to the test signal through the low-voltage side signal transceiver channel and transmitted to the high-voltage side die of the isolated gate driver chip, so that the high-voltage side signal transceiver channel in the high-voltage side die determines the high-voltage side signal according to the low-voltage side signal and returns it to the low-voltage side die; and determines the return signal according to the high-voltage side signal; and based on the test signal and the return signal, checks and determines the test result of the isolated gate driver chip; and

[0084] The high-voltage side test circuit 200_2 is constructed in the high-voltage side die (HV Die) of the isolated gate driver chip, and is used to convert the high-voltage side signal and transmit it to the high-voltage side signal transceiver channel for output, so as to return it to the low-voltage side die.

[0085] In some examples, the low-voltage side signal transceiver channel of the low-voltage side die in the isolated gate driver chip may include a signal input module 210 , a multiplexer 202 , a low-voltage side transmitter 203 , and a low-voltage side modem 204 .

[0086] Among them, the signal input module 210 can be used to obtain and output the signal to be transmitted, such as the control signal (such as a pulse width modulation PWM signal) when the chip is working normally. The multiplexer 202 can be used to select a signal output from multiple input signals, such as selecting a signal output from the signal to be transmitted output by the signal input module 210 and the test signal generated and output by the signal generator 201. When the chip is working normally, the multiplexer 202 can output the signal to be transmitted; when the chip is tested, the multiplexer 202 can output the test signal. The low-voltage side transmitter 203 can be used to convert the input signal into a signal (such as voltage or current) suitable for transmission to drive the power device, and may include a signal amplifier, etc. The low-voltage side modem 204 can be used to modulate the input low-frequency signal into a high-frequency signal and output it, or demodulate the input high-frequency signal into a low-frequency signal and output it.

[0087] In some examples, the high-side signal transceiver channel of the high-side die in the isolated gate driver chip may include a high-side modem 211 and a high-side receiver 212 .

[0088] The high-voltage side modem 211 can be used to demodulate the input high-frequency signal into a low-frequency signal and output it, or modulate the input low-frequency signal into a high-frequency signal and output it. The high-voltage side receiver 212 can be used to convert the input signal into a signal (such as voltage or current) suitable for driving a power device, and can include a signal amplifier, etc.

[0089] Then, reference Figure 2 and Figure 3 , Figure 3 A schematic diagram of a specific example of a signal flow in an embodiment of the present application is shown. In the low-voltage side tube core, a low-voltage side modem 204 in a low-voltage side signal transceiver channel can be used to modulate a test low-frequency signal S2 (the test signal S1 is converted by a low-voltage side transmitter 203 to obtain a test low-frequency signal S2, i.e., a low-voltage side signal) input to the low-voltage side modem 204 and determined according to the test signal, into a test high-frequency signal S3 and transmit the signal for output.

[0090] In the high-voltage side die, the high-voltage side modem 211 in the high-voltage side signal transceiver channel can be used to demodulate the test high-frequency signal S3 input to the high-voltage side modem 211 into a test low-frequency signal S4, and output it to the high-voltage side receiver 212 to convert it into a high-voltage side signal S5.

[0091] Furthermore, in the high-voltage side die, the high-voltage side modem 211 in the high-voltage side signal transceiver channel can be used to modulate the low-frequency intermediate signal S6 (the high-voltage side signal S5 is converted by the high-voltage side transmitter 213 to obtain the intermediate signal S6) input to the high-voltage side modem 211 into a return high-frequency signal S7 and transmit it for output.

[0092] In the low-voltage side tube core, the low-voltage side modem 204 in the low-voltage side signal transceiver channel can be used to demodulate the return high-frequency signal S7 input to the low-voltage side modem 204 into a return low-frequency signal S8, and output it to the low-voltage side test circuit 200_1; then, the low-voltage side test circuit 200_1 converts the return low-frequency signal S8 into a return signal S9 corresponding to the test signal S1 (the return low-frequency signal S8 is converted by the low-voltage side receiver 205 to obtain the return signal S9); and then the test signal and the return signal can be checked and compared to obtain the test result. For example, if the two are the same, it can be considered that the low-voltage side tube core and the high-voltage side tube core are working normally and have no defects.

[0093] In some examples, the correspondence between the test signal and the return signal can be preset according to the actual situation of factors such as the multiple relationship of signal conversion in the low-voltage side die and the high-voltage side die (such as signal amplification). For example, the test signal and the return signal can be preset to be the same, or can be preset to have a preset multiple relationship, so that in the actual test process, when checking and comparing the two, it is possible to make a judgment based on the preset correspondence and obtain the corresponding test results. For example, if the test signal and the actual return signal meet the preset correspondence, it can be considered that there is no defect; on the contrary, if it does not meet, it can be considered that there is a defect.

[0094] Thus, the embodiment of the present application constructs a low-voltage side test circuit in the low-voltage side tube core of the isolated gate driver chip, and constructs a high-voltage side test circuit in the high-voltage side tube core, that is, a chip built-in test circuit, which can realize the built-in self-test of the chip, thereby avoiding the use of expensive signal generators and other equipment, and greatly reducing the test cost. It can also be applied to the on-wafer (on-chip) test in the CP stage, automatically detect, and can also output the test results to the test PAD by reserving a test PAD (pin) on the tube core, so that the voltage of the test PAD can be directly measured to determine whether the chip is defective, thereby simplifying the judgment process of the test results, improving the test efficiency and shortening the test time.

[0095] refer to Figure 2 In an optional implementation, the low voltage side test circuit 200_1 includes:

[0096] A signal generator 201, used to generate the test signal;

[0097] A low-voltage side receiver 205, configured to obtain a return low-frequency signal determined according to the high-voltage side signal, and convert the return low-frequency signal into a return signal corresponding to the test signal; and

[0098] The checker 206 is used to generate and output a first result signal to indicate that the isolated gate driver chip is working normally when the test signal and the return signal satisfy a preset corresponding relationship; and to generate and output a second result signal to indicate that the isolated gate driver chip is working abnormally when the test signal and the return signal do not satisfy the preset corresponding relationship.

[0099] In some examples, the signal generator 201 may include a pseudo-random signal generator, and the generated test signal is mainly used as an input stimulus for the low-voltage side die during the test phase, but is not limited to this. An appropriate signal generator may be selected according to actual needs, such as a function generator, an arbitrary waveform generator, etc.

[0100] The low-voltage side receiver 205 may include a signal amplifier (or an operational amplifier, etc.), but is not limited thereto and may be set according to actual needs. Exemplarily, the amplification factor of the low-voltage side receiver 205 may be set to the inverse of the amplification factor of the low-voltage side transmitter 203, so as to set the test signal and the return signal to meet a preset corresponding relationship. For example, if the amplification factor of the low-voltage side transmitter 203 is K, the amplification factor of the low-voltage side receiver 205 may be 1 / K.

[0101] The checker 206 can use any current circuit that can compare the test signal and the return signal. The structure of the checker itself is not the invention of this application, and the structure of the checker itself is existing technology, so this application will not introduce it in detail.

[0102] In this way, the embodiment of the present application improves the circuit symmetry and the comparability of the test signal and the return signal through the low-voltage side test circuit 200_1 including the signal generator 201, the low-voltage side receiver 205 and the checker 206, thereby improving the reliability and credibility of the test results, so as to better complete the built-in self-test of the chip.

[0103] refer to Figure 2 In an optional implementation, the high-voltage side test circuit 200_2 includes:

[0104] The high-voltage side transmitter 213 is used to obtain the high-voltage side signal and convert the high-voltage side signal into an intermediate signal for returning to the low-voltage side test circuit 200_1, so that the low-voltage side test circuit 200_1 obtains the return signal.

[0105] In some examples, the high-voltage side transmitter 213 may include a signal amplifier (or an operational amplifier, etc.), but is not limited thereto and may be set according to actual needs. Exemplarily, the amplification factor of the high-voltage side transmitter 213 may be set to the inverse of the amplification factor of the high-voltage side receiver 212, so as to set the test signal and the return signal to meet a preset corresponding relationship. For example, if the amplification factor of the high-voltage side receiver 212 is A, the amplification factor of the high-voltage side transmitter 213 may be 1 / A.

[0106] In this way, the embodiment of the present application improves the circuit symmetry and the comparability of the test signal and the return signal through the high-voltage side test circuit 200_2 including the high-voltage side transmitter 213, thereby improving the reliability and credibility of the test results, so as to better complete the built-in self-test of the chip.

[0107] In an exemplary embodiment, the low-voltage side die includes at least one of the following: a signal generator 201; a multiplexer 202; a low-voltage side transmitter 203; a low-voltage side modem 204; a low-voltage side receiver 205; and a checker 206, which can start and stop working and / or switch working states under the control of a low-voltage side controller.

[0108] The high-voltage side die includes at least one of the following: a high-voltage side modem 211; a high-voltage side receiver 212; a high-voltage side transmitter 213; and a high-voltage side driver 214, which can start and stop working and / or switch working states under the control of a high-voltage side controller.

[0109] The low-voltage side controller and the high-voltage side controller can be used to control various timings and functions, etc., to implement various test control logics. Both can be peripheral controller devices or built-in self-test controllers (BIST Control), which can be set according to actual needs. The structures of the low-voltage side controller and the high-voltage side controller themselves are not the invention points of this application, and their structures themselves are all prior art, and this application will not be described in detail.

[0110] refer to Figure 2 In an optional implementation manner, the low voltage side test circuit 200_1 further includes:

[0111] The low-voltage side controller 207 is at least used to control the signal generator 201 to generate the test signal; and control the checker 206 to compare the test signal and the return signal to obtain the test result of the isolated gate driver chip.

[0112] And / or, the high-voltage side test circuit 200_2 further includes:

[0113] The high-voltage side controller 215 is at least used to control the high-voltage side transmitter 213 to obtain the high-voltage side signal and convert the high-voltage side signal into an intermediate signal.

[0114] In some examples, the low-voltage side controller 207 can also be used to implement at least one of the following: control the multiplexer 202 to switch the output; control the start and stop operation of the low-voltage side transmitter 203 to turn on or off the output; control the start and stop operation of the low-voltage side receiver 205 (such as controlling the on and off of the signal amplifier bias voltage to achieve the control of the start and stop operation) to turn on or off the acquisition of the return low-frequency signal and / or the conversion from the return low-frequency signal to the return signal; control the start and stop of the modulation and demodulation work of the low-voltage side modem 204; and so on.

[0115] The high-voltage side controller 215 can also be used to implement at least one of the following: control the start and stop operation of the high-voltage side receiver 212 to turn on or off the output; start and stop the modulation and demodulation operations of the high-voltage side modem 211; start and stop the high-voltage side driver 214 to turn on or off the output drive signal; and so on.

[0116] In this way, the embodiment of the present application can implement built-in self-test through the low-voltage side test circuit 200_1 including the low-voltage side controller 207 and the high-voltage side test circuit 200_2 including the high-voltage side controller 215, thereby improving test efficiency, shortening test time, and reducing test costs.

[0117] refer to Figure 2 In an optional implementation manner, the built-in test circuit 200 further includes:

[0118] The first pin 208 is used to obtain a test start enable signal and provide it to the low-voltage side test circuit 200_1 to control the isolated gate driver chip to enter a test phase;

[0119] The second pin 209 is used to output the test result;

[0120] Wherein, the first pin and the second pin are constructed in the low-voltage side tube core.

[0121] In the embodiment of the present application, the first pin 208 and the second pin 209 can be circuit lead-out PADs on the wafer, providing test PADs for on-wafer testing in the CP phase. In this way, by reserving two test PADs on the low-voltage side die, the test results can be directly read by a multimeter, such as directly reading the voltage on the test PAD (second pin 209) to determine whether the chip is defective, thereby simplifying the test result judgment process, improving test efficiency and shortening test time.

[0122] The embodiment of the present application also provides an isolated gate driver chip, Figure 4 A schematic diagram of a principle block diagram of a specific example of an isolated gate driver chip in an embodiment of the present application is shown. As shown in the figure, the isolated gate driver chip 300 includes a low-voltage side die (LV Die) and a high-voltage side die (HV Die);

[0123] Among them, the isolated gate drive chip 300 also includes a built-in test circuit as described in the above embodiment; the built-in test circuit includes a low-voltage side test circuit (LV BIST) 3031 constructed in the low-voltage side die and a high-voltage side test circuit (HV BIST) 3032 constructed in the high-voltage side die.

[0124] In this way, the embodiment of the present application saves expensive signal generators and oscilloscopes and reduces testing costs by setting a built-in test circuit in the isolated gate driver chip; it can automatically perform detection without manual judgment, thereby improving test efficiency; it can obtain test results by reading the pin status, thereby shortening the test time.

[0125] refer to Figure 4 In an optional implementation manner, the isolated gate driver chip 300 further includes:

[0126] The first pin pad1 is used to obtain a test start enable signal and provide it to the low-voltage side test circuit 3031 to control the isolated gate drive chip 300 to enter a test phase;

[0127] The second pin pad2 is used to output the test result generated after the self-test of the isolated gate driver chip 300 is completed;

[0128] The first pin pad1 and the second pin pad2 are constructed in the low-voltage side die.

[0129] In this way, the embodiment of the present application reserves two test PADs in the low-voltage side die, and the test results can be directly read by a multimeter, such as directly reading the voltage on the test PAD to determine whether the chip is defective, thereby simplifying the test result judgment process, improving test efficiency and shortening test time.

[0130] Figure 5 A schematic diagram of a principle block diagram of another specific example of an isolated gate driver chip in an embodiment of the present application is shown. As shown in the figure, in an optional implementation, the isolated gate driver chip 300 further includes a low-voltage side signal transceiver channel 301 constructed in the low-voltage side die and a high-voltage side signal transceiver channel 302 constructed in the high-voltage side die;

[0131] The low-voltage side signal transceiver channel 301 is at least used to determine a test high-frequency signal according to a test signal provided by the low-voltage side test circuit 3031, and transmit the test high-frequency signal; receive a return high-frequency signal, and determine a return low-frequency signal according to the return high-frequency signal, so that the low-voltage side test circuit determines a return signal according to the return low-frequency signal;

[0132] The high-voltage side signal transceiver channel 302 is at least used to receive the test high-frequency signal, and determine the high-voltage side signal based on the test high-frequency signal, so that the high-voltage side test circuit determines the intermediate signal based on the high-voltage side signal; and determines the return high-frequency signal based on the intermediate signal, and transmits the return high-frequency signal.

[0133] In the embodiment of the present application, the specific structure and effect of the low-voltage side signal transceiver channel 301 and the high-voltage side signal transceiver channel 302 can be referred to above and will not be repeated here.

[0134] Figure 6 A schematic block diagram of another specific example of an isolated gate driver chip in an embodiment of the present application is shown. As a specific example, as shown in the figure, a low voltage side transmitter (LV TX) 603, a low voltage side receiver (LV RX) 605, a high voltage side receiver (HV RX) 612, and a high voltage side transmitter (HV TX) 613 may use a signal amplifier.

[0135] The isolated gate driver chip includes a low voltage side die (LV Die) and a high voltage side die (HV Die). The low voltage side die (LV Die) includes a signal input module (Input PWM) 610, a signal generator (PRBS Pattern) 601, a multiplexer (MUX) 602, a low voltage side transmitter (LVTX) 603, a low voltage side modem (LV OOK Mod&Demod) 604, a low voltage side receiver (LV RX) 605, a checker (Checker) 606, a low voltage side controller (LVBIST Control) 607, a first pin (Test PAD1) 608 and a second pin (Test PAD2) 609. The low voltage side test circuit 600_1 includes a signal input module (Input PWM) 610, a low voltage side receiver (LV RX) 605, a checker (Checker) 606 and a low voltage side controller (LV BIST Control) 607.

[0136] The high-voltage side die (HV Die) includes a high-voltage side modem (HV OOK Mod&Demod) 611, a high-voltage side receiver (HV RX) 612, a high-voltage side transmitter (HV TX) 613, a high-voltage side controller (HV BIST Control) 615, and a high-voltage side driver (HV Driver) 614. The high-voltage side test circuit 600_2 includes a high-voltage side transmitter (HV TX) 613 and a high-voltage side controller (HV BIST Control) 615.

[0137] An on-off keying (OOK) modulation technique may be used between the low voltage side modem (LV OOK Mod&Demod) 604 and the high voltage side modem (HV OOK Mod&Demod) 611 .

[0138] The embodiment of the present application also provides a wafer, Figure 7 A schematic diagram of a principle block diagram of a specific example of a wafer in an embodiment of the present application is shown. As shown in the figure, the wafer 700 includes one or more crystal grains 701;

[0139] The die 701 is used to form the isolated gate driving chip as described in the above embodiment, that is, the die 701 includes an isolated gate driving circuit structure.

[0140] Thus, the embodiment of the present application sets a built-in test circuit in each die of the wafer that realizes the function of the isolated gate driver chip, and can realize automatic testing in the On Wafer CP test, thereby reducing the test cost and improving the test efficiency. Moreover, the test results can be directly obtained by testing the PAD, thus shortening the test time.

[0141] The present application also provides a testing platform. Figure 8 A schematic diagram of a principle block diagram of a specific example of a test platform in an embodiment of the present application is shown. As shown in the figure, the test platform 800 includes a power supply, a multimeter, and an isolated gate drive chip as described in the above embodiment;

[0142] The power supply is used to supply power to the isolated gate drive chip;

[0143] The multimeter is used to read the test result output by the isolated gate drive chip.

[0144] In this way, the embodiment of the present application connects the second pin pad2 through a multimeter to read the test results output by the chip, such as reading the pin level. A high level means that the test result has no defects, and a low level means that the test result has defects, thereby reducing the test cost, improving the test efficiency and shortening the test time.

[0145] In some examples, the test platform 800 can input a test start enable signal through the first pin pad1 to start the test process and enter the test phase, but is not limited to this and can be set according to actual needs. For example, the test platform 800 can also use the low-voltage side controller of the low-voltage side test circuit to execute the test control logic to perform automatic testing at a fixed time.

[0146] The present application also provides a testing platform. Fig. 9 A schematic diagram of a principle block diagram of another specific example of a test platform in an embodiment of the present application is shown. As shown in the figure, the test platform 900 includes a test probe Probe and a wafer 901 as described in the above embodiment;

[0147] The test probe Probe includes a first short-circuit probe group, a second short-circuit probe group, a first signal probe, a second signal probe, a first power probe and a second power probe;

[0148] The first short-circuit probe group includes a pair of short-circuit probes for connecting a channel between a low-voltage side modem and a high-voltage side modem in any one of the dies forming the isolated gate drive chip on the wafer; the second short-circuit probe group includes a pair of short-circuit probes for connecting another channel between the low-voltage side modem and the high-voltage side modem;

[0149] The first signal probe is used to provide a test start enable signal to the first pin pad1 of the die;

[0150] The second signal probe is used to obtain a test result output by the second pin pad2 of the die;

[0151] The first power probe is used to supply power to the low voltage side die of the die;

[0152] The second power probe is used to supply power to the high-voltage side die of the die.

[0153] Thus, the embodiment of the present application realizes the communication between the low-voltage side die and the high-voltage side die by replacing the bonding wire with two pairs of short-circuited test probes. And through the two test pads reserved on the low-voltage side die, it is possible to use the test probes to directly read the voltage on the test pads to determine whether the chip is defective. Therefore, the on-wafer test at the CP stage is realized by the test platform with the test probes.

[0154] The embodiment of the present application also provides a testing method, which can be applied to the above-mentioned built-in testing circuit to perform defect testing on the isolated gate driver chip. Fig.10A schematic diagram of a principle block diagram of a specific example of a test method in an embodiment of the present application is shown. As shown in the figure, the test method includes:

[0155] S101: The low voltage side test circuit generates and outputs a test signal;

[0156] S102: The low-voltage side signal transceiver channel generates a low-voltage side signal according to the test signal and transmits it for output;

[0157] S103: The high-voltage side signal transceiver channel generates and outputs a high-voltage side signal according to the low-voltage side signal;

[0158] S104: The high-voltage side test circuit converts the high-voltage side signal and transmits it to the high-voltage side signal transceiver channel for output;

[0159] S105: The low-voltage side test circuit obtains the signal transmitted by the high-voltage side signal transceiver channel through the low-voltage side signal transceiver channel and determines a return signal based on the signal; and based on the test signal and the return signal, checks and determines the test result of the isolated gate drive chip.

[0160] Thus, the test method implemented by the built-in test circuit in the embodiment of the present application can check whether the low-voltage side die and the high-voltage side die are working properly and whether there are defects based on the test signal and the return signal. It can also avoid the use of expensive equipment such as signal generators, which can greatly reduce the test cost. It can also be applied to on-wafer testing at the CP stage, automatically detect, simplify the judgment process of the test results, improve test efficiency and shorten test time.

[0161] In the embodiment of the present application, the test method can be implemented by controlling various timings and functions through the test control logic of the low-voltage side controller and the high-voltage side controller. The high-voltage side signal can be used to control the operation of the high-voltage side driver to drive the power device.

[0162] refer to Figure 3 As a specific example, the test method may include:

[0163] S201: the signal generator 201 generates a test signal S1;

[0164] S202: The multiplexer 202 selects and outputs the test signal S1;

[0165] S203: the low voltage side transmitter 203 converts the test signal S1 to obtain a test low frequency signal S2;

[0166] S204: the low-voltage side modem 204 modulates the test low-frequency signal S2 into a test high-frequency signal S3 and transmits it for output;

[0167] S205: The high-voltage side modem 211 receives the test high-frequency signal S3 and demodulates it into a test low-frequency signal S4;

[0168] S206: The high-voltage side receiver 212 converts the test low-frequency signal S4 into a high-voltage side signal S5;

[0169] S207: the high-voltage side transmitter 213 converts the high-voltage side signal S5 to obtain an intermediate signal S6;

[0170] S208: The high-voltage side modem 211 modulates the intermediate signal S6 into a return high-frequency signal S7 and transmits it for output;

[0171] S209: The low-voltage side modem 204 receives the returned high-frequency signal S7 and demodulates it into a returned low-frequency signal S8;

[0172] S210: The low-voltage side receiver 205 converts the returned low-frequency signal S8 to obtain a returned signal S9;

[0173] S211: The checker 206 checks the test signal S1 and the return signal S9, and generates and outputs a first result signal when the test signal S1 and the return signal S9 satisfy a preset corresponding relationship, and generates and outputs a second result signal when the test signal S1 and the return signal S9 do not satisfy the preset corresponding relationship.

[0174] In some examples, the testing method may further include, before step S201:

[0175] S212 : The first pin 208 obtains the test start enable signal and provides it to the low-voltage side controller 207 to control the signal generator 201 to generate the test signal S1 .

[0176] The testing method may further include, after step S211:

[0177] S213: The low-voltage side controller 207 generates a first level according to the first result signal or generates a second level according to the second result signal, and outputs the first level or the second level to the second pin 209 for measurement; for example, if the test signal S1 and the return signal S9 are the same, a high level is output on the second pin 209, and it is considered that the low-voltage side die and the high-voltage side die are working normally and have no defects; conversely, if the test signal S1 and the return signal S9 are not the same, a low level is output on the second pin 209, and it is considered that the operation is abnormal.

[0178] In the embodiment of the present application, the isolated gate driver chip may include a test phase and a normal working state. If the chip enters the test phase, the above test method can be implemented. If the chip enters the normal working phase, the signal input module can be used to obtain the signal to be transmitted, and through the transmission of the low-voltage side die and the high-voltage side die, the drive signal is finally output through the high-voltage side driver to drive the power device.

[0179] It should be understood that the above embodiments are exemplary and are not intended to include all possible implementations. Various modifications and changes may also be made on the basis of the above embodiments without departing from the scope of the present disclosure. Similarly, the various technical features of the above embodiments may also be combined arbitrarily to form other embodiments of the present application that may not be clearly described. Therefore, the above embodiments only express several implementations of the present application and do not limit the scope of protection of the patent of this application.

Claims

1. A built-in test circuit, applied to an isolated gate driver chip, characterized in that: The built-in test circuit comprises: A low-voltage side test circuit is constructed in the low-voltage side die of the isolated gate driver chip, and is used to generate a test signal and provide it to the low-voltage side signal transceiver channel in the low-voltage side die, so that the low-voltage side signal is determined according to the test signal through the low-voltage side signal transceiver channel and transmitted to the high-voltage side die of the isolated gate driver chip, so that the high-voltage side signal transceiver channel in the high-voltage side die determines the high-voltage side signal according to the low-voltage side signal and returns it to the low-voltage side die; and determines the return signal according to the high-voltage side signal; and based on the test signal and the return signal, checks and determines the test result of the isolated gate driver chip; and The high-voltage side test circuit is constructed in the high-voltage side die of the isolated gate driver chip, and is used to convert the high-voltage side signal and transmit and output it to the high-voltage side signal transceiver channel to return it to the low-voltage side die.

2. The built-in test circuit according to claim 1, characterized in that: The low voltage side test circuit comprises: A signal generator, used for generating the test signal; a low-voltage side receiver, configured to obtain a return low-frequency signal determined according to the high-voltage side signal, and convert the return low-frequency signal into a return signal corresponding to the test signal; and A checker, configured to generate and output a first result signal to indicate that the isolated gate driver chip works normally when the test signal and the return signal satisfy a preset corresponding relationship; and to generate and output a second result signal to indicate that the isolated gate driver chip works abnormally when the test signal and the return signal do not satisfy the preset corresponding relationship; And / or, the high-voltage side test circuit comprises: The high-voltage side transmitter is used to obtain the high-voltage side signal and convert the high-voltage side signal into an intermediate signal for returning to the low-voltage side test circuit so that the low-voltage side test circuit obtains the return signal.

3. The built-in test circuit according to claim 2, characterized in that: The low voltage side test circuit also includes: A low-voltage side controller, at least used to control the signal generator to generate the test signal; and control the checker to compare the test signal and the return signal to obtain a test result of the isolated gate driver chip; And / or, the high-voltage side test circuit further includes: The high-voltage side controller is at least used to control the high-voltage side transmitter to obtain the high-voltage side signal and convert the high-voltage side signal into an intermediate signal.

4. The built-in test circuit according to any one of claims 1 to 3, characterized in that: The built-in test circuit also includes: A first pin is used to obtain a test start enable signal and provide it to the low-voltage side test circuit to control the isolated gate drive chip to enter a test phase; A second pin, used for outputting the test result; Wherein, the first pin and the second pin are constructed in the low-voltage side tube core.

5. An isolated gate driver chip, characterized in that: The isolated gate drive chip includes a low-voltage side die and a high-voltage side die; Among them, the isolated gate drive chip also includes a built-in test circuit as described in any one of claims 1-4; the built-in test circuit includes a low-voltage side test circuit constructed in the low-voltage side die and a high-voltage side test circuit constructed in the high-voltage side die.

6. The isolated gate driver chip according to claim 5, characterized in that: The isolated gate driver chip further includes a low-voltage side signal transceiver channel constructed in the low-voltage side tube core and a high-voltage side signal transceiver channel constructed in the high-voltage side tube core; The low-voltage side signal transceiver channel is at least used to determine a test high-frequency signal according to a test signal provided by the low-voltage side test circuit, and transmit the test high-frequency signal; Receiving a returned high-frequency signal, and determining a returned low-frequency signal according to the returned high-frequency signal, so that the low-voltage side test circuit determines a returned signal according to the returned low-frequency signal; The high-voltage side signal transceiver channel is at least used to receive the test high-frequency signal, and determine the high-voltage side signal based on the test high-frequency signal, so that the high-voltage side test circuit determines the intermediate signal based on the high-voltage side signal; and determines the return high-frequency signal based on the intermediate signal, and transmits the return high-frequency signal.

7. A wafer, characterized in that: The wafer includes one or more dies; Wherein, the crystal grains are used to form the isolated gate driving chip as described in claim 5 or 6.

8. A test platform, characterized in that: The test platform comprises a power supply, a multimeter, and the isolated gate drive chip according to claim 5 or 6; The power supply is used to supply power to the isolated gate drive chip; The multimeter is used to read the test result output by the isolated gate drive chip.

9. A test platform, characterized in that: The test platform comprises a test probe and the wafer as claimed in claim 7; The test probes include a first short-circuit probe group, a second short-circuit probe group, a first signal probe, a second signal probe, a first power supply probe, and a second power supply probe; The first short-circuit probe group includes a pair of short-circuit probes for connecting a channel between a low-voltage side modem and a high-voltage side modem in any one of the dies forming the isolated gate drive chip on the wafer; the second short-circuit probe group includes a pair of short-circuit probes for connecting another channel between the low-voltage side modem and the high-voltage side modem; The first signal probe is used to provide a test start enable signal to a first pin of the die; The second signal probe is used to obtain a test result output by a second pin of the die; The first power probe is used to supply power to the low voltage side die of the die; The second power probe is used to supply power to the high-voltage side die of the die.

10. A testing method, characterized in that: The test method includes: The low voltage side test circuit generates and outputs a test signal; The low-voltage side signal transceiver channel generates a low-voltage side signal according to the test signal and transmits it for output; The high-voltage side signal transceiver channel generates and outputs a high-voltage side signal according to the low-voltage side signal; The high-voltage side test circuit converts the high-voltage side signal and transmits it to the high-voltage side signal transceiver channel for output; The low-voltage side test circuit obtains the signal transmitted by the high-voltage side signal transceiver channel through the low-voltage side signal transceiver channel and determines a return signal based on the signal; and based on the test signal and the return signal, checks and determines the test result of the isolated gate drive chip.

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