Test system and method based on relay channel switching
By designing a test system based on relay channel switching, the problem of poor flexibility of traditional FPGA board resource switching systems is solved, and flexible switching of relay channels and efficient system production is realized, which is convenient for improved design and maintenance.
Patent Information
- Application Number
- CN202411991466.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-31
- Publication Date
- 2025-04-01
AI Technical Summary
Traditional FPGA board resource switching systems have problems such as poor flexibility, high design complexity and limited scalability, which leads to the need to redesign the routing network when changing resource allocation or increasing board resources, which increases cost and time overhead.
A test system based on relay channel switching is designed. The upper computer sends control signals, and the communication board receives and forwards signals to the test machine interface board. The signal processing module analyzes the control signals and controls the conduction of the relay channel, so that the digital signal board and the communication board are connected.
It realizes flexible switching of relay channels, improves the production efficiency of the test system, facilitates improved design and maintenance, and reduces system complexity and cost.
Smart Images
Figure CN119738694A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor device testing, and in particular to a testing system and method based on relay channel switching. Background Art
[0002] In the traditional FPGA board resource switching system, relay matrix circuits are widely used to achieve flexible resource allocation. The system usually includes multiple relay groups, such as X1, X2, X3 and X4, where one end of the X1, X2 and X3 relay groups are connected in parallel to the PCIE board, and the X4 relay group is connected to the chip under test through X3.
[0003] However, this system has some obvious disadvantages. First, the input and output of the FPGA board are strictly dependent on the preset board resources, which means that each relay is bound to a specific FPGA board and lacks flexibility. When the resource allocation needs to be changed, the routing network of the FPGA board may need to be redesigned, which not only increases the design complexity, but also may lead to additional cost and time overhead.
[0004] Secondly, due to the binding relationship between relays and resources, the scalability of the system is also limited. If new board resources or relays need to be added, the architecture and design of the entire system may need to be reconsidered, which further increases the complexity and cost of the system. Summary of the invention
[0005] The purpose of the present application is to provide a test system and method based on relay channel switching, which facilitates the switching of relay channels, is beneficial to improving the production efficiency of the test system, facilitates the improved design of the test system, and also facilitates the maintenance of the test system.
[0006] In order to achieve the above-mentioned purpose, an embodiment of the present application provides a test system based on relay channel switching for testing a chip, and the test system includes: Host computer, used to send control signals; A communication board connected to the host computer and used to receive the control signal and send it to the test machine interface board; A tester interface board, the tester interface board includes a signal processing module and a plurality of digital signal boards, each of the digital signal boards includes a relay channel, the relay channel includes a plurality of relays connected in series, and the relay channels are connected in parallel; The test machine interface board analyzes the control signal through the signal processing module, and controls at least one of the relay channels to be turned on based on the analysis result, so that the corresponding digital signal board is connected to the communication board.
[0007] Optionally, the test machine interface board also includes a universal module, one end of which is connected to the chip to be tested, and the universal module includes a number of relays connected in series. The test machine interface board controls the conduction of the relay channels therein based on the analysis results, so that the corresponding digital signal board connects the communication board and the universal module.
[0008] Optionally, the host computer determines the control signal to be sent based on model parameters of the chip to be tested.
[0009] Optionally, the control signal includes a board number mask, and the test machine interface board parses the board number mask through the signal processing module to obtain the board number of the digital signal board to be connected, and controls the relay channel on the digital signal board corresponding to the board number to be turned on.
[0010] Optionally, the control signal includes a board number mask, and the signal processing module includes a DAC module, and the DAC module is used to convert a digital signal in the control signal into an analog signal.
[0011] Optionally, the test machine interface board is a FPGA board.
[0012] Optionally, the communication board is a PCIE board.
[0013] In order to achieve the above object, the present application also provides a relay channel switching method, comprising: Send control signals through the host computer; The communication board receives the control signal and sends the control signal to the test machine interface board; The signal processing module of the test machine interface board analyzes the control signal; The tester interface board controls the relay channel on at least one digital signal board thereon to be turned on based on the analysis result of the signal processing module, so that the digital signal board is connected to the communication board; The tester interface board is used to connect with the chip to be tested, and includes a plurality of digital signal boards, each of which includes a relay channel, and the relay channel includes a plurality of relays connected in series.
[0014] Optionally, the control signal includes a board number mask, and the signal processing module of the tester interface board parses the control signal to include: The signal processing module parses the board number mask to obtain the board number of the digital signal board to be connected; The test machine interface board controls the conduction of a relay channel on a digital signal board thereon based on the analysis result of the signal processing module, including: The tester interface board controls the relay channel on the digital signal board corresponding to the board number to be turned on.
[0015] Optionally, the tester interface board further includes a universal module, one end of which is connected to the chip to be tested, and the universal module includes a plurality of relays connected in series, and the method further includes: The tester interface board controls one of the relay channels to be turned on based on the analysis result, so that the corresponding digital signal board is connected to the communication board and the universal module.
[0016] In an embodiment of the present application, the test system includes a host computer, a communication board and a test machine interface board, the communication board receives the control signal sent by the host computer and sends it to the test machine interface board, the test machine interface board includes a signal processing module and a plurality of digital signal boards, each digital signal board includes a relay channel, each relay channel is composed of a plurality of relays connected in series, and each relay channel is connected in parallel, the signal processing module parses the control signal and controls at least one of the relay channels to be turned on based on the parsing result, so that the corresponding digital signal board is connected to the communication board. The embodiment of the present application can flexibly switch channels, which is convenient for improving the design of the test system. In addition, by grouping the relays, when the test system fails, there is no need to test each relay separately, only each relay channel needs to be tested, which is convenient for maintaining the test system. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Figure 1 It is a structural block diagram of the test system in the embodiment of the present application.
[0018] Figure 2 This is a schematic diagram of the relay circuit of the test machine interface board in the embodiment of the present application.
[0019] Figure 3 This is a circuit schematic diagram when the relay channels of the test machine interface board in the embodiment of the present application are fully closed.
[0020] Figure 4 Flow chart of the relay channel switching method in an embodiment of the present application. DETAILED DESCRIPTION
[0021] In order to explain the technical content, structural features and achieved effects of the present application in detail, the following is a detailed description in combination with the implementation methods and the accompanying drawings.
[0022] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present application, so the present application is not limited by the specific embodiments disclosed below.
[0023] See also Figure 1 and Figure 2 The embodiment of the present application discloses a test system based on relay channel switching, including a host computer 10, a communication board 20 and a test machine interface board 30. The host computer 10 is used to send a control signal, and the communication board 20 is connected to the host computer 10 to receive the control signal and send it to the test machine interface board 30.
[0024] The tester interface board 30 includes a signal processing module 40 and a plurality of digital signal boards 50. Each digital signal board 50 includes a relay channel. The relay channel includes a plurality of relays connected in series. Each relay channel is connected in parallel. The tester interface board 30 analyzes the control signal through the signal processing module 40, and controls at least one relay channel to be turned on based on the analysis result, so that the corresponding digital signal board 50 is connected to the communication board 20.
[0025] It can be understood that the connection between the digital signal board 50 and the communication board 20 here means that a communication connection is established between the digital signal board 50 and the communication board 20, and the signal can flow through the relay channel thereon.
[0026] In the embodiment of the present application, the test system includes a host computer 10, a communication board 20 and a test machine interface board 30. The communication board 20 receives the control signal sent by the host computer 10 and sends it to the test machine interface board 30. The test machine interface board 30 includes a signal processing module 40 and a plurality of digital signal boards 50. Each digital signal board 50 includes a relay channel, each relay channel is composed of a plurality of relays connected in series, and each relay channel is directly connected in parallel. The signal processing module 40 analyzes the control signal and controls at least one of the relay channels to be turned on based on the analysis result, so that the corresponding digital signal board 50 is connected to the communication board 20. In the test system of the embodiment of the present application, since the test machine interface board 30 controls the connection with the relay channels on each digital signal board 50 based on the control signal, each relay channel is relatively independent and does not need to be bound and connected with the relay. Therefore, the test system of the embodiment of the present invention can flexibly switch channels, and it is also convenient to improve the design of the test system. In addition, by grouping the relays, when the test system fails, it is not necessary to test each relay separately, but only to test each relay channel, which is convenient for maintenance of the test system.
[0027] In the embodiment of the present application, the tester interface board 30 includes three digital signal boards 50, i.e., three relay channels, and the board IDs of the three digital signal boards 50 are VID1, VID2, and VID3. Of course, in other embodiments, the number of digital signal boards 50 may also be 4 or more, and the present application does not limit this. In addition, in practical applications, the board resources of the tester interface board 30 may also be expanded as needed to increase the number of digital signal boards 50.
[0028] It is understandable that the board ID is only for the convenience of distinguishing the digital signal board 50 and should not be regarded as a limitation to the present application.
[0029] Furthermore, each relay channel includes 3 relays, wherein the VID1 board corresponds to relay channel channel1, and relay channel channel1 includes relays K11, K12, and K13; the VID2 board includes a corresponding relay channel channel2, and relay channel channel2 includes relays K21, K22, and K23; the VID3 board corresponds to relay channel channel3, and relay channel channel3 includes relays K31, K32, and K33. Of course, the present application does not limit the number of relays in each relay channel, and the number of relays in each relay channel may be the same or different.
[0030] In some embodiments, the test machine interface board 30 also includes a universal module 60, one end of which is connected to the chip to be tested 70, and the universal module 60 includes a plurality of relays connected in series. The test machine interface board 30 controls the conduction of the relay channels therein based on the analysis results, so that the corresponding digital signal board 50 is connected to the communication board 20 and the universal module 60.
[0031] In the specific example, the number of relays in the universal module 60 is 3, including relays KV1, KV2 and KV3. Of course, the present application does not limit the number of relays in the universal module 60.
[0032] Specifically, the host computer 10 determines the control signal to be sent based on the model parameters of the chip 70 to be tested.
[0033] See also Figure 3In some embodiments, the control signal includes a board number mask VID_Mask, and the tester interface board 30 parses the board number mask VID_Mask through the signal processing module 40 to obtain the board number of the digital signal board 50 to be connected, and controls the relay channel on the digital signal board 50 corresponding to the board number to be turned on. For example, when VID_Mask=0000_0111 (0x07), it means that VID boards 1, 2, and 3 are executed, that is, digital signal boards VID1, VID2, and VID3 are executed at the same time, and relay channels channel1, channel2, and channel3 are all controlled to be turned on by the tester interface board 30.
[0034] In a specific example, the control signal may also include digital signals such as voltage range value, current range value, sampling lag time, sampling times, level mode, etc. These control signals are all related to the model parameters of the chip under test 70, and different models of chips under test 70 require different relay channels.
[0035] In some implementations, the signal processing module 40 includes a DAC module for converting a digital signal in the control signal into an analog signal.
[0036] Specifically, the tester interface board 30 is a FPGA board card. The FPGA outputs an enable signal to close or open the relay contact, thereby turning on or off the relay channel.
[0037] Specifically, the communication board 20 is a PCIE board. In the test machine, the PCIE board can be used to achieve high-speed data transmission and interface expansion. The test machine requires a PCIE interface to perform high-speed data transmission with the host computer 10, and this function is achieved by using a PCIE board. In addition, the PCIE board can also be used to expand the functions of the test machine, such as adding a network interface, a storage interface, etc.
[0038] See also Figure 4 , the embodiment of the present application also discloses a relay channel switching method, including: S1, sending a control signal through the host computer 10.
[0039] S2, receiving the control signal from the host computer 10 through the communication board 20, and sending the control signal to the test machine interface board 30.
[0040] S3, the signal processing module 40 of the tester interface board 30 analyzes the control signal.
[0041] S31 , the signal processing module 40 parses the board number mask to obtain the board number of the digital signal board 50 to be connected.
[0042] S4 , the tester interface board 30 controls a relay channel on a digital signal board 50 thereon to be turned on based on the analysis result of the signal processing module 40 , so that the digital signal board 50 is connected to the communication board 20 .
[0043] The tester interface board 30 is used to connect with the chip under test 70. The tester interface board 30 includes a plurality of digital signal boards 50. Each digital signal board 50 includes a relay channel. The relay channel includes a plurality of relays connected in series.
[0044] S41, the tester interface board 30 controls the relay channel on the digital signal board 50 corresponding to the board number to be turned on.
[0045] In some embodiments, the tester interface board 30 further includes a universal module 60, the universal module 60 is connected to the chip to be tested 70, and the universal module 60 includes a plurality of relays connected in series. The method further includes: The tester interface board 30 controls one of the relay channels to be turned on based on the analysis result, so that the corresponding digital signal board 50 is connected to the communication board 20 and the universal module 60 .
[0046] The above disclosure is only a preferred example of the present application, and its role is to facilitate the technical personnel in this field to understand and implement it. Of course, it cannot be used to limit the scope of rights of the present application. Therefore, equivalent changes made according to the scope of the patent application of the present application still fall within the scope covered by the present application.
Claims
1. A test system based on relay channel switching, used for chip testing, characterized in that: include: Host computer, used to send control signals; A communication board connected to the host computer and used to receive the control signal and send it to the test machine interface board; The tester interface board is used to connect to the chip to be tested, and the tester interface board includes a signal processing module and a plurality of digital signal boards, each of the digital signal boards includes a relay channel, and the relay channel includes a plurality of relays connected in series, and each of the relay channels is connected in parallel; The test machine interface board analyzes the control signal through the signal processing module, and controls at least one of the relay channels to be turned on based on the analysis result, so that the corresponding digital signal board is connected to the communication board.
2. The test system according to claim 1, characterized in that: The test machine interface board also includes a universal module, one end of which is connected to the chip to be tested, and the universal module includes a plurality of relays connected in series. The test machine interface board controls the conduction of the corresponding relay channel based on the analysis result, so that the corresponding digital signal board connects the communication board and the universal module.
3. The test system according to claim 2, characterized in that: The host computer determines the control signal to be sent based on the model parameters of the chip to be tested.
4. The test system according to claim 1, characterized in that: The control signal includes a board number mask. The tester interface board parses the board number mask through the signal processing module to obtain the board number of the digital signal board to be connected, and controls the relay channel on the digital signal board corresponding to the board number to be turned on.
5. The test system according to claim 1, characterized in that: The signal processing module includes a DAC module, and the DAC module is used to convert a digital signal in the control signal into an analog signal.
6. The test system according to claim 1, characterized in that: The test machine interface board is a FPGA board.
7. The test system according to claim 1, characterized in that: The communication board is a PCIE board.
8. A relay channel switching method, characterized in that: include: Send control signals through the host computer; The communication board receives the control signal and sends the control signal to the test machine interface board; The signal processing module of the test machine interface board analyzes the control signal; The tester interface board controls the relay channel on at least one digital signal board to be turned on based on the analysis result of the signal processing module to establish a connection with the communication board; The tester interface board is used to connect with the chip to be tested, and includes a plurality of digital signal boards, each of which includes a relay channel, and the relay channel includes a plurality of relays connected in series.
9. The relay channel switching method according to claim 8, characterized in that: The control signal includes a board number mask, and the signal processing module of the tester interface board analyzes the control signal to include: The signal processing module parses the board number mask to obtain the board number of the digital signal board to be connected; The test machine interface board controls the conduction of a relay channel on at least one digital signal board based on the analysis result of the signal processing module, including: The tester interface board controls the relay channel on the digital signal board corresponding to the board number to be turned on.
10. The relay channel switching method according to claim 8, characterized in that: The tester interface board further comprises a universal module, one end of which is connected to the chip to be tested, and the universal module comprises a plurality of relays connected in series. The method further comprises: The tester interface board controls one of the relay channels to be turned on based on the analysis result, so that the corresponding digital signal board is connected to the communication board and the universal module.