An extreme precision stable test structure

Abstract

The present invention discloses an extreme precision stable test structure, including a tester, the tester including a first voltage and current source and a test matrix selector, the first voltage and current source can be connected to the forced end and the sensing end of the chip under test through the test matrix selector, the extreme precision stable test structure also includes a test resistor, the test resistor is connected to the test matrix selector, and can be connected to the forced end and the sensing end of the first voltage and current source through the test matrix selector, the test resistor is used to pre-test the tester; wherein, after the first voltage and current source applies current to the test resistor through the test matrix selector, if the voltage on the test resistor exceeds a preset voltage range, the test is stopped. The present invention avoids the need for complex pre-testing before normal testing of old equipment, and solves the problem in the prior art that the tester cannot monitor whether an abnormality occurs during the test process.

Description

Technical Field

[0001] The present invention relates to the technical field of chip testing, and in particular to an extreme precision stable testing structure. Background Art

[0002] When the tester tests the chip, the extreme accuracy test means that some of the test items are close to the accuracy of the tester itself. At present, in order to ensure the stability of the tester under high-precision testing, the frequency of regular detection of diagnostic programs is usually increased in the tester to repeatedly confirm all interfaces and connections before testing, and pre-test with standard wafers or during the test, and then conduct production testing when the pre-test data is good and stable.

[0003] In the prior art, during the test process, if the tester itself and the test board are subject to certain external interference, the data may drift, especially when the tester and the test board are old. If the test board is subjected to small external vibrations and touches, poor contact will usually cause inaccurate test data. In severe cases, the data may even exceed the standard, causing the tester to display FAIL. In addition, because the pre-test process of the tester is complicated, it cannot be used in time during the chip test process, and it is impossible to monitor whether the tester is abnormal during the test process, which undoubtedly reduces the test efficiency and accuracy of the chip.

[0004] Based on this, a new technical solution is needed. Summary of the invention

[0005] In view of this, an embodiment of the present invention provides an extreme precision stable test structure to at least solve the problem in the prior art that the tester cannot monitor whether an abnormality occurs during the test process.

[0006] The embodiment of the present invention provides the following technical solutions:

[0007] An embodiment of the present invention provides an extreme precision stable test structure, including a tester, the tester including a first voltage and current source and a test matrix selector, the first voltage and current source can be connected to a forced end and a sensing end of a chip under test through the test matrix selector, and the extreme precision stable test structure further includes:

[0008] A test resistor, the test resistor is connected to the test matrix selector and can be connected to the forcing end and the sensing end of the first voltage and current source through the test matrix selector, the test resistor is used to pre-test the tester;

[0009] Among them, after the first voltage and current source applies current to the test resistor through the test matrix selector, if the voltage on the test resistor is within a preset voltage range, the first current source is connected to the chip under test through the test matrix selector; if the voltage on the test resistor exceeds the preset voltage range, the test is stopped.

[0010] Furthermore, the output end of the test resistor is grounded.

[0011] Furthermore, the test resistor is 100Ω, the current applied by the voltage-current source is 12.5MA, and the preset voltage range is 1.25V±3MV.

[0012] Furthermore, the extreme precision stability test structure also includes:

[0013] A single-pole multi-throw switch, wherein an input terminal of the single-pole multi-throw switch is connected to a frequency reference terminal of the tester;

[0014] A detection point, the detection point is connected to an output end of the single-pole multi-throw switch and is used to connect to the chip under test;

[0015] An active crystal oscillator connected to another output terminal of the single-pole multi-throw switch;

[0016] Among them, when the single-pole multi-throw switch is switched to connect with the active crystal oscillator, the active crystal oscillator monitors the measurement waveform time of the chip under test through the detection point, and when the measurement waveform time is within a preset time range, the single-pole multi-throw switch is switched to connect with the detection point to test the chip under test; if the measurement waveform time exceeds the preset time range, the test is stopped.

[0017] Furthermore, the tester further comprises:

[0018] A counter is integrated in the tester, and the tester is used to control the switching frequency of the single-pole multi-throw switch through the counter to control the test frequency of the active crystal oscillator on the chip under test.

[0019] Furthermore, a capacitor is connected to a VCC terminal of the active crystal oscillator, and the other end of the capacitor is connected to a second voltage and current source.

[0020] Furthermore, the single-pole multi-throw switch is a single-pole double-throw controllable relay and is electrically connected to the tester so that the tester controls the single-pole multi-throw switch to switch automatically.

[0021] Furthermore, the active crystal oscillator is a 32.768K high-precision active crystal oscillator, and the preset time range is 30.5US±5US.

[0022] Compared with the prior art, the at least one technical solution adopted in the embodiment of the present invention can achieve the following beneficial effects:

[0023] An extreme precision stable test structure of the present invention connects a test matrix selector to a first voltage and current source on a tester for monitoring key parameters of a chip under test, and uses the test matrix selector to flexibly switch test resistors and the chip under test, thereby being able to judge whether an abnormality occurs in the tester during the test process based on whether the voltage on the test resistor is within a preset voltage range. This solves the problem in the prior art that the tester cannot monitor whether an abnormality occurs during the test process, avoids the need for complex pre-testing of old equipment before normal testing, and improves the test efficiency of chip testing using old equipment. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0025] Figure 1 is the normal distribution of a normal wafer under test;

[0026] Figure 2 is the normal distribution of a wafer with problems under test;

[0027] Figure 3 This is the normal distribution of another wafer with problems under test;

[0028] Figure 4 A schematic diagram of an extreme precision stable test structure using a test resistor to monitor a tester according to an embodiment of the present invention;

[0029] Figure 5 This is a schematic diagram of a chip test principle of an extreme precision stable test structure according to an embodiment of the present invention (I);

[0030] Figure 6 A frequency monitoring test principle diagram of an extreme precision stable test structure according to an embodiment of the present invention;

[0031] Figure 7 This is a schematic diagram (II) of a chip test principle of an extreme precision stable test structure according to an embodiment of the present invention.

[0032] The accompanying drawings of the present invention are as follows:

[0033] 10. Tester; 20. First voltage and current source; 30. Test matrix selector; 40. Test resistor; 50. Single-pole multi-throw switch; 60. Probe point; 70. Active crystal oscillator; 80. Capacitor. DETAILED DESCRIPTION

[0034] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0035] The following describes the implementation methods of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the absence of conflict, the following embodiments and the features in the embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work belong to the scope of protection of the present application.

[0036] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present application, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspect described herein can be used to implement the device and / or practice the method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this device and / or practice this method.

[0037] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application. The drawings only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0038] Additionally, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the examples can be practiced without these specific details.

[0039] During the test of the tester 10, after the tester 10 itself and the test board are disturbed by the outside world, the data may drift, especially when the tester 10 is an old device. For example, when the test board of the tester 10 is subjected to slight vibration and touch from the outside, poor contact may occur on the test board, thereby causing inaccurate and offset test data. If the data drift is serious, it will directly cause the data to exceed the standard, and the tester 10 will display FAIL. If the tester 10 continuously displays FAIL, the tester 10 will alarm, so that the staff can find the error. However, if the drift is not large and the data can also fall within the range, this situation has little effect on the general chip being tested. As long as the test data is within the required range, it can be identified as a good device. Even if problems are found later, retesting can be performed. However, for sintered products, this slight data drift may cause different sintering gears, thereby causing part or all of the center value of the device being tested to shift. Although the output value of the device falls within the required range and does not affect the use, the accuracy and consistency of the device are poor, making it difficult to meet customer needs.

[0040] like Figures 1 to 3 As shown, Figure 1 is the normal distribution of the normal wafer under test, Figure 2 and 3 All of them are normal distributions of the wafers with problems. Figure 2 and Figure 3 It was observed that, compared with normal Figure 1 There is a drift to the right or left compared to the center value, so from a testing perspective the test accuracy must be guaranteed to avoid losses.

[0041] In addition, in order to pursue extremely small errors, some customers divide the sintered aluminum wire into coarse adjustment and fine adjustment. The fine adjustment is mainly to compensate for the process errors to achieve the requirements of extremely high numerical accuracy. At the same time, because the sintering logic is an algorithm, it also has some errors to a greater or lesser extent. Therefore, when using the tester 10 to test the chip under test, it is necessary to ensure that the tester 10 is extremely stable to meet the needs of this product. However, because the test board will cause inaccurate data when it is slightly vibrated and touched, it is undoubtedly difficult to meet the needs of the above products.

[0042] Based on this, the embodiment of this specification proposes a processing solution: an extreme precision stable test structure of the present invention, by connecting the test resistor 40 to the test matrix selector 30, so as to determine whether the voltage on the test resistor 40 is within a preset range when the current is applied to the test resistor 40, thereby determining whether the key parameters on the first voltage and current source 20 are correct, and finally determining whether the tester 10 can be detected normally based on whether the key parameters are correct, thereby simplifying the pre-inspection of the tester 10 and facilitating monitoring whether the tester 10 has any abnormalities during the test process.

[0043] The technical solutions provided by various embodiments of the present application are described below in conjunction with the accompanying drawings.

[0044] like Figures 4 to 7 As shown, an extreme precision stable testing structure according to an embodiment of the present invention includes a tester 10.

[0045] Among them, the tester 10 described in the present application is an old LTX tester 10, and the extreme precision stable test structure of the present application is used to improve the test accuracy of the old LTX tester 10.

[0046] For example, when the LTX tester 10 was purchased in 1990 and operated for 34 years, the tester 10 was relatively old, the test accuracy was insufficient, and poor contact would occur due to slight external vibrations or touches. Therefore, when measuring products with higher precision, the LTX tester 10 needs to be improved to monitor whether there are any abnormalities in the test status during the test process to ensure that the test process can proceed smoothly and the test structure can be stable and accurate.

[0047] Specifically, the tester 10 includes a first voltage and current source 20 and a test matrix selector 30 . The first voltage and current source 20 can be connected to the force terminal and the sense terminal of the chip under test through the test matrix selector 30 .

[0048] When monitoring the tester 10, key parameters should be selected without affecting the test time, and precision devices should be used to ensure the accuracy of the monitoring test.

[0049] The tester 10 has five controllable voltage and current sources, which can provide voltage and current and can also measure them simultaneously. The first voltage and current source 20 at the output end of the key parameter measurement and its surrounding connection circuits are mainly monitored. The first voltage and current source 20 is different from other voltage and current sources in that it can be connected to the test matrix selector 30 and can be flexibly switched. The first voltage and current source 20 can be used to measure the voltage at the output end. The first voltage and current source 20 can correctly measure the voltage at the output end to determine whether the aluminum wire can be sintered correctly.

[0050] like Figures 4-5 As shown, the extreme precision stability test structure also includes a test resistor 40, which is connected to the test matrix selector 30 and can be connected to the forcing end and the sensing end of the first voltage and current source 20 through the test matrix selector 30. The test resistor 40 is used to pre-test the tester 10; wherein, after the first voltage and current source 20 applies current to the test resistor 40 through the test matrix selector 30, if the voltage on the test resistor 40 is within a preset voltage range, the first current source is connected to the chip under test through the test matrix selector 30; if the voltage on the test resistor 40 exceeds the preset voltage range, the test is stopped.

[0051] The test resistor 40 may be 100Ω, the current applied by the voltage-current source may be 12.5MA, and the preset voltage range may be 1.25V±3MV.

[0052] Among them, ±3MV is selected based on the accuracy of the tester 10 and the required accuracy of the chip under test. Once the voltage of the test resistor 40 exceeds the preset voltage range, the tester 10 stops testing and performs inspection and maintenance on the tester 10.

[0053] Furthermore, the output terminal of the test resistor 40 is grounded.

[0054] The present application uses a test resistor 40 to test the tester 10 before the first voltage and current source 20 is normally tested, and when the test voltage is within a preset voltage range, the tester 10 is used to perform a normal test on the chip under test, thereby saving the pre-testing of the existing tester 10 and being able to quickly monitor whether the tester 10 is abnormal during the test process.

[0055] Furthermore, the sintered device has one end that outputs a sine wave, and it sintered the aluminum wire fuse to adjust the output capacitance, thereby obtaining a sine wave of the required frequency. Therefore, another key parameter is to measure the waveform time, and mainly detect the AUDIO METER plate and its surrounding connections in the tester 10.

[0056] The frequency of the waveform tested by the tester 10 is the time of the test waveform, and its reciprocal is the frequency. Since the test of measuring the waveform time has higher requirements on the stability of the tester 10 and the surrounding interference shielding, the substrate and connection lines of the tester 10 need to be shielded.

[0057] Furthermore, in order to improve the stability of the tester 10, as Figures 6-7 As shown, the extreme precision stability test structure of the present application also includes a single-pole multi-throw switch 50, a detection point 60 and an active crystal oscillator 70. The input end of the single-pole multi-throw switch 50 is connected to the frequency reference end of the tester 10; the detection point 60 is connected to an output end of the single-pole multi-throw switch 50 for connecting to the chip under test; the active crystal oscillator 70 is connected to the other output end of the single-pole multi-throw switch 50; when the single-pole multi-throw switch 50 is switched to connect to the active crystal oscillator 70, the active crystal oscillator 70 monitors the measurement waveform time of the chip under test through the detection point 60, and when the measurement waveform time is within the preset time range, the single-pole multi-throw switch 50 is switched to connect to the detection point 60 to test the chip under test; if the measurement waveform time exceeds the preset time range, the test is stopped.

[0058] Among them, the single-pole multi-throw switch 50 is a single-pole double-throw controllable relay, which is electrically connected to the tester 10 and can be switched under the control of the tester 10.

[0059] For example, the tester 10 can control the single-pole double-throw controllable relay to be connected to the active crystal oscillator 70 or to be connected to the detection point 60 .

[0060] Among them, when the single-pole double-throw controllable relay is connected to the detection point 60, the tester 10 tests the chip under test normally; when the single-pole double-throw controllable relay is connected to the active crystal oscillator 70, the active crystal oscillator 70 can measure the time of the crystal oscillator output waveform, that is, the waveform output time.

[0061] Furthermore, the tester 10 also includes a counter, which is integrated in the tester 10. The tester 10 is used to control the switching frequency of the single-pole multi-throw switch 50 through the counter to control the test frequency of the active crystal oscillator 70 on the chip under test.

[0062] The counter may be a software counter, which is composed of a software program and integrated into the tester 10 .

[0063] Among them, the tester 10 controls the connection frequency between the single-pole multi-throw switch 50 and the active crystal oscillator 70 through a counter, thereby controlling the active crystal oscillator 70 to adjust the test quantity of the chip under test, so as to avoid the active crystal oscillator 70 testing too many chips under test and causing a long delay time in the time test.

[0064] The number / frequency of tests on the chip under test can be modified according to actual conditions.

[0065] Furthermore, a capacitor 80 is connected to the VCC terminal of the active crystal oscillator 70 , and the other end of the capacitor 80 is connected to a second voltage and current source.

[0066] Furthermore, the active crystal oscillator 70 is a 32.768K high-precision active crystal oscillator 70, and the preset time range is 30.5US±5US

[0067] Specifically, a 32.768K high-precision active crystal oscillator 70 and a single-pole double-throw controllable relay are installed on the substrate of the tester 10 to measure the time of the crystal oscillator output waveform at 30.5US+ / -5US. The positive and negative 5US is also a value between the accuracy of the tester 10 and the required accuracy of the device, thereby meeting the product's frequency at the K level.

[0068] Among them, since the delay time of the time test is relatively long, if each chip under test is tested once before the test process, it will affect the test time of the entire wafer. Therefore, a counter is added to the program to achieve one-side time testing for every 100 chips under test.

[0069] The extreme precision stable test structure of the present invention can timely detect whether an abnormality occurs in a device, a test board and its connection during the test process, thereby ensuring the smooth progress of the test process and making the test structure stable and accurate.

[0070] In this specification, the same or similar parts between the various embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the product embodiment described later, since it corresponds to the method, the description is relatively simple, and the relevant parts can be referred to the partial description of the system embodiment.

[0071] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. An extreme precision stable test structure, comprising a tester, the tester comprising a first voltage and current source and a test matrix selector, the first voltage and current source being connectable to a forced end and a sensing end of a chip under test through the test matrix selector, characterized in that: The extreme precision stability test structure also includes: A test resistor, the test resistor is connected to the test matrix selector and can be connected to the forcing end and the sensing end of the first voltage and current source through the test matrix selector, the test resistor is used to pre-test the tester; Among them, after the first voltage and current source applies current to the test resistor through the test matrix selector, if the voltage on the test resistor is within a preset voltage range, the first current source is connected to the chip under test through the test matrix selector; if the voltage on the test resistor exceeds the preset voltage range, the test is stopped.

2. The extreme precision stable test structure according to claim 1, characterized in that: The output end of the test resistor is grounded.

3. The extreme precision stable test structure according to claim 2, characterized in that: The test resistance is 100Ω, the current applied by the voltage-current source is 12.5MA, and the preset voltage range is 1.25V±3MV.

4. The extreme precision stable test structure according to any one of claims 1 to 3, characterized in that: Also includes: A single-pole multi-throw switch, wherein an input terminal of the single-pole multi-throw switch is connected to a frequency reference terminal of the tester; A detection point, the detection point is connected to an output end of the single-pole multi-throw switch and is used to connect to the chip under test; An active crystal oscillator connected to another output terminal of the single-pole multi-throw switch; Among them, when the single-pole multi-throw switch is switched to connect with the active crystal oscillator, the active crystal oscillator monitors the measurement waveform time of the chip under test through the detection point, and when the measurement waveform time is within a preset time range, the single-pole multi-throw switch is switched to connect with the detection point to test the chip under test; if the measurement waveform time exceeds the preset time range, the test is stopped.

5. The extreme precision stable test structure according to claim 4, characterized in that: The tester also includes: A counter is integrated in the tester, and the tester is used to control the switching frequency of the single-pole multi-throw switch through the counter to control the test frequency of the active crystal oscillator on the chip under test.

6. The extreme precision stable test structure according to claim 5, characterized in that: A capacitor is connected to the VCC terminal of the active crystal oscillator, and the other end of the capacitor is connected to a second voltage and current source.

7. The extreme precision stable test structure according to claim 4, characterized in that: The SPMT switch is a single-pole double-throw controllable relay and is electrically connected to the tester so that the tester controls the SPMT switch to switch automatically.

8. The extreme precision stable test structure according to claim 4, characterized in that: The active crystal oscillator is a 32.768K high-precision active crystal oscillator, and the preset time range is 30.5US±5US.

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