A resource allocation board for a testing machine and its detection method

Abstract

The present invention relates to the technical field of chip testing equipment, and specifically discloses a resource allocation board for a testing machine and its detection method. The board includes a resource board and a motherboard. The power supplies and input control signals of the digital channel board, the power supply board, and the high-current PMU board are all input from the backplane. The input control signal is sourced from the system control board in the power cabinet, and the interface definitions and connectors of the three resource boards with the backplane are exactly the same. The resource boards are all connected to the motherboard through connectors for output, and the connectors used by the digital channel board, the power supply board, and the high-current PMU board to connect to the motherboard are exactly the same. The connectors in the motherboard are redistributed through cables in the high-fidelity test interface and docked with the probe card for wafer testing.

Description

Technical Field

[0001] The present invention relates to the technical field of chip testing equipment, and in particular to a resource allocation board for a testing machine and a detection method thereof. Background Art

[0002] With the continuous advancement of electronic technology, personal computers, workstations, smart devices, monitoring equipment, etc. are widely popularized. These devices use a large number of memory chips, control chips, logic chips, etc., making the importance of chip testing equipment increasingly prominent. When testing memory chips, in order to improve the test efficiency, multi-channel simultaneous testing is usually adopted, which requires the tester to have many channels.

[0003] At present, most designed load boards often use fixed area interfaces and channels in circuit design, and the board compatibility is poor. When faced with different test requirements, the board has to be redesigned, which not only increases the cost, but also consumes a lot of time and energy. Take our company's memory chip tester as an example, it includes digital channel board, power channel board, high current channel board, and the total number of channels is over 10,000. Such a large number of channels need to be integrated on the motherboard, and then connected to the probe card through cables. There are many problems in practical applications: on the one hand, the large number of channels leads to a large number of transfer cables, the installation space of the motherboard and cable is tight, and the installation and removal operations are cumbersome; on the other hand, it is very important to detect the connectivity of the motherboard and cable before installation, but the existing detection methods are not convenient and efficient enough. At the same time, when locating channel problems, the traditional control variable method of exchanging various boards is inefficient, which is not conducive to the rapid maintenance of equipment.

[0004] In addition, when storing calibration data, the existing technology has a contradiction between accuracy and storage space. To improve accuracy, a large-capacity flash memory is required to store calibration data, resulting in insufficient flexibility in the storage and use of calibration data. In the entire test system, due to the complex connection links from the resource board to the terminal, the existing detection method is difficult to accurately determine whether the problem in the calibration process is caused by a short circuit or the resource board itself. Summary of the invention

[0005] The purpose of the present invention is to provide a resource allocation board for a test machine and a detection method thereof to solve the above technical problems:

[0006] The purpose of the present invention can be achieved by the following technical solutions:

[0007] A resource allocation board for a test machine, comprising a resource board and a motherboard, wherein the resource board comprises a digital channel board, a power board and a high-current PMU board;

[0008] The power supplies and input control signals of the digital channel board card, power supply board card, and high-current PMU board card are all input from the backplane. The input control signals are sourced from the system control board card in the power supply cabinet, and the interface definitions and connectors of the three resource board cards with the backplane are exactly the same;

[0009] The digital channel board card, power supply board card, and high-current PMU board card are all connected to the motherboard through connectors for output, and the connectors used by the digital channel board card, power supply board card, and high-current PMU board card to connect to the motherboard are exactly the same;

[0010] The connectors in the motherboard are redistributed through cables in the high-fidelity test interface and docked with the probe card for wafer testing.

[0011] As a further solution of the present invention: The sequence of the slots on the motherboard is fixedly defined by the backplane through the control board card in the power supply cabinet, and each control board card corresponds to a resource board card at a fixed position;

[0012] Each resource board card is docked with the motherboard through four connectors. The connector located on the back of the motherboard is defined as the Site side; the connector located on the front of the motherboard and used to connect to the high-fidelity test interface is defined as the LIF side.

[0013] As a further solution of the present invention: The channels in the digital channel board card connector are output in one-to-one correspondence with the channels in the LIF side connector; the channels in the power supply board card and high-current PMU board card are evenly distributed horizontally and output in the LIF side connector.

[0014] As a further solution of the present invention: The motherboard also includes MB-I and MB-J, where MB-I connects the power supplies and ground planes in different quadrants, and MB-J connects the motherboard and the backplane for introducing the control signals in the control board card.

[0015] A detection circuit for a resource allocation board card of a test machine, the detection circuit includes a detection board, a measurement board, and a motherboard:

[0016] The connectors in the detection board are connected to the LIF side connectors at the ends of the motherboard through cables. When the circuit is turned on and there is no open or short circuit problem with the motherboard, the light-emitting diodes in the detection board emit light normally;

[0017] The backplane is connected to the Site side of the motherboard to provide an external 5V input level;

[0018] The measurement board is a module of a multiplexing plus analog-to-digital converter in the system resource board. Signals in the motherboard are connected to the multiplexer in the measurement board. The signals include 1 PMU signal, 33 DPS signals, 82 PE signals, and 10 Ubit signals. These signals collect voltages through the analog-to-digital converter of the control board, and determine the open or short circuit conditions based on the collected voltages.

[0019] During detection, instead of using the MB-J board connecting the motherboard and the backplane, the connector interface of the MB-J is used and connected to the measurement board through a cable, and the detection results of the motherboard are synchronously displayed.

[0020] A detection method for a resource allocation board of a test machine, the method includes:

[0021] Perform circuit continuity detection through a detection circuit: Connect the detection board to the LIF side connector of the motherboard through a cable. The backplane provides a 5V input level to the Site side of the motherboard. Initially judge whether there are open or short circuit problems in the motherboard according to whether the light-emitting diodes in the detection board emit light normally.

[0022] If there is a problem channel, use the time domain reflection method to locate the problem point: A step signal is generated inside the resource board for the channel with continuity problems. After this signal is transmitted through the resource board, connector, motherboard, connector and cable, high-fidelity test interface, and probe card path, the reflected voltage is collected; According to the reflected voltage, use the formula Calculate the impedance value at the suspected break point;

[0023] Where Z dut is the impedance at the suspected break point, Z 0 is the known characteristic impedance, V i is the incident voltage, V r is the reflected voltage;

[0024] According to the performance of the impedance value on the time axis, combined with the signal propagation speed, calculate the location of the break point, generate a TDR curve and display it.

[0025] As a further solution of the present invention: Before performing wafer testing, first perform open / short circuit detection on the entire system path to eliminate the influence of path open / short circuit on the calibration result.

[0026] Advantages of the present invention: By designing a compatible resource board interface and a flexibly designable motherboard, different test requirements can be met only by replacing the motherboard, avoiding the need to redesign the board each time, reducing costs and the design cycle; the detection circuit has minor modifications based on the original system, and only the interface board in contact with the chip under test at the top layer needs to be replaced to operate in the E-commerce Workbench (EWS), and multiple functions of the original system can be reused. Each pin is connected to a light-emitting diode, enabling intuitive observation of the on / off results of different channels, facilitating quick detection of the motherboard and cable connectivity before installation and during on-site troubleshooting; the time-domain reflection technology is used to locate the problem points in the channels, greatly improving the location efficiency compared with the traditional control variable method, making it convenient for maintenance personnel to quickly determine the break point position, promptly replace the components or boards at the specified position, and enhancing the maintainability of the device; introducing open / short circuit detection for the entire system path after installation and before calibration can eliminate the influence of path open / short circuit on the calibration results and improve the accuracy of calibration. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The present invention will be further described below in conjunction with the accompanying drawings.

[0028] Figure 1 is a schematic structural diagram of a resource allocation board for a test machine in the present invention;

[0029] Figure 2 is a structural block diagram of a template in the present invention;

[0030] Figure 3 is a schematic structural diagram of a detection circuit in the present invention;

[0031] Figure 4 is a schematic diagram of the principle of impedance calculation in the present invention;

[0032] Figure 5 is a schematic diagram of the break point position in the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0033] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0034] The present invention relates to a resource allocation board for a test machine. The test head (Tester Header) is divided into 4 quadrants, and each quadrant is as Figure 1 shown:

[0035] The resource boards of the system are divided into three types: digital channel board (HSU320), power supply board (PSU128), and high-current PMU board (HCU512);

[0036] 1) The power supply and input control signals are input from the backplane. The control signals are sourced from the system control board (SMB) in the power supply cabinet. The interface definitions and their connectors between the three resource boards and the backplane are exactly the same.

[0037] 2) The outputs of the three resource boards are connected to the motherboard (MotherBoard or MB) through connectors (the connectors of the three boards are exactly the same) for output.

[0038] 3) Since the inputs are compatible and the output connectors are compatible, the three boards are compatible. Only a new motherboard needs to be designed to meet different types of test requirements.

[0039] 4) The connectors in the motherboard are redistributed through cables in the high-fidelity test interface (HIFIX) and docked with the probe card for wafer testing.

[0040] The motherboard block diagram is as Figure 2 shown:

[0041] 1) The sequence of channels (slots) is fixed-defined through the backplane using the SMB control board in the power supply cabinet. Each slot corresponds to a resource board at a fixed position.

[0042] 2) Each resource board has four connectors to dock with the Mother Board. They are inserted into the back of the Mother Board and are called the Site side; the connectors connected to the HIFIX are placed on the front of the Mother Board and are called the LIF side.

[0043] 3) The channels in the connectors of the digital board HSU320 are output in one-to-one correspondence with the channels in the LIF side connectors. The channels in the power supply board PSU128 and the high-current board HCU512 are output in a horizontally uniform distribution in the LIF side connectors.

[0044] 4) MB-I connects the power supply and ground planes in different quadrants to facilitate calibration of the power supply and ground planes in different quadrants. MB-J connects the Mother Board to the backplane so that the control signals in the SMB can be introduced.

[0045] The detection circuit composition is as Figure 3As shown, the connector in the Check Board is connected to the LIF side connector in the MotherBoard through a Cable. When the circuit is turned on and there is no short - circuit problem in the Mother Board, the light - emitting diodes in the Check Board emit light normally; the backplane is connected to the Site side of the Mother Board, providing an external 5V input level; the signals in the Mother Board are connected to the multiplexer in the Measure Board. The signals in each connector include 17 PMU signals, 33 DPS signals, 82 PE signals, and 10 Ubit signals; finally, the detection results of the MotherBoard are synchronously displayed in the EWS for users' reference.

[0046] As Figure 4 shown, a detection method for a resource allocation board card of a test machine includes:

[0047] Using the time - domain reflection method to check the problem points:

[0048] 1) Since there are many connections used in the entire path from the resource board card to the terminal: resource board card - connector - motherboard - connector and harness - HiFix - Probe Card. When using the detection circuit to check all channels in the third step, if there are problems, we need to find out where the problem points are in the entire path, which is very difficult for the maintenance of the entire system. Therefore, after checking the circuit continuity, we added the time - domain reflection method to locate where the problem points of this channel are, which greatly improves the maintainability of the entire system.

[0049] 2) The principle of time - domain reflection:

[0050] For channels with continuity problems, a step signal is generated inside the resource board card. After passing through the above - mentioned path, the reflected voltage is collected. According to the reflected voltage, the impedance value of the impedance discontinuity (which may be the break point) is calculated. According to the performance of the impedance value on the entire time axis, the position of the break point is calculated. Finally, through integration, the final TDR curve is obtained and displayed in the EWS for users' reference.

[0051] 3) Impedance calculation at suspected break points:

[0052] Assume that the DUT (device under test) is a transmission line with a 60 - ohm characteristic impedance and a 250 - ps delay. The voltage curve measured at point A is shown in the following figure. Based on the voltage waveform at point A, the impedance information of the subsequent DUT can be calculated. The calculation method is as follows:

[0053] Z 0 and Z dutThe incident voltage and the reflected voltage at the position of the junction point are V i , V r . Then, from the formula of the reflection coefficient: V r / V i = (Z dut - Z 0 ) / (Z dut + Z 0 );

[0054] Then Z dut = Z 0 * (V i + V r ) / (V i - V r );

[0055] From Figure 4 we can see that V r is equal to 0.091V, and Z dut = 50 * (1 + 0.091) / (1 + 0.091) = 60.

[0056] 4) Calculation of the position of the suspected break point

[0057] As Figure 5 shown, for a 48 ohm, 5 inch line, at a propagation speed of 6 mil / ps, and then the wave propagates back and forth twice the transmission distance, it can be obtained that it takes about 1.66 ns, which is approximately consistent with the time on the graph:

[0058] t = 2 * 5000 mil / (6 mil / ps) = 1.66 ns;

[0059] Conversely, we can also obtain the position of the distance sampling point based on the time of the impedance discontinuity point in the picture.

[0060] That is:

[0061] l = (1.66 ns * 6 mil / ps) / 2 = 5 inch;

[0062] In other words, if there is a break point somewhere from the resource board to the terminal, according to the relationship between time and impedance in time domain reflection, the distance of the suspected break point is calculated based on the time of the impedance high point, and the location of the break point in the entire path is judged based on the distance.

[0063] The above has described a specific embodiment of the present invention in detail, but the described content is only a preferred embodiment of the present invention and cannot be considered as limiting the scope of implementation of the present invention. All equivalent changes and improvements made according to the scope of the present invention application should still fall within the scope covered by the patent of the present invention.

Claims

1. A detection circuit for a resource allocation board of a test machine, comprising a resource board and a motherboard, characterized in that: The detection circuit includes a detection board and a measurement board: The connector in the detection board is connected to the LIF side connector in the motherboard through a cable. When the circuit is connected and there is no open or short circuit problem in the motherboard, the light-emitting diode in the detection board emits light normally. The backplane is connected to the Site side of the motherboard to provide an external 5V input level; The measurement board is a multiplexing and analog-to-digital converter module in the system resource board. The signals in the motherboard are connected to the multiplexing selector in the measurement board. The signals include 1 PMU signal, 33 DPS signals, 82 PE signals and 10 Ubit signals. These signals collect voltage through the analog-to-digital converter of the control board, and the open circuit or short circuit situation is judged according to the collected voltage. During the test, the MB-J board connecting the motherboard and the backplane is not used. Instead, the connector interface of the MB-J is used to connect to the measurement board through a cable, and the test results of the motherboard are displayed synchronously; The resource boards include a digital channel board, a power board and a high-current PMU board; The power supply and input control signals of the digital channel card, power card, and high-current PMU card are all input from the backplane, and the input control signal originates from the system control card in the power cabinet, and the interface definitions and connectors of the three resource cards and the backplane are exactly the same; The digital channel board, the power board and the high-current PMU board are all connected to the motherboard through connectors for output, and the connectors used by the digital channel board, the power board and the high-current PMU board to connect to the motherboard are completely consistent; The connectors in the motherboard are redistributed in a high-fidelity test interface through cables and docked with a probe card for wafer testing; The sequence of the slots on the motherboard is fixedly defined by the backplane through the control board in the power cabinet, and each control board corresponds to a resource board at a fixed position; Each resource board is connected to the motherboard through four connectors, and the connector located at the back of the motherboard is defined as Siteside; the connector located at the front of the motherboard for connecting with the high-fidelity test interface is defined as LIF side; The motherboard also includes MB-I and MB-J, wherein MB-I connects power supplies and ground planes in different quadrants, and MB-J connects the motherboard and the backplane to introduce control signals in the control board.

2. A detection circuit for a resource allocation board of a test machine according to claim 1, characterized in that: The channels in the digital channel card connector are output in one-to-one correspondence with the channels in the LIF side connector; the channels in the power card and the high-current PMU card are output in the LIF side connector in a uniformly distributed manner in the horizontal direction.

3. A method for testing a resource allocation board of a test machine, characterized in that: Applied to the detection circuit of claim 2, the method comprising: Conduct circuit continuity test through the detection circuit: Connect the detection board to the LIF side connector of the motherboard through a cable. The backplane provides a 5V input level to the Site side of the motherboard. Preliminary judgment on whether the motherboard has an open or short circuit problem is made based on whether the LED in the detection board emits light normally. If there is a problem channel, the time domain reflection method is used to locate the problem point: the resource board generates a step signal for the channel with on-off problem. The signal is transmitted through the resource board, connector, motherboard, connector and cable, high-fidelity test interface, and probe card path, and then the reflected voltage is collected; according to the reflected voltage, the formula is used Calculate the impedance value at the suspected breakpoint; Where Z dut is the impedance at the suspected breakpoint, Z0 is the known characteristic impedance, V i is the incident voltage, V r is the reflected voltage; According to the performance of the impedance value on the time axis and the signal propagation speed, the location of the breakpoint is calculated, and the TDR curve is generated and displayed.

4. A detection method for resource allocation board of a test machine according to claim 3, characterized in that: Before conducting wafer testing, the entire system path is first tested for open and short circuits to eliminate the impact of path open and short circuits on calibration results.

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