A voltage-stabilized starting circuit without operational amplifier for high voltage and a voltage-stabilized starting method thereof

Abstract

The present invention discloses a high-voltage op-amp-free voltage-stabilizing startup circuit and a voltage-stabilizing startup method thereof. The circuit includes a voltage-stabilizing circuit and a startup circuit. The startup circuit generates a bias current Ibias2. In the voltage-stabilizing circuit, a transistor Q7 and a PMOS transistor PDM2 form a first common-emitter amplifier, an NMOS transistor NDM2 and a PMOS transistor PDM3 form a first common-source amplifier, and a PMOS transistor PDM4, a transistor Q6, a resistor R4, and a transistor Q5 form a second common-source amplifier. The present invention does not require the additional design of a pre-voltage-stabilizing circuit and a high-voltage operational amplifier, thereby saving chip area. Furthermore, after the voltage-stabilizing startup circuit is started, the startup circuit does not need to be shut down.

Description

Technical Field

[0001] The present invention relates to a voltage-stabilized starting circuit and a voltage-stabilized starting method thereof, in particular to an operational amplifier-free voltage-stabilized starting circuit and a voltage-stabilized starting method thereof applied to high voltage, belonging to the technical field of semiconductor integrated circuits. Background Art

[0002] As an important component of a chip, the voltage regulator circuit provides a stable operating voltage for the analog and digital circuits within the chip, ensuring the chip can operate normally. Because some applications require both low and high power supply voltages, it is crucial to ensure that the voltage regulator circuit can operate normally under both low and high power supply voltages.

[0003] The block diagram of the traditional voltage stabilization circuit used for high voltage is as follows: Figure 2 As shown, its operating principle is that the pre-regulator circuit steps down the external high-voltage power supply VS to provide a low-voltage power supply for the low-voltage bandgap reference circuit, ensuring that the low-voltage bandgap reference circuit is not damaged by the external high-voltage power supply VS. The output VREF of the bandgap reference circuit provides a reference voltage for the negative input of the high-voltage operational amplifier HV_AMP1. The positive input of the high-voltage operational amplifier HV_AMP1 is connected to the output of the high-voltage operational amplifier HV_AMP1 and then to the gate of the high-voltage PMOS regulator PDM1. The drain of the high-voltage PMOS regulator PDM1 is input to the positive input of the high-voltage operational amplifier HV_AMP1 through resistor R2, forming a negative feedback loop. Through this negative feedback loop, the positive input and negative input of the high-voltage operational amplifier HV_AMP1 are clamped to be equal. Then, the output voltage VLDO of the voltage regulator circuit is:

[0004] VLDO= VREF*(R1+R2) / R2

[0005] The above analysis shows that conventional high-voltage voltage regulators require a pre-regulator circuit to provide a low-voltage power supply for the low-voltage bandgap reference circuit. To achieve negative feedback clamping at high voltages, a high-voltage operational amplifier is required, significantly increasing design complexity and requiring a larger chip area. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide an op amp-free voltage-stabilizing startup circuit and a voltage-stabilizing startup method thereof for high voltage, which does not require an additional op amp and can stably generate an output voltage VLDO.

[0007] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0008] A non-op-amp voltage-stabilizing startup circuit for high voltage includes a voltage-stabilizing circuit and a startup circuit. The startup circuit generates a bias current Ibias2. The voltage-stabilizing circuit includes a transistor Q2, a transistor Q3, a transistor Q4, a transistor Q5, a transistor Q6, a transistor Q7, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a PMOS transistor PDM3, a PMOS transistor PDM4, an NMOS transistor NDM2, and a Zener diode Z2. The cathode of the Zener diode Z2 is connected to the collector of the transistor Q7 and the gate of the NMOS transistor NDM2 and is connected to the bias current Ibias2. The base of the transistor Q7 is connected to the collector of the transistor Q5, the base of the transistor Q5, the base of the transistor Q4, and the collector of the transistor Q3. The base of the transistor Q3 is connected to the base of the transistor Q2, the collector of the transistor Q2, and the collector of the transistor Q4. The emitter of transistor Q3 is connected to one end of resistor R3, the emitter of transistor Q5 is connected to one end of resistor R4 and the emitter of transistor Q4, the other end of resistor R4 is connected to the emitter of transistor Q6, the collector of transistor Q6 is connected to the drain of PMOS transistor PDM4 and one end of resistor R6 to generate an output voltage VLDO, the base of transistor Q6 is connected to the other end of resistor R6 and one end of resistor R5, the source of PMOS transistor PDM4 and the source of PMOS transistor PDM3 are connected to power supply VS, the gate of PMOS transistor PDM4 is connected to the gate of PMOS transistor PDM3, the drain of PMOS transistor PDM3 and the drain of NMOS transistor NDM2 are connected, and the anode of Zener diode Z2, the emitter of transistor Q7, the source of NMOS transistor NDM2, the other end of resistor R3, the emitter of transistor Q2 and the other end of resistor R5 are grounded.

[0009] Furthermore, the startup circuit includes a resistor R1, a resistor R2, a transistor Q1, an NMOS transistor NDM1, a PMOS transistor PDM1, a PMOS transistor PDM2 and a Zener diode Z1, one end of the resistor R1 is connected to the source of the PMOS transistor PDM1, the source of the PMOS transistor PDM2 and the power supply VS, the other end of the resistor R1 is connected to the collector of the transistor Q1, the cathode of the Zener diode Z1 and the gate of the NMOS transistor NDM1, the base of the transistor Q1 is connected to the source of the NMOS transistor NDM1 and one end of the resistor R2, the drain of the NMOS transistor NDM1 is connected to the drain of the PMOS transistor PDM1, the gate of the PMOS transistor PDM1 and the gate of the PMOS transistor PDM2, the drain of the PMOS transistor PDM2 outputs a bias current Ibias2, and the emitter of the transistor Q1, the anode of the Zener diode Z1 and the other end of the resistor R2 are grounded.

[0010] Furthermore, the NMOS transistors NDM1 and NDM2 are high-voltage NMOS transistors, and the PMOS transistors PDM1, PMOS transistors PDM2, PMOS transistors PDM3 and PMOS transistors PDM4 are high-voltage PMOS transistors.

[0011] Furthermore, the transistor Q7 and the PMOS transistor PDM2 form a first common-emitter amplifier, the NMOS transistor NDM2 and the PMOS transistor PDM3 form a first common-source amplifier, and the PMOS transistor PDM4 and the transistor Q6, the resistor R4 and the transistor Q5 form a second common-source amplifier.

[0012] Furthermore, the transistors Q4 and Q5 are PNP transistors, and the transistors Q4 and Q5 form a first PNP current mirror. The transistors Q1 , Q2 , Q3 , Q6 and Q7 are NPN transistors.

[0013] Furthermore, the PMOS transistor PDM1 and the PMOS transistor PDM2 form a first PMOS current mirror, and the PMOS transistor PDM3 and the PMOS transistor PDM4 form a second PMOS current mirror.

[0014] Furthermore, the resistor R1, the resistor R2, the transistor Q1, the NMOS transistor NDM1, the PMOS transistor PDM1, the PMOS transistor PDM2 and the Zener diode Z1 form a high-voltage Wilson current source.

[0015] A voltage stabilization startup method for a high voltage op amp-free voltage stabilization startup circuit includes the following steps:

[0016] The collector of the transistor Q5 is connected to the input end of a first common-emitter amplifier formed by the transistor Q7 and the PMOS transistor PDM2. The output end of the first common-emitter amplifier is connected to the input end of a first common-source amplifier formed by the NMOS transistor NDM2 and the PMOS transistor PDM3. The output end of the first common-source amplifier is connected to a second common-source amplifier formed by the high-voltage PMOS transistor PDM4, the transistor Q6, the resistor R4, and the triode Q5. The first common-emitter amplifier, the first common-source amplifier, and the second common-source amplifier form a negative feedback loop. A stable output voltage VLDO is obtained through negative feedback compensation.

[0017] The first PNP current mirror formed by transistors Q4 and Q5 ensures that the currents flowing through transistors Q2 and Q3 are equal. Due to the different areas of transistors Q2 and Q3, there is a positive temperature coefficient voltage difference △VBE between the base-emitter voltages VBE of transistors Q2 and Q3. This positive temperature coefficient voltage difference △VBE divided by the zero temperature coefficient resistor R3 yields the positive temperature coefficient current Ip. The base voltage of transistor Q6 is equal to the base-emitter voltage VBE7 of transistor Q7 (with a negative temperature coefficient) plus the base-emitter voltage VBE5 of transistor Q5 (with a negative temperature coefficient) plus the voltage drop across resistor R4 (2*Ip*R4) plus the base-emitter voltage VBE6 of transistor Q6 (with a negative temperature coefficient), i.e., VBE7+VBE5+2*Ip*R4+VBE6. Therefore, the output voltage VLDO is:

[0018] VLDO=(VBE7+VBE5+2*Ip*R4+VBE6)*(R6+R5) / R5

[0019] By adjusting the value of resistor R4, temperature compensation is achieved to obtain a voltage with zero temperature coefficient;

[0020] The Zener diode Z2 is used to clamp the collector-emitter voltage VCE7 of the transistor Q7 and the gate-source voltage VGSN2 of the NMOS transistor NDM2 so as to be lower than the Zener diode clamping voltage VZ2, thereby preventing the collector-emitter of the transistor Q7 and the gate-source of the NMOS transistor NDM2 from being broken down.

[0021] When the power supply VS starts to power on, the circuit is in a zero current state. At this time, the current on the resistor R1 is zero and the voltage drop is zero. The voltage at one end of the resistor R1 increases as VS increases. Similarly, the current on the resistor R2 is zero and the voltage drop is zero. The voltage at one end of the resistor R2 is zero. As the voltage at one end of the resistor R1 increases, the NMOS transistor NDM1 gradually turns on and generates a bias current Ibias. The bias current Ibias flows through the resistor R2 and generates a voltage drop, causing the voltage at one end of the resistor R2 to start increasing, and eventually the transistor Q1 turns on. After the circuit stabilizes, the voltage drop on the resistor R2 is equal to the base-emitter voltage VBE1 of the transistor Q1, and the bias current Ibias is equal to VBE1 / R2. The bias current Ibias The PMOS transistors PDM1 and PMOS transistors PDM2 in the first PMOS current mirror are copied and flow into the transistor Q7 to provide a bias current Ibias2 for the transistor Q7, thereby determining the base-emitter voltage VBE7 of the transistor Q7. The high-voltage Wilson current source has no degeneracy point and can start normally. After the high-voltage Wilson current source is started, the drain terminal of the PMOS transistor PDM2 in the first PMOS current mirror is high, the gate terminal of the NMOS transistor NDM2 in the first common-source amplifier is high-conducting, the gate terminal and drain terminal of the PMOS transistor PDM3 in the first common-source amplifier are low-conducting, and the gate terminal of the PMOS transistor PDM4 in the second common-source amplifier is low-conducting, thereby starting the entire circuit.

[0022] Compared with the prior art, the present invention has the following advantages and effects: The present invention provides an op amp-free voltage-stabilizing startup circuit and a voltage-stabilizing startup method for high voltage applications, which uses a common-emitter amplifier and two common-source amplifiers to form a negative feedback loop. A stable output voltage VLDO is obtained through negative feedback compensation, eliminating the need for additional pre-voltage regulator circuits and high-voltage operational amplifiers, thereby saving chip area. Moreover, after the voltage-stabilizing startup circuit is started, there is no need to shut down the startup circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 The present invention is a schematic diagram of a voltage-stabilizing startup circuit without an operational amplifier applied to high voltage.

[0024] Figure 2 The present invention is a schematic diagram of a voltage stabilizing circuit structure applied to high voltage in the prior art. DETAILED DESCRIPTION

[0025] In order to elaborate on the technical solutions adopted by the present invention to achieve the predetermined technical purpose, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments, and the technical means or technical features in the embodiments of the present invention can be replaced without creative work. The present invention will be described in detail below with reference to the drawings and in conjunction with the embodiments.

[0026] like Figure 1 As shown, a voltage-stabilizing startup circuit for high voltage without an operational amplifier of the present invention includes a voltage-stabilizing circuit and a startup circuit. The startup circuit generates a bias current Ibias2. The voltage-stabilizing circuit includes transistors Q2, Q3, Q4, Q5, Q6, Q7, resistors R3, R4, R5, R6, PMOS transistors PDM3, PMOS transistors PDM4, NMOS transistors NDM2, and a Zener diode Z2. The cathode of the Zener diode Z2 is connected to the collector of the transistor Q7 and the gate of the NMOS transistor NDM2 and is connected to the bias current Ibias2. The base of the transistor Q7 is connected to the collector of the transistor Q5, the base of the transistor Q5, the base of the transistor Q4, and the collector of the transistor Q3. The base of the transistor Q3 is connected to the base of the transistor Q2, the collector of the transistor Q2, and the collector of the transistor Q4. The emitter of transistor Q3 is connected to one end of resistor R3, the emitter of transistor Q5 is connected to one end of resistor R4 and the emitter of transistor Q4, the other end of resistor R4 is connected to the emitter of transistor Q6, the collector of transistor Q6 is connected to the drain of PMOS transistor PDM4 and one end of resistor R6 to generate output voltage VLDO, the base of transistor Q6 is connected to the other end of resistor R6 and one end of resistor R5, the source of PMOS transistor PDM4 and the source of PMOS transistor PDM3 are connected to power supply VS, the gate of PMOS transistor PDM4 is connected to the gate of PMOS transistor PDM3, the drain of PMOS transistor PDM3 and the drain of NMOS transistor NDM2, the anode of Zener diode Z2, the emitter of transistor Q7, the source of NMOS transistor NDM2, the other end of resistor R3, the emitter of transistor Q2 and the other end of resistor R5 are grounded;

[0027] The startup circuit includes a resistor R1, a resistor R2, a transistor Q1, an NMOS transistor NDM1, a PMOS transistor PDM1, a PMOS transistor PDM2, and a Zener diode Z1. One end of the resistor R1 is connected to the source of the PMOS transistor PDM1, the source of the PMOS transistor PDM2, and the power supply VS. The other end of the resistor R1 is connected to the collector of the transistor Q1, the cathode of the Zener diode Z1, and the gate of the NMOS transistor NDM1. The base of the transistor Q1 is connected to the source of the NMOS transistor NDM1 and one end of the resistor R2. The drain of the NMOS transistor NDM1 is connected to the drain of the PMOS transistor PDM1, the gate of the PMOS transistor PDM1, and the gate of the PMOS transistor PDM2. The drain of the PMOS transistor PDM2 outputs a bias current Ibias2. The emitter of the transistor Q1, the anode of the Zener diode Z1, and the other end of the resistor R2 are grounded.

[0028] The NMOS transistors NDM1 and NMOS transistor NDM2 are high-voltage NMOS transistors, and the PMOS transistors PDM1, PMOS transistor PDM2, PMOS transistor PDM3 and PMOS transistor PDM4 are high-voltage PMOS transistors.

[0029] Transistor Q7 and PMOS transistor PDM2 form a first common-emitter amplifier, NMOS transistor NDM2 and PMOS transistor PDM3 form a first common-source amplifier, and PMOS transistor PDM4, transistor Q6, resistor R4, and transistor Q5 form a second common-source amplifier. The first common-emitter amplifier, first common-source amplifier, and second common-source amplifier form a negative feedback loop, which generates a stable output voltage VLDO through negative feedback compensation.

[0030] The transistor Q4 and the transistor Q5 are PNP transistors, and the transistor Q4 and the transistor Q5 form a first PNP current mirror. The transistor Q1 , the transistor Q2 , the transistor Q3 , the transistor Q6 and the transistor Q7 are NPN transistors.

[0031] The PMOS transistor PDM1 and the PMOS transistor PDM2 form a first PMOS current mirror, and the PMOS transistor PDM3 and the PMOS transistor PDM4 form a second PMOS current mirror.

[0032] The resistor R1, the resistor R2, the transistor Q1, the NMOS transistor NDM1, the PMOS transistor PDM1, the PMOS transistor PDM2 and the Zener diode Z1 form a high-voltage Wilson current source.

[0033] A voltage stabilization startup method for a high voltage op amp-free voltage stabilization startup circuit includes the following steps:

[0034] The collector of transistor Q5 is connected to the input of a first common-emitter amplifier formed by transistor Q7 and PMOS transistor PDM2. The output of the first common-emitter amplifier is connected to the input of a first common-source amplifier formed by NMOS transistor NDM2 and PMOS transistor PDM3. The output of the first common-source amplifier is connected to a second common-source amplifier formed by high-voltage PMOS transistor PDM4, transistor Q6, resistor R4, and triode Q5. The first common-emitter amplifier, the first common-source amplifier, and the second common-source amplifier form a negative feedback loop. A stable output voltage VLDO is obtained through negative feedback compensation.

[0035] The first PNP current mirror formed by transistors Q4 and Q5 ensures that the currents flowing through transistors Q2 and Q3 are equal. Due to the different areas of transistors Q2 and Q3, there is a positive temperature coefficient voltage difference △VBE between the base-emitter voltages VBE of transistors Q2 and Q3. This positive temperature coefficient voltage difference △VBE divided by the zero temperature coefficient resistor R3 yields the positive temperature coefficient current Ip. The base voltage of transistor Q6 is equal to the base-emitter voltage VBE7 of transistor Q7 (with a negative temperature coefficient) plus the base-emitter voltage VBE5 of transistor Q5 (with a negative temperature coefficient) plus the voltage drop across resistor R4 (2*Ip*R4) plus the base-emitter voltage VBE6 of transistor Q6 (with a negative temperature coefficient), i.e., VBE7+VBE5+2*Ip*R4+VBE6. Therefore, the output voltage VLDO is:

[0036] VLDO=(VBE7+VBE5+2*Ip*R4+VBE6)*(R6+R5) / R5

[0037] Temperature compensation is achieved by adjusting the value of resistor R4 to obtain a voltage with zero temperature coefficient.

[0038] The Zener diode Z2 is used to clamp the collector-emitter voltage VCE7 of the transistor Q7 and the gate-source voltage VGSN2 of the NMOS transistor NDM2 so as to be lower than the Zener diode clamping voltage VZ2, thereby preventing the collector-emitter of the transistor Q7 and the gate-source of the NMOS transistor NDM2 from being broken down.

[0039] Resistor R1, resistor R2, transistor Q1, NMOS transistor NDM1, PMOS transistor PDM1, PMOS transistor PDM2, and Zener diode Z1 form a high-voltage Wilson current source. When power supply VS is turned on, the circuit is in a zero-current state. At this time, the current in resistor R1 is zero, the voltage drop is zero, and the voltage across resistor R1 increases as VS increases. Similarly, the current in resistor R2 is zero, the voltage drop is zero, and the voltage across resistor R2 is zero. As the voltage across resistor R1 increases, NMOS transistor NDM1 gradually turns on, generating bias current Ibias. Bias current Ibias flows through resistor R2, generating a voltage drop, causing the voltage across resistor R2 to begin to increase, ultimately turning on transistor Q1. After the circuit stabilizes, the voltage drop across resistor R2 equals the base-emitter voltage VBE1 of transistor Q1, and bias current Ibias is equal to VBE1 / R2. Bias current Ibias By replicating the currents of PMOS transistors PDM1 and PMOS transistors PDM2 in the first PMOS current mirror and flowing them into transistor Q7, bias current Ibias2 is provided to transistor Q7, determining the base-emitter voltage VBE7 of transistor Q7. The high-voltage Wilson current source has no degeneracy point and can start normally. After the high-voltage Wilson current source is started, the drain of PMOS transistor PDM2 in the first PMOS current mirror is high, and the gate of NMOS transistor NDM2 in the first common-source amplifier is high. This then causes the gate and drain of PMOS transistor PDM3 in the first common-source amplifier to be low, and the gate of PMOS transistor PDM4 in the second common-source amplifier to be low, thereby starting the entire circuit. Furthermore, compared to traditional startup circuits, the startup circuit does not need to be shut down after startup.

[0040] The present invention provides an op amp-free voltage-stabilizing startup circuit and a voltage-stabilizing startup method for high voltage applications. A common-emitter amplifier and two common-source amplifiers form a negative feedback loop, and a stable output voltage VLDO is obtained through negative feedback compensation. No additional pre-voltage regulator circuit and high-voltage operational amplifier are required, thereby saving chip area. Furthermore, after the voltage-stabilizing startup circuit is started, there is no need to shut down the startup circuit.

[0041] The above description is merely a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Although the present invention has been disclosed as a preferred embodiment as above, it is not intended to limit the present invention. Any technician familiar with the present profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical content disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent replacement and improvement of the above embodiments made according to the technical essence of the present invention, within the spirit and principles of the present invention, without departing from the content of the technical solution of the present invention, shall still fall within the scope of protection of the technical solution of the present invention.

Claims

1. A voltage-stabilizing startup circuit without an operational amplifier for high voltage applications, characterized in that: The invention comprises a voltage stabilizing circuit and a startup circuit, wherein the startup circuit generates a bias current Ibias2. The voltage stabilizing circuit comprises transistors Q2, Q3, Q4, Q5, Q6, Q7, resistors R3, R4, R5, R6, PMOS transistors PDM3, PMOS transistors PDM4, NMOS transistors NDM2 and Zener diode Z2. The cathode of Zener diode Z2 is connected to the collector of transistor Q7 and the gate of NMOS transistor NDM2 and is connected to the bias current Ibias2. The base of transistor Q7 is connected to the collector of transistor Q5, the base of transistor Q5, the base of transistor Q4 and the collector of transistor Q3. The base of transistor Q3 is connected to the base of transistor Q2, the collector of transistor Q2 and the collector of transistor Q4. The emitter of transistor Q3 is connected to resistor R 3, the emitter of the transistor Q5 is connected to one end of the resistor R4 and the emitter of the transistor Q4, the other end of the resistor R4 is connected to the emitter of the transistor Q6, the collector of the transistor Q6 is connected to the drain of the PMOS transistor PDM4 and one end of the resistor R6 to generate an output voltage VLDO, the base of the transistor Q6 is connected to the other end of the resistor R6 and one end of the resistor R5, the source of the PMOS transistor PDM4 and the source of the PMOS transistor PDM3 are connected to the power supply VS, the gate of the PMOS transistor PDM4 is connected to the gate of the PMOS transistor PDM3, the drain of the PMOS transistor PDM3 and the drain of the NMOS transistor NDM2 are connected, the anode of the Zener diode Z2, the emitter of the transistor Q7, the source of the NMOS transistor NDM2, the other end of the resistor R3, the emitter of the transistor Q2 and the other end of the resistor R5 are grounded; The startup circuit includes a resistor R1, a resistor R2, a transistor Q1, an NMOS transistor NDM1, a PMOS transistor PDM1, a PMOS transistor PDM2 and a Zener diode Z1. One end of the resistor R1 is connected to the source of the PMOS transistor PDM1, the source of the PMOS transistor PDM2 and the power supply VS. The other end of the resistor R1 is connected to the collector of the transistor Q1, the cathode of the Zener diode Z1 and the gate of the NMOS transistor NDM1. The base of the transistor Q1 is connected to the source of the NMOS transistor NDM1 and one end of the resistor R2. The drain of the NMOS transistor NDM1 is connected to the drain of the PMOS transistor PDM1, the gate of the PMOS transistor PDM1 and the gate of the PMOS transistor PDM2. The drain of the PMOS transistor PDM2 outputs a bias current Ibias2. The emitter of the transistor Q1, the anode of the Zener diode Z1 and the other end of the resistor R2 are grounded.

2. The op amp-free voltage-stabilizing startup circuit for high voltage according to claim 1, characterized in that: The NMOS tube NDM1 and the NMOS tube NDM2 are high-voltage NMOS tubes, and the PMOS tubes PDM1, PMOS tube PDM2, PMOS tube PDM3 and PMOS tube PDM4 are high-voltage PMOS tubes.

3. The op amp-free voltage-stabilizing startup circuit for high voltage according to claim 1, characterized in that: The transistor Q7 and the PMOS transistor PDM2 form a first common-emitter amplifier, the NMOS transistor NDM2 and the PMOS transistor PDM3 form a first common-source amplifier, and the PMOS transistor PDM4 and the transistor Q6, the resistor R4 and the transistor Q5 form a second common-source amplifier.

4. The op amp-less voltage-stabilizing startup circuit for high voltage according to claim 1, characterized in that: The transistors Q4 and Q5 are PNP transistors, and the transistors Q4 and Q5 form a first PNP current mirror. The transistors Q1 , Q2 , Q3 , Q6 and Q7 are NPN transistors.

5. The op amp-free voltage-stabilizing startup circuit for high voltage according to claim 1, characterized in that: The PMOS transistor PDM1 and the PMOS transistor PDM2 form a first PMOS current mirror, and the PMOS transistor PDM3 and the PMOS transistor PDM4 form a second PMOS current mirror.

6. The op amp-free voltage-stabilizing startup circuit for high voltage according to claim 1, characterized in that: The resistor R1, the resistor R2, the transistor Q1, the NMOS transistor NDM1, the PMOS transistor PDM1, the PMOS transistor PDM2 and the Zener diode Z1 form a high-voltage Wilson current source.

7. A voltage stabilizing starting method for a high voltage op amp-free voltage stabilizing starting circuit according to any one of claims 1 to 6, characterized in that The following steps are involved: The collector of the transistor Q5 is connected to the input end of a first common-emitter amplifier formed by the transistor Q7 and the PMOS transistor PDM2. The output end of the first common-emitter amplifier is connected to the input end of a first common-source amplifier formed by the NMOS transistor NDM2 and the PMOS transistor PDM3. The output end of the first common-source amplifier is connected to a second common-source amplifier formed by the high-voltage PMOS transistor PDM4, the transistor Q6, the resistor R4, and the triode Q5. The first common-emitter amplifier, the first common-source amplifier, and the second common-source amplifier form a negative feedback loop. A stable output voltage VLDO is obtained through negative feedback compensation. The first PNP current mirror formed by transistors Q4 and Q5 ensures that the currents flowing through transistors Q2 and Q3 are equal. Due to the different areas of transistors Q2 and Q3, there is a positive temperature coefficient voltage difference △VBE between the base-emitter voltages VBE of transistors Q2 and Q3. This positive temperature coefficient voltage difference △VBE divided by the zero temperature coefficient resistor R3 yields the positive temperature coefficient current Ip. The base voltage of transistor Q6 is equal to the base-emitter voltage VBE7 of transistor Q7 (with a negative temperature coefficient) plus the base-emitter voltage VBE5 of transistor Q5 (with a negative temperature coefficient) plus the voltage drop across resistor R4 (2*Ip*R4) plus the base-emitter voltage VBE6 of transistor Q6 (with a negative temperature coefficient), i.e., VBE7+VBE5+2*Ip*R4+VBE6. Therefore, the output voltage VLDO is: VLDO=(VBE7+VBE5+2*Ip*R4+VBE6)*(R6+R5) / R5 By adjusting the value of resistor R4, temperature compensation is achieved to obtain a voltage with zero temperature coefficient; The Zener diode Z2 is used to clamp the collector-emitter voltage VCE7 of the transistor Q7 and the gate-source voltage VGSN2 of the NMOS transistor NDM2 so as to be lower than the Zener diode clamping voltage VZ2, thereby preventing the collector-emitter of the transistor Q7 and the gate-source of the NMOS transistor NDM2 from being broken down. When the power supply VS starts to power on, the circuit is in a zero current state. At this time, the current on the resistor R1 is zero and the voltage drop is zero. The voltage at one end of the resistor R1 increases as VS increases. Similarly, the current on the resistor R2 is zero and the voltage drop is zero. The voltage at one end of the resistor R2 is zero. As the voltage at one end of the resistor R1 increases, the NMOS transistor NDM1 gradually turns on and generates a bias current Ibias. The bias current Ibias flows through the resistor R2 and generates a voltage drop, causing the voltage at one end of the resistor R2 to start increasing, and eventually the transistor Q1 turns on. After the circuit stabilizes, the voltage drop on the resistor R2 is equal to the base-emitter voltage VBE1 of the transistor Q1, and the bias current Ibias is equal to VBE1 / R2. The bias current Ibias The PMOS transistors PDM1 and PMOS transistors PDM2 in the first PMOS current mirror are copied and flow into the transistor Q7 to provide a bias current Ibias2 for the transistor Q7, thereby determining the base-emitter voltage VBE7 of the transistor Q7. The high-voltage Wilson current source has no degeneracy point and can start normally. After the high-voltage Wilson current source is started, the drain terminal of the PMOS transistor PDM2 in the first PMOS current mirror is high, the gate terminal of the NMOS transistor NDM2 in the first common-source amplifier is high-conducting, the gate terminal and drain terminal of the PMOS transistor PDM3 in the first common-source amplifier are low-conducting, and the gate terminal of the PMOS transistor PDM4 in the second common-source amplifier is low-conducting, thereby starting the entire circuit.

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