Voltage selection circuit, multi-stage voltage selection circuit, chip and voltage regulator

Abstract

Embodiments of the present invention provide a voltage selection circuit, a multi-stage voltage selection circuit, a chip, and a voltage regulator. The voltage selection circuit includes: a first PMOS transistor, wherein the gate of the first PMOS transistor receives a first voltage and the source receives a second voltage; a second NMOS transistor, wherein the gate of the second NMOS transistor receives the first voltage and the drain receives the second voltage; a third NMOS transistor, wherein the drain of the third NMOS transistor is connected to the source of the second NMOS transistor, the source of the third NMOS transistor is connected to the drain of the first PMOS transistor, and the transistor outputs a voltage VG; and a selection module, wherein the selection module connects the source of the third NMOS transistor to the drain of the first PMOS transistor to receive the voltage VG, and is configured to receive a first voltage and a second voltage, and select a voltage VMAX1 from the first and second voltages for output, wherein the voltage VMAX1 is also applied to the gate of the third NMOS transistor.

Description

Technical Field

[0001] The present invention relates to the field of circuit control technology, and more particularly to a voltage selection circuit, a multi-stage voltage selection circuit, a chip, and a voltage stabilizer. Background Art

[0002] When designing a digital distributed low-dropout linear regulator (DLDO), for example, it's necessary to select between different voltages, choosing the higher voltage as the driver. Given the specific design requirements of the DLDO's power supply voltage range, a voltage selection circuit is needed to effectively select the voltage output and utilize the selected voltage for driving.

[0003] Current voltage selection circuits generally enable voltage selection and driving between voltages with significant differences. However, when the voltages to be selected are relatively close, current voltage selection circuits struggle to achieve this voltage selection function. Even when a voltage is selected, it is difficult to achieve strong driving capabilities.

[0004] Therefore, there is a need for a voltage selection circuit, a multi-stage voltage selection circuit, a chip and a voltage regulator that can compare and select voltages between voltages with relatively close voltage differences and can make the selected voltage have a stronger driving capability. Summary of the Invention

[0005] According to one aspect of the present invention, a voltage selection circuit is provided, comprising: a first PMOS transistor, wherein a gate of the first PMOS transistor receives a first voltage, and a source of the first PMOS transistor receives a second voltage; a second NMOS transistor, wherein a gate of the second NMOS transistor receives the first voltage, and a drain of the second NMOS transistor receives the second voltage; a third NMOS transistor, wherein a drain of the third NMOS transistor is connected to the source of the second NMOS transistor, a source of the third NMOS transistor is connected to the drain of the first PMOS transistor, and the transistor outputs a voltage VG; and a selection module, wherein the selection module connects the source of the third NMOS transistor to the drain of the first PMOS transistor to receive the voltage VG, and is configured to receive the first voltage and the second voltage, and select a voltage VMAX1 from the first voltage and the second voltage for output, wherein the voltage VMAX1 is also applied to the gate of the third NMOS transistor.

[0006] In one example, the selection module includes: a fourth PMOS transistor, wherein the gate of the fourth PMOS transistor receives the voltage VG, and the source of the fourth PMOS transistor receives the first voltage; a fifth PMOS transistor, wherein the gate of the fifth PMOS transistor receives the first voltage, the source of the fifth PMOS transistor receives the second voltage, and the drain of the fifth PMOS transistor is connected to the drain of the fourth PMOS transistor and outputs the voltage VMAX1.

[0007] In an example, the voltage VG outputted by the source of the third NMOS transistor and the drain of the first PMOS transistor further includes a driving module, and the driving module is configured to increase leakage current at the voltage VG.

[0008] In one example, the driving module includes at least one of the following: one or more NMOS transistors; one or more resistors; and one or more current sources.

[0009] In one example, when the driving module includes multiple NMOS tubes, the multiple NMOS tubes are connected in series, the source of each stage of the NMOS tube is connected to the drain of the next stage of the NMOS tube, the drain of the first stage of the NMOS tube receives the voltage VG, the last stage of the NMOS tube is grounded, and the gate of each stage of the NMOS tube receives a high level respectively.

[0010] In an example, the high level is the first voltage or the second voltage.

[0011] In one example, when the driving module includes a plurality of resistors, the plurality of resistors are connected in series, and one end of the series resistors is connected to the voltage VG, and the other end is grounded.

[0012] According to another aspect of the present invention, a multi-stage voltage selection circuit is provided, comprising: a plurality of cascaded voltage selection circuits as described in any one of the above items, wherein the voltage selection circuit of the first stage inputs the first voltage V1 and the second voltage V2 and outputs a selected voltage VMAX1; the subsequent voltage selection circuits of the n+1th stage respectively input the voltage VMAX selected by the voltage selection circuit of the previous stage. n And the voltage to be selected V n+2 , and output from VMAX n and V n+2 The voltage VMAX selected in n+1 , where n is a positive integer greater than or equal to 1.

[0013] According to another aspect of the present invention, a chip is provided, comprising: the voltage selection circuit as described in any one of the above items, or the multi-stage voltage selection circuit as described in the above items.

[0014] According to another aspect of the present invention, a voltage regulator is provided, comprising the chip as described above.

[0015] According to the voltage selection circuit, multi-stage voltage selection circuit, chip, and voltage regulator of the embodiments of the present invention, a third NMOS transistor in the circuit, which receives voltage VMAX1 via its gate, can cause a voltage drop in VG to occur simultaneously with a voltage drop in VMAX1 due to driving a load circuit. This avoids the problem of the selection module having difficulty selecting between the first and second voltages due to VG being unable to coordinate with voltage VMAX1 during voltage selection. The embodiments of the present invention enable stable voltage comparison and selection between voltages with relatively close voltage differences, and can ensure that the selected voltage has strong driving capability.

[0016] In addition, through the further configuration of the driving module in the embodiment of the present invention, the leakage current at the voltage VG is further increased, thereby increasing the voltage difference |Vgs| between the gate-source electrodes of the second NMOS transistor and the third NMOS transistor, reducing the on-resistance in the selection module, and further increasing the driving capability of the selected voltage VMAX1. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments of the present invention or the description of the prior art. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can also be obtained based on these drawings of the embodiments of the present invention.

[0018] Figure 1 A schematic diagram of a voltage selection circuit according to an embodiment of the present invention is shown;

[0019] Figure 2 A schematic diagram showing the specific structure of a selection module in a voltage selection circuit according to an embodiment of the present invention is shown;

[0020] Figure 3 A schematic diagram of a voltage selection circuit including a driving module according to an embodiment of the present invention is shown;

[0021] Figure 4 A schematic diagram of a voltage selection circuit according to an embodiment of the present invention is shown, wherein a driving module of the voltage selection circuit includes a plurality of NMOS transistors connected in series;

[0022] Figure 5 A schematic diagram showing substrate voltage access of a MOS transistor in a voltage selection circuit according to an example of an embodiment of the present invention is shown;

[0023] Figure 6A schematic structural diagram of a multi-stage voltage selection circuit according to another example of an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0024] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0025] Before proceeding to the description of the specific embodiments below, it may be beneficial to set forth the definitions of certain words and phrases used throughout this patent document. The terms "include" and "comprising" and their derivatives mean including, but not limited to. The term "or" is inclusive, meaning and / or. The phrase "associated with..." and its derivatives mean including, included within, connected to, interconnected with, containing, contained within, connected to or connected with, coupled to or coupled with, communicable with, collaborate with, intertwined, juxtaposed, proximate, bound to or bound with, having, having an attribute of, having a relationship with, or having a relationship with, etc. The term "controller" means any device, system, or portion thereof that controls at least one operation. Such a controller may be implemented in hardware, or in a combination of hardware and software and / or firmware. The functionality associated with any particular controller may be centralized or distributed, local or remote.

[0026] The terms used herein to describe the embodiments of the present invention are not intended to limit and / or define the scope of the present invention. For example, unless otherwise defined, the technical terms or scientific terms used in this disclosure should have the same general meaning as those understood by persons of ordinary skill in the art to which the present invention belongs.

[0027] It should be understood that the terms "first," "second," and similar terms used in this disclosure do not denote any order, quantity, or importance, but are merely used to distinguish different components. Unless the context clearly indicates otherwise, the singular forms "a," "an," or "the" and similar terms do not denote a limitation of quantity, but rather denote the presence of at least one.

[0028] As used herein, any reference to "one example" or "an example," "one embodiment," or "an embodiment" means that a particular element, feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. The appearances of the phrases "in one embodiment" or "in an example" in different places in the specification are not necessarily all referring to the same embodiment.

[0029] It will be further understood that the terms "include" or "comprising" and similar words mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, but do not exclude other elements or objects. Words such as "connected" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0030] The various embodiments discussed below used to describe the principles of the present disclosure in this patent document are by way of illustration only and should not be construed in any way to limit the scope of the disclosure.

[0031] In the design process of digital distributed low-dropout linear regulators (DLDOs), the variation in the power supply voltage setting range makes it difficult to select between relatively close voltages when some circuits in the DLDO need to select a voltage to drive them.

[0032] Therefore, a voltage selection circuit and corresponding chip and voltage regulator are needed, which can not only select a higher voltage when two power supply voltages are close, but also ensure that the selected voltage has a considerable driving capability.

[0033] In addition, a multi-stage voltage selection circuit and corresponding chip and voltage regulator are also needed, which can select a voltage from multiple voltages by cascading the voltage selection circuits and perform driving operations.

[0034] Figure 1 A schematic diagram of a voltage selection circuit according to an embodiment of the present invention is shown.

[0035] like Figure 1 As shown, the voltage selection circuit 1 may include at least a first PMOS transistor M1, a second NMOS transistor M2, a third NMOS transistor M3 and a selection module N1. Specifically, Figure 1In the embodiment of the present invention, the gate of the first PMOS transistor M1 can receive a first voltage V1, and the source of the first PMOS transistor M1 can receive a second voltage V2. The gate of the second NMOS transistor M2 can receive the first voltage V1, and the drain of the second NMOS transistor can receive the second voltage V2. The drain of the third NMOS transistor M3 can be connected to the source of the second NMOS transistor, and the source of the third NMOS transistor M3 can be connected to the drain of the first PMOS transistor M1 and output a voltage VG. In addition, the selection module N1 can connect the source of the third NMOS transistor M3 to the drain of the first PMOS transistor M1 to receive the voltage VG, and can be configured to receive the first voltage V1 and the second voltage V2, and select a voltage VMAX1 from the first voltage V1 and the second voltage V2 for output. The voltage VMAX1 can also be applied to the gate of the third NMOS transistor M3.

[0036] Optionally, Figure 1 The selection module N1 in the circuit can be any circuit module capable of selecting and outputting one of the first voltage V1 and the second voltage V2 as the voltage VMAX1. In one example, when the voltage difference between V1 and V2 is large, the selection module N1 can select the higher voltage from the first voltage V1 and the second voltage V2 as the voltage VMAX1. In another example, when the voltage difference between V1 and V2 is small, the selection module N1 can stably select one of the first voltage V1 and the second voltage V2 (the first voltage V1 or the second voltage V2) as the voltage VMAX1. Considering that the first voltage V1 and the second voltage V2 are very close, the voltage selection requirements of the voltage selection circuit can be met as long as the selection module N1 can stably select one of the voltages (the first voltage V1 or the second voltage V2) and ensure that it has strong load driving capability.

[0037] In an example of the present invention, the selection module N1 may be composed of two MOS transistors. Figure 2 FIG. 1 shows a schematic diagram of the specific structure of a selection module in a voltage selection circuit according to an embodiment of the present invention. Figure 2 As shown, the selection module N1 may include a fourth PMOS transistor M4, a gate of which may receive the voltage VG, and a source of which may receive the first voltage V1. Furthermore, the selection module N1 may further include a fifth PMOS transistor M5, a gate of which may receive the first voltage V1, a source of which may receive the second voltage V2, and a drain of which may be connected to the drain of the fourth PMOS transistor M4 and output the voltage VMAX1.

[0038] Figure 2 The specific structure of the selection module N1 shown is only an example in the embodiment of the present invention. In addition, in another example, Figure 2 The source of the fourth PMOS transistor M4 of the selection module N1 can receive the second voltage V2, while the gate of the fifth PMOS transistor M5 can receive the second voltage V2 and the source can receive the first voltage V1. In practical applications, any specific structural form of the selection module that can perform voltage comparison and selection can be adopted according to specific needs, and there is no limitation here. Figure 2 In the embodiment, the number of components, connection mode and input voltage value of the selection module N1 can be changed according to actual needs, and other components capable of voltage selection can also be used to implement a specific voltage selection function.

[0039] The following targets Figure 2 The structure of the voltage selection circuit shown in FIG. 1 is used to illustrate the specific voltage selection working mode of the voltage selection circuit of this example. Figure 2 In the voltage selection circuit shown, the voltage difference between V1 and V2 can be large (for example, it can be expressed as |V1-V2|>V th , where V th is the threshold voltage) or the voltage difference between V1 and V2 is relatively close (for example, it can be expressed as |V1-V2|≤V th ), the selection function of the voltage VMAX1 in V1 and V2 is realized respectively.

[0040] In one example, when the voltage difference between V1 and V2 is large, it can be expressed as V1-V2>V th When V1 is smaller than V2, V2-V1>V th Optionally, when V1-V2>V th When the voltage VG received by the gate of the fourth PMOS transistor M4 in the selection module N1 is the second voltage V2, the fourth PMOS transistor M4 is turned on, while the fifth PMOS transistor M5 is turned off, and the output voltage VMAX1 is the first voltage V1.

[0041] In addition, optionally, when V2-V1>V thWhen , the first PMOS transistor M1 is turned on, causing VG to be the second voltage V2. Considering that the voltages across the second NMOS transistor M2 and the third NMOS transistor M3 connected in series are both the second voltage V2, it can be assumed that the second NMOS transistor M2 and the third NMOS transistor M3 are both turned off, and the gate voltage of the fourth PMOS transistor M4 in the input selection module N1 is the second voltage V2. At this time, the fourth PMOS transistor M4 is turned off, while the fifth PMOS transistor M5 is turned on, and the output voltage VMAX1 is the second voltage V2.

[0042] In another example, consider that the voltage difference between V1 and V2 is relatively close (expressed as |V1-V2|≤V th ) At this time, since the voltage difference between V1 and V2 is very small, it is less than the threshold voltage V of the first PMOS tube M1. th , the first PMOS transistor M1 is in the off state. For the second NMOS transistor M2, since the first PMOS transistor M1 is in the off state, the source of the second NMOS transistor M2, namely VG, is floating, and only a very small leakage current is present. At this time, the second NMOS transistor M2 is in the deep subthreshold region, and the voltage of the source of the second NMOS transistor M2, namely VG, is equal to V1-|Vgs2|, where |Vgs2| is the gate-source voltage difference of the second NMOS transistor M2 at this time. Since M2 is in the deep subthreshold region at this time, |Vgs2| is less than the threshold voltage V when the transistor is normally turned on. th In the case where the source of the second NMOS transistor M2 is directly connected to the drain of the first PMOS transistor M1 without the third NMOS transistor M3, the voltage VG of the second NMOS transistor M2 will be equal to (V1-|Vgs2|) due to the leakage current. Since the value of |Vgs2| is less than the threshold voltage V when the transistor is normally turned on, th At this time, the voltage between the gate and source of the fourth PMOS tube M4 |Vgs| is less than the threshold voltage V th , thus being in an approximately cut-off state, with poor driving capability, and the output VMAX1 can easily drop due to driving a large load.

[0043] However, by introducing the third NMOS transistor M3, when the voltage VMAX1 output by the selection module N1 drives the load circuit and generates a corresponding voltage drop, due to the effect of leakage current, the voltage VG will become approximately equal to (VMAX1-|Vgs3|), where |Vgs3| is the gate-source voltage difference of the third NMOS transistor M3 at this time. Subsequently, the voltage VG is input to the gate of the fourth PMOS transistor M4, so that when the output voltage VMAX1 drops, the gate voltage of the fourth PMOS transistor M4 also drops, thereby increasing the voltage difference |Vgs| between the gate and source of the fourth PMOS transistor M4, allowing the fourth PMOS transistor M4 to conduct, thereby increasing the driving capability.

[0044] In this case, even when the output voltage VMAX1 is subjected to a heavy load, voltage VMAX1 can stably output a voltage slightly lower than and approximately equal to first voltage V1. By stably selecting an approximate value of first voltage V1 from first voltage V1 and second voltage V2, the voltage selection output result of voltage selection circuit 1 can be guaranteed, and the selected voltage can be guaranteed to have strong driving capability.

[0045] Of course, the above Figure 2 The specific structure and voltage selection method of the selection module N1 in the voltage selection circuit 1 shown in the figure are only examples. In other examples, the output result of the voltage selection of the voltage selection circuit 1 can also be guaranteed by, for example, stably selecting the second voltage V2 from the first voltage V1 and the second voltage V2, and it can also be ensured that the selected voltage has a strong driving capability.

[0046] According to another example of the embodiment of the present invention, the voltage selection circuit 1 may further include a driving module N2. Figure 3 FIG. 1 shows a schematic diagram of a voltage selection circuit including a driving module according to an embodiment of the present invention. Figure 3 As shown, the driving module N2 can be set at the voltage VG output by the source of the third NMOS tube and the drain of the first PMOS tube. The driving module N2 can be used to increase the leakage current at the voltage VG, so that when the voltage VMAX1 drives the load circuit to generate a voltage drop, the voltage VG can be more quickly and stably reduced to (VMAX1-V th ), shortening the time interval during the voltage drop. The specific value of the leakage current provided by the driver module N2 can be flexibly designed by those skilled in the art based on specific needs. In one example, the leakage current provided by the driver module N2 can be approximately several hundred nA. This leakage current can further increase the gate-source voltage difference |Vgs| of the fourth PMOS transistor M4, reducing the on-resistance of the fourth PMOS transistor M4, thereby further increasing the drive capability of the fourth PMOS transistor M4 and bringing the output voltage VMAX1 closer to V1.

[0047] Optionally, the driver module N2 may include at least one of the following: one or more NMOS transistors; one or more resistors; or one or more current sources. The above-mentioned specific configuration of the driver module N2 is merely an example. In practical applications, any configuration that can provide leakage current may be adopted, without limitation.

[0048] In an example, the driving module N2 may include a plurality of NMOS transistors connected in series. Figure 4FIG. 1 shows a schematic diagram of a voltage selection circuit according to an embodiment of the present invention, wherein a driving module of the voltage selection circuit includes a plurality of NMOS transistors MM1-MMn connected in series. Figure 4 As shown, the multiple NMOS tubes MM1-MMn are connected in series, the source of each stage NMOS tube is connected to the drain of the next stage NMOS tube, the drain of the first stage NMOS tube MM1 receives the voltage VG, and the last stage NMOS tube MMn is grounded V SS , the gate of each stage of NMOS transistors receives a high level V. Optionally, the high level V received by the gates of these NMOS transistors can be any one of the first voltage V1 and the second voltage V2. Of course, optionally, the high level V can also be other high levels with reasonable values, which is not limited here.

[0049] In another example, when the driving module includes a resistor, one end of the resistor can be connected to the voltage VG, and the other end can be connected to the ground V SS When the driving module includes multiple resistors, the multiple resistors can be connected in series, and one end of the series resistor can be connected to the voltage VG, and the other end can be grounded V SS .

[0050] In another example, when the driving module includes one or more current sources, the current direction provided by the current source can flow out from the voltage VG, and the one or more current sources can be used to provide leakage current to promote the voltage VG to drop to (VMAX1-V th ).

[0051] According to an embodiment of the present invention, when the voltage selection circuit is applied to a chip, the substrates of the respective MOS transistors in the voltage selection circuit need to meet different voltage access modes. Figure 5 FIG. 1 is a schematic diagram showing the substrate voltage access of a MOS tube in a voltage selection circuit according to an example of an embodiment of the present invention. Figure 5 As shown, the substrate of the NMOS tube in the voltage selection circuit 1 can be grounded V SS , and the substrate of the PMOS transistor can receive the highest voltage among the source, gate, and drain of the PMOS transistor to avoid leakage. Therefore, the substrate of the first PMOS transistor M1 in the voltage selection circuit 1 can receive the second voltage V2, and the substrates of the fourth PMOS transistor M4 and the fifth PMOS transistor M5 can receive the voltage VMAX1. The substrates of the second NMOS transistor M2, the third NMOS transistor M3, and the series-connected NMOS transistors MM1-MMn in the voltage selection circuit 1 can be grounded to V SS .

[0052] According to an embodiment of the present invention, the voltage selection circuit can utilize a third NMOS transistor in the circuit, which receives voltage VMAX1 via its gate, to cause a corresponding voltage drop on VG when voltage VMAX1 generates a voltage drop due to driving a load circuit. This avoids the problem of the selection module having difficulty selecting between the first and second voltages due to VG not being able to coordinate with voltage VMAX1 during voltage selection. This embodiment of the present invention enables stable voltage comparison and selection between voltages with relatively close voltage differences, and ensures that the selected voltage has strong driving capability.

[0053] In addition, through the further configuration of the driving module in the embodiment of the present invention, the leakage current at the voltage VG is further increased, thereby increasing the voltage difference |Vgs| between the gate-source electrodes of the second NMOS transistor and the third NMOS transistor, reducing the on-resistance in the selection module, and further increasing the driving capability of the selected voltage VMAX1.

[0054] In the embodiment according to the present invention Figure 1-Figure 5 Based on the structural design of the voltage selection circuit shown, when it is desired to further perform voltage selection and stable load driving from multiple input voltages, multiple voltage selection circuits can be cascaded to obtain a multi-stage voltage selection circuit. Figure 6 FIG. 2 shows a schematic diagram of a multi-stage voltage selection circuit according to another example of an embodiment of the present invention. Figure 6 As shown, the multi-stage voltage selection circuit may include a plurality of the aforementioned voltage selection circuits connected in cascade, and its specific working principle is as described above and will not be repeated here.

[0055] In the embodiment of the present invention, the voltage selection circuit of the first stage inputs the first voltage V1 and the second voltage V2, and outputs the selected voltage VMAX1; each subsequent voltage selection circuit of the n+1th stage can respectively input the voltage VMAX selected by the voltage selection circuit of the previous stage. n And the voltage to be selected V n+2 , and output from VMAX n and V n+2 The voltage VMAX selected in n+1 , where n is a positive integer greater than or equal to 1. Figure 6 In the example shown, optionally, when the two voltages input to a voltage selection circuit of a certain level are close to each other, the voltage can be stably selected from VMAX. n and V n+2 Select a voltage (VMAX n or V n+2 ) as voltage VMAX n+1 , and not necessarily a relatively high voltage.

[0056] The multi-stage voltage selection circuit according to an embodiment of the present invention can avoid the problem of difficulty in selecting a voltage from among the voltages to be selected during voltage selection by designing cascaded voltage selection circuits. This embodiment of the present invention can perform stable voltage comparison and selection between voltages with relatively close voltage differences, and can ensure that the selected voltage has strong driving capabilities, making it suitable for various subsequent application scenarios.

[0057] According to another embodiment of the present invention, a chip is provided, which includes the voltage selection circuit as described above, or the multi-stage voltage selection circuit as described above.

[0058] According to another embodiment of the present invention, a voltage regulator is provided, comprising the chip described above. The voltage regulator in the embodiment of the present invention may be, for example, a digital distributed low dropout linear regulator (DLDO).

[0059] Although the present invention has been described in detail with respect to various specific example embodiments thereof, each example is provided by way of explanation rather than limitation of the present invention. Those skilled in the art, upon obtaining an understanding of the foregoing, can readily make variations, changes, and equivalents of such embodiments. Therefore, the present invention does not exclude the inclusion of such modifications, changes, and / or additions to the present invention that would be apparent to those of ordinary skill in the art. For example, a feature illustrated or described as part of one embodiment may be used in conjunction with another embodiment to produce yet another embodiment. Therefore, it is intended that the present invention cover such variations, changes, and equivalents.

[0060] Specifically, although the figures of the present disclosure describe steps performed in a specific order for the purposes of illustration and discussion, the method of the present disclosure is not limited to the order or arrangement of the specific illustrations. The various steps of the above method can be omitted, rearranged, combined and / or adjusted in various ways without departing from the scope of the present disclosure.

[0061] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It should also be understood that terms such as those defined in common dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or highly formal sense, unless explicitly defined as such herein.

[0062] The above is an illustration of the present disclosure and should not be considered as a limitation thereof. Although several exemplary embodiments of the present disclosure have been described, it will be readily understood by those skilled in the art that many modifications may be made to the exemplary embodiments without departing from the novel teachings and advantages of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the present disclosure as defined by the claims. It should be understood that the above is an illustration of the present disclosure and should not be considered as limited to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims. The present disclosure is defined by the claims and their equivalents.

Claims

1. A voltage selection circuit comprising: a first PMOS transistor, wherein a gate of the first PMOS transistor receives a first voltage, and a source of the first PMOS transistor receives a second voltage; a second NMOS transistor, wherein a gate of the second NMOS transistor receives the first voltage, and a drain of the second NMOS transistor receives the second voltage; a third NMOS transistor, wherein the drain of the third NMOS transistor is connected to the source of the second NMOS transistor, the source of the third NMOS transistor is connected to the drain of the first PMOS transistor and outputs a voltage VG; a selection module, wherein the selection module connects the source of the third NMOS transistor and the drain of the first PMOS transistor to receive the voltage VG, and is configured to receive the first voltage and the second voltage, and select a voltage VMAX1 from the first voltage and the second voltage for output, and the voltage VMAX1 is also applied to the gate of the third NMOS transistor.

2. The voltage selection circuit according to claim 1, wherein: The selection module includes: a fourth PMOS transistor, wherein a gate of the fourth PMOS transistor receives the voltage VG, and a source of the fourth PMOS transistor receives the first voltage; A fifth PMOS transistor, wherein a gate of the fifth PMOS transistor receives the first voltage, a source of the fifth PMOS transistor receives the second voltage, a drain of the fifth PMOS transistor is connected to the drain of the fourth PMOS transistor and outputs the voltage VMAX1.

3. The voltage selection circuit according to claim 1, wherein: A driving module is further included at the voltage VG output by the source of the third NMOS transistor and the drain of the first PMOS transistor, and the driving module is used to increase the leakage current at the voltage VG.

4. The voltage selection circuit according to claim 3, wherein: The driving module includes at least one of the following: One or more NMOS tubes; one or more resistors; One or more current sources.

5. The voltage selection circuit according to claim 4, wherein: When the driving module includes multiple NMOS tubes, the multiple NMOS tubes are connected in series, the source of each stage of the NMOS tube is connected to the drain of the next stage of the NMOS tube, the drain of the first stage of the NMOS tube receives the voltage VG, the last stage of the NMOS tube is grounded, and the gate of each stage of the NMOS tube receives a high level respectively.

6. The voltage selection circuit according to claim 5, wherein: The high level is the first voltage or the second voltage.

7. The voltage selection circuit according to claim 4, wherein: When the driving module includes a plurality of resistors, the plurality of resistors are connected in series, one end of the series resistors is connected to the voltage VG, and the other end is grounded.

8. A multi-stage voltage selection circuit comprising: A plurality of voltage selection circuits according to any one of claims 1 to 7 are cascaded, wherein the voltage selection circuit of the first stage inputs the first voltage V1 and the second voltage V2 and outputs a selected voltage VMAX1; and the subsequent voltage selection circuits of the n+1th stage respectively input the voltage VMAX selected by the voltage selection circuit of the previous stage. n And the voltage to be selected V n+2 , and output from VMAX n and V n+2 The voltage VMAX selected in n+1 , where n is a positive integer greater than or equal to 1.

9. A chip comprising: The voltage selection circuit according to any one of claims 1 to 7, or the multi-stage voltage selection circuit according to claim 8.

10. A voltage regulator comprising the chip according to claim 9.

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