Bank address decoder and memory

Abstract

An embodiment of the present disclosure provides a memory body address decoder and a semiconductor memory, wherein the memory body address decoder includes: a command address processing circuit, for determining a first operation address signal based on a first command signal, a second command signal, a first undecoded address signal, and a second undecoded address signal; wherein the first undecoded address signal is an address signal corresponding to the first command signal, and the second undecoded address signal is an address signal corresponding to the second command signal; an address decoding circuit, connected to the command address processing circuit and receiving the first operation address signal, the address decoding circuit being used to decode the first operation address signal to obtain a second operation address signal; a command address activation circuit, connected to the address decoding circuit and receiving the second operation address signal, the command address activation circuit being used to generate a memory body activation address signal based on information of the first command signal, the second command signal, and the second operation address signal.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of memory, and in particular to a memory address decoder and a memory. Background Art

[0002] Under the current technology framework, memory operations require corresponding commands, and the address decoding logic for each command is processed independently. Subsequently, each command is used as a clock signal to sample and latch the decoded memory bank address, thereby generating an enable signal that determines whether the memory bank is on or off. However, this practice of configuring separate address decoding circuits for each command type inevitably leads to significant consumption of chip area, which is contrary to the trend of pursuing high integration and compact layout in modern integrated circuit design, and thus constitutes a potential obstacle to improving overall system performance and efficiency.

[0003] Therefore, exploring a new circuit that can not only meet the needs of command address decoding but also significantly reduce area consumption is of great significance for improving the integration and overall performance of the storage system. Summary of the Invention

[0004] The embodiments of the present application provide a memory address decoder and a memory, which at least help to solve the problem of excessive area occupied by the address decoding circuit.

[0005] According to some embodiments of the present application, an embodiment of the present application provides a memory address decoder, characterized in that it includes a command address processing circuit, an address decoding circuit and a command address activation circuit, wherein:

[0006] The command address processing circuit is configured to determine a first operation address signal based on a first command signal, a second command signal, a first undecoded address signal, and a second undecoded address signal; wherein the first undecoded address signal is an address signal corresponding to the first command signal, and the second undecoded address signal is an address signal corresponding to the second command signal;

[0007] The address decoding circuit is connected to the command address processing circuit and receives the first operation address signal, and the address decoding circuit is used to decode the first operation address signal to obtain a second operation address signal;

[0008] The command address activation circuit is connected to the address decoding circuit and receives the second operation address signal. The command address activation circuit is used to generate a memory bank activation address signal according to the information of the first command signal, the second command signal and the second operation address signal.

[0009] In some embodiments, the command address processing circuit includes a command processing circuit and a command address latch circuit, wherein the command processing circuit is used to narrow the effective level width of the first command signal according to the first command signal and the second command signal to generate a first narrowed command signal; wherein the effective level width of the first narrowed command signal is narrower than the first command signal; the command address latch circuit is connected to the command processing circuit and receives the first narrowed command signal, and is used to generate a first operation address signal according to the first narrowed command signal, the second command signal, the first undecoded address signal and the second undecoded address signal.

[0010] In some embodiments, the command processing circuit includes a first inverter and a first NOR gate, the input end of the first inverter receives the first command signal, the first input end of the first NOR gate is connected to the output end of the first inverter, the second input end of the first NOR gate receives the second command signal, and the output end of the first NOR gate outputs the first narrowing command signal.

[0011] In some embodiments, the command address latch circuit includes a first gated inverter and a second gated inverter; wherein, the control end of the first gated inverter receives the first narrowed command signal, and the input end of the first gated inverter receives the first undecoded address signal; the control end of the second gated inverter receives the second command signal, and the input end of the second gated inverter receives the second undecoded address signal; the output end of the first gated inverter and the output end of the second gated inverter are connected to the input end of the second inverter, and the output end of the second inverter outputs the first operation address signal.

[0012] In some embodiments, the command address latch circuit further includes a third inverter and a third gated inverter; wherein, the input end of the third inverter is connected to the output end of the second inverter, the output end of the third inverter is connected to the input end of the third gated inverter, the control end of the third gated inverter receives the first narrowing command signal and the second command signal, and the output end of the third gated inverter is connected to the input end of the third inverter.

[0013] In some embodiments, the command address activation circuit is connected to the command address processing circuit and the address decoding circuit and receives the first narrowed command signal and the second operation address signal. The command address activation circuit is used to perform sampling processing and logical operation processing on the first narrowed command signal and the second command signal according to the second operation address signal to generate a storage body activation address signal.

[0014] In some embodiments, the command address activation circuit includes a first trigger, a second trigger and a first latch, wherein the data input terminal of the first trigger receives the first narrowed command signal, the clock input terminal of the first trigger receives the second operation address signal, and the data output terminal of the first trigger is connected to the first input terminal of the first latch; the data input terminal of the second trigger receives the second command signal, the clock input terminal of the second trigger receives the second operation address signal, and the data output terminal of the second trigger is connected to the second input terminal of the first latch; and the output terminal of the first latch outputs the storage body activation address signal.

[0015] In some embodiments, the data output terminals of the first trigger and the second trigger both include a data positive output terminal and a data negative output terminal, the data negative output terminal of the first trigger is connected to the first input terminal of the first latch; the data negative output terminal of the second trigger is connected to the second input terminal of the first latch; the first latch includes two NAND gates.

[0016] In some embodiments, the data output terminals of the first trigger and the second trigger both include a data positive output terminal and a data negative output terminal, and the data negative output terminal of the first trigger is connected to the first input terminal of the first latch; the data positive output terminal of the second trigger is connected to the first input terminal of the second NOR gate, the second input terminal of the second NOR gate receives the full storage body control signal, and the output terminal of the second NOR gate is connected to the second input terminal of the first latch; the first latch includes two NAND gates.

[0017] According to some embodiments of the present application, on the other hand, an embodiment of the present application further provides a memory, which includes a storage body address decoder and a storage body as described in any of the aforementioned embodiments, and the storage body is connected to the storage body address decoder for activating the corresponding storage body according to the storage body activation address signal.

[0018] The technical solution provided by the embodiments of the present application has at least the following advantages:

[0019] The present application provides a memory address decoder. By setting a command address processing circuit, a first operation address signal is determined according to a first command signal and a second command signal, so that an address decoding circuit can be used to sequentially decode the addresses corresponding to the first command signal and the second command signal to obtain a second operation address signal; and a command address activation circuit is used to process the second operation address using information of the first command signal and the second command signal to generate a corresponding memory activation address signal to determine whether the corresponding memory address is turned on. This allows the memory address decoders of different types of commands in the memory to be reused through control logic, effectively reducing the layout area. In addition, due to the addition of a latch structure, the corresponding memory address information is latched and output according to the command information, which can avoid invalid signal flipping and reduce dynamic power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] One or more embodiments are exemplarily described by the pictures in the corresponding drawings. These exemplifications do not constitute limitations on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute proportional limitations.

[0021] Figure 1 A schematic structural diagram of a memory address decoder provided in an embodiment of the present disclosure.

[0022] Figure 2 A waveform diagram of the overlap of a first command signal and a second command signal provided in an embodiment of the present disclosure.

[0023] Figure 3 A schematic diagram of the circuit structure of a command address processing circuit provided in an embodiment of the present disclosure.

[0024] Figure 4 A waveform diagram of a first narrowing command signal and a second command signal provided in an embodiment of the present disclosure.

[0025] Figure 5 A schematic diagram of the circuit structure of another command address processing circuit provided in an embodiment of the present disclosure.

[0026] Figure 6 A schematic diagram of the circuit structure of a third gated inverter provided in an embodiment of the present disclosure.

[0027] Figure 7 A schematic diagram of the circuit structure of another command address processing circuit provided in an embodiment of the present disclosure.

[0028] Figure 8 A schematic diagram of the circuit structure of a command address activation circuit provided in an embodiment of the present disclosure.

[0029] Figure 9A detailed circuit structure diagram of a command address activation circuit provided in an embodiment of the present disclosure.

[0030] Figure 10 A detailed circuit structure diagram of another command address activation circuit provided in an embodiment of the present disclosure.

[0031] Figure 11 A schematic diagram of a memory provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0032] Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily practice the present invention. As will be appreciated by those skilled in the art, the described embodiments may be modified in various ways, all without departing from the spirit or scope of the present invention. For example, the exemplary embodiments provided herein are considered to be capable of being combined with each other in whole or in part to achieve this. Specifically, an element described in a particular exemplary embodiment, even if not described in another exemplary embodiment, may be understood as a description related to another exemplary embodiment, unless a contrary or contradictory description is provided therein.

[0033] Throughout this specification, when any part is referred to as being “connected” to another part, this includes both the case where the part and the other part are “indirectly connected” to each other due to another part being interposed therebetween, and the case where the part and the other part are “directly connected” to each other. For example, it should be understood that when an element is referred to as being “connected” or “coupled” or “on” another element, it can be directly connected or coupled to or on the other element, or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, or as being “in contact with” or “in contact with” another element, there are no intervening elements at the point of contact.

[0034] Furthermore, "electrically connected" conceptually includes both physical connections and physical disconnections. It will be understood that when terms such as "first" and "second" are used to refer to an element, the element is not limited thereto. They may serve only to distinguish the element from other elements and may not limit the order or importance of the elements. In some cases, a first element may be referred to as a second element without departing from the scope of the claims set forth herein. Similarly, a second element may also be referred to as a first element.

[0035] Each operation of the memory (such as activation, refresh, precharge, read, write, etc.) requires receiving the corresponding command and address information before it can be performed. In the prior art, the address decoding corresponding to the commands of various memory operations is performed separately. Subsequently, each type of command is used as a clock signal to sample and latch the decoded memory address, and then generate an enable signal that determines the open or closed state of the memory. For example, for the activation command (Activate) and precharge command (Pre-charge), the activation command has a set of address decoding circuits, and the precharge command has a set of address decoding circuits. When the activation command or precharge command is received, the address decoding circuit performs address decoding respectively. This consumes a large amount of area.

[0036] Therefore, exploring a new circuit that can not only meet the needs of command address decoding but also significantly reduce area consumption is of great significance for improving the integration and overall performance of the storage system.

[0037] The present application provides a memory bank address decoder, including a command address processing circuit, an address decoding circuit, and a command address activation circuit, wherein the command address processing circuit is used to determine a first operation address signal based on a first command signal, a second command signal, a first undecoded address signal, and a second undecoded address signal; wherein the first undecoded address signal is the address signal corresponding to the first command signal, and the second undecoded address signal is the address signal corresponding to the second command signal; the address decoding circuit is connected to the command address processing circuit and receives the first operation address signal, and the address decoding circuit is used to decode the first operation address signal to obtain a second operation address signal; the command address activation circuit is connected to the address decoding circuit and receives the second operation address signal, and the command address activation circuit is used to generate a memory bank activation address signal based on the information of the first command signal, the second command signal, and the second operation address signal. Through the command address processing circuit, the first command signal and the second command signal can reuse the same address decoding circuit, effectively reducing the chip area. In addition, due to the addition of a latch structure, the corresponding memory bank address information is latched and output according to the command information, which can avoid invalid signal flipping and reduce dynamic power consumption.

[0038] The following detailed description of the various embodiments of the present application is provided in conjunction with the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present application to facilitate a better understanding of the present application. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the present application can still be implemented.

[0039] Figure 1This is a schematic diagram of the structure of a memory address decoder provided by an embodiment of the present disclosure. Figure 1 The memory bank address decoder 10 includes a command address processing circuit 110, an address decoding circuit 120 and a command address activation circuit 130, wherein:

[0040] The command address processing circuit 110 is configured to determine a first operation address signal OP1<4:0> based on a first command signal CMD_ACT, a second command signal CMD_PRE, a first undecoded address signal ACT_BA<4:0>, and a second undecoded address signal PRE_BA<4:0>; wherein the first undecoded address signal ACT_BA<4:0> is an address signal for the operation corresponding to the first command signal CMD_ACT, and the second undecoded address signal PRE_BA<4:0> is an address signal for the operation corresponding to the second command signal CMD_PRE;

[0041] The address decoding circuit 120 is connected to the command address processing circuit 110 and receives the first operation address signal OP1<4:0>. The address decoding circuit 120 is used to decode the first operation address signal OP1<4:0> to obtain the second operation address signal OP2<31:0>;

[0042] The command address activation circuit 130 is connected to the address decoding circuit 120 and receives the second operation address signal OP2<31:0>. The command address activation circuit 130 is used to generate a storage body activation address signal OP3<31:0> based on the information of the first command signal CMD_ACT, the second command signal CMD_PRE and the second operation address signal OP2<31:0>.

[0043] Among them, the first command signal and the second command signal are commands for performing different types of operations on the memory. For example, the first command signal can be an activation command (Activate, ACT), and the second command signal can be a pre-charge command (Pre-charge, PRE), a read command (Read), a write command (Write), a read command with automatic pre-charge (Read with AutoPre-charge, RAP), a read command with automatic pre-charge (WAP), etc. For ease of description, the above and below text uses the activation command as the first command signal (CMD_ACT) and the pre-charge command as the second command signal (CMD_PRE) as an example. The first command signal and the second command signal are decoded command signals. For example, the first command signal CMD_ACT is a pulse signal with an effective level width of 2 system clock cycles (2T), and the second command signal CMD_PRE is a pulse signal with an effective level pulse width of 1 system clock cycle (1T). Among them, the system clock cycle refers to the period of the system clock ck. The effective level can be a high level or a low level. This article uses the effective level as an example of a high level.

[0044] The command address processing circuit 110 controls the output sequence of the first undecoded address signal ACT_BA<4:0> and the second undecoded address signal PRE_BA<4:0> of the corresponding operation by adopting the decoded first command signal CMD_ACT and the second command signal CMD_PRE as control signals, and sequentially outputs the address of the corresponding operation according to the timing of receiving the first command signal CMD_ACT and the second command signal CMD_PRE, thereby realizing the selection of the storage body address under different commands, so that the address decoding circuit 120 only receives and decodes the address corresponding to the command under different command timings, thereby realizing the multiplexing of the address decoding circuit of the storage body.

[0045] That is, if the command address processing circuit 110 first receives the first command signal CMD_ACT and then receives the second command signal CMD_PRE, the command address processing circuit 110 processes the first undecoded address signal ACT_BA<4:0> and the second undecoded address signal PRE_BA<4:0> in sequence, and outputs the first undecoded address signal ACT_BA<4:0> and the second undecoded address signal PRE_BA<4:0> in sequence as the first operation address signal OP1<4:0>.

[0046] That is, the first operation address signals OP1<4:0> are the address signals corresponding to the first command signal CMD_ACT or the second command signal CMD_PRE that is at an active level. When the first command signal CMD_ACT is at an active level, the first operation address signals OP1<4:0> are the address signals corresponding to the first command signal CMD_ACT; when the second command signal CMD_PRE is at an active level, the first operation address signals OP1<4:0> are the address signals corresponding to the second command signal CMD_PRE.

[0047] In some embodiments, a conventional decoder is used to form the address decoding circuit 120. For example, in the case of receiving a six-bit first operation address signal OP1<4:0>, the address decoding circuit 120 can use a 5-32 binary decoder to decode the input 5-bit data into 32-bit data with only one bit in a valid level state to obtain the second operation address signal OP2<31:0>.

[0048] The command address activation circuit 130 is connected to the address decoding circuit 120 and receives the second operation address signal OP2<4:0>. The command address activation circuit 130 is used to generate a storage body activation address signal OP3<31:0> based on the information of the first command signal CMD_ACT, the second command signal CMD_PRE and the second operation address signal OP2<31:0>.

[0049] The second operation address signal OP2<31:0> includes a decoded address signal corresponding to the timing of the first command signal CMD_ACT and the second command signal CMD_PRE. The command address activation circuit 130 receives the second operation address signal OP2<4:0> and processes these signals according to the information of the first command signal CMD_ACT, the second command signal CMD_PRE and the second operation address signal OP2<31:0>. At the moment of the timing operation of the first command signal CMD_ACT and the second command signal CMD_PRE, the corresponding address signal is processed to generate a corresponding storage body activation address signal, thereby turning on or off the storage body.

[0050] Thus, the circuit shown in this embodiment can reuse the bank address decoding circuits for different commands. Furthermore, for the addresses corresponding to different commands, corresponding bank activation address signals are generated based on the command timing and address information, thereby avoiding invalid signal flips and reducing dynamic power consumption.

[0051] Since the first command signal CMD_ACT is a pulse signal with a 2T effective level width and the second command signal CMD_PRE is a pulse signal with a 1T effective level pulse width, in some operating scenarios, an activation command may be followed by a pre-charge command, resulting in overlap of the first command signal and the second command signal. Figure 2 FIG. 1 shows a waveform diagram of the overlap of the first command signal CMD_ACT and the second command signal CMD_PRE. Figure 2 As shown, in the first cycle (first 1T) of the first command signal CMD_ACT, the address corresponding to the activation command can be decoded and selected. However, in the second cycle (second 1T) of the first command signal CMD_ACT, since the first command signal CMD_ACT has not yet ended and the second command signal CMD_PRE has been received, a signal conflict occurs, resulting in the inability to correctly decode and select the corresponding address.

[0052] In this regard, Figure 3 The present invention provides a circuit diagram of a command address processing circuit according to an embodiment of the present invention. The command address processing circuit 110 includes a command processing circuit 111 and a command address latch circuit 112. The command processing circuit 111 is configured to narrow the effective level width of the first command signal CMD_ACT based on the first command signal CMD_ACT and the second command signal CMD_PRE to generate a first narrowed command signal CMD_ACTD. The effective level width of the first narrowed command signal CMD_ACTD is narrower than that of the first command signal CMD_ACT.

[0053] The command address latch circuit 112 is connected to the command processing circuit 111 and receives the first narrowed command signal CMD_ACTD, and is used to generate a first operation address signal OP1<4:0> according to the first narrowed command signal CMD_ACTD, the second command signal CMD_PRE, the first undecoded address signal ACT_BA<4:0> and the second undecoded address signal PRE_BA<4:0>.

[0054] That is, the command address processing circuit 110 processes the first command signal, the second command signal, the first undecoded address signal, and the second undecoded address signal, and outputs a first operation address signal corresponding to the first command signal and the second command signal that is at an active level. Furthermore, the second command signal has a higher priority than the first command signal. When the first command signal is at an active level, the first operation address signal is the address signal corresponding to the first command signal; when the second command signal is at an active level, the first operation address signal is the address signal corresponding to the second command signal; and when the first command signal and the second command signal are both at active levels, the first operation address signal is the address signal corresponding to the second command signal.

[0055] The command processing circuit narrows the effective level width of the first command signal based on the second command signal, so that the effective level width of the first command signal is narrowed, thereby avoiding conflict between the first command signal and the second command signal.

[0056] After the narrowing, when the second command signal is at the active level, the first command signal is at the inactive level. Figure 4 A schematic diagram of the waveforms of the first narrowed command signal CMD_ACTD and the second command signal CMD_PRE is shown. The first narrowed command signal CMD_ACTD is at an active level during the first cycle, and the second command signal CMD_PRE is at an active level during the second cycle. Thus, the command address latch circuit 112 can output the first undecoded address signal ACT_BA<4:0> during the first cycle and the second undecoded address signal PRE_BA<4:0> during the second cycle. The address decoding circuit can decode the memory bank address corresponding to the first command signal during the first cycle and decode the memory bank address corresponding to the second command signal during the second cycle.

[0057] Therefore, the command address processing circuit 110 can accurately respond to the first command signal and the second command signal in various situations, and output a correct first operation address signal, so that the memory bank address decoder can correctly perform decoding.

[0058] In some embodiments, as Figure 3 As shown, the command processing circuit 111 includes a first inverter INV1 and a first NOR gate NOR1, the input end of the first inverter INV1 receives the first command signal CMD_ACT, the first input end of the first NOR gate NOR1 is connected to the output end of the first inverter INV1, the second input end of the first NOR gate NOR1 receives the second command signal CMD_PRE, and the output end of the first NOR gate NOR1 outputs the first narrowed command signal CMD_ACTD.

[0059] Therefore, by narrowing the first command signal CMD_ACT through the second command signal CMD_PRE, the connection between the first command signal CMD_ACT and the second command signal CMD_PRE can be accurately achieved.

[0060] In some embodiments, as Figure 3 As shown, the command address latch circuit 112 includes a first gated inverter GINV1 and a second gated inverter GINV2; wherein, the control end of the first gated inverter GINV1 receives the first narrowed command signal CMD_ACTD, and the input end of the first gated inverter GINV1 receives the first undecoded address signal ACT_BA<4:0>; the control end of the second gated inverter GINV2 receives the second command signal CMD_PRE, and the input end of the second gated inverter GINV2 receives the second undecoded address signal PRE_BA<4:0>; the output end of the first gated inverter GINV1 and the output end of the second gated inverter GINV2 are connected to the input end of the second inverter INV2, and the output end of the second inverter INV2 outputs the first operation address signal OP1<4:0>.

[0061] In this embodiment, the first narrowing command signal CMD_ACTD and the second command signal CMD_PRE serve as control signals of the gated inverter to control the transmission timing of the corresponding address signal. When the command signal is in the valid level state, the corresponding address information is transmitted to the subsequent stage, so that the corresponding command signal sequentially outputs its corresponding address information. Specifically, when the first narrowing command signal CMD_ACTD is in the valid level state ( Figure 3 , the first gate inverter GINV1 is turned on, and the first undecoded address signal ACT_BA<4:0> is output as the first operation address signal OP1<4:0>; when the second command signal CMD_PRE is in the valid level state ( Figure 3 The second gate inverter GINV2 is turned on, and the second undecoded address signal PRE_BA<4:0> is output as the first operation address signal OP1<4:0>.

[0062] Figure 5 A circuit structure diagram of another command address processing circuit provided by an embodiment of the present disclosure. Figure 3The same parts of the embodiments are not repeated here. In addition, the command address latch circuit 112 also includes a third inverter INV3 and a third gated inverter GINV3; wherein, the input end of the third inverter INV3 is connected to the output end of the second inverter INV2, the output end of the third inverter INV3 is connected to the input end of the third gated inverter GINV3, the control end of the third gated inverter GINV3 receives the first narrowing command signal CMD_ACTD and the second command signal CMD_PRE, and the output end of the third gated inverter GINV3 is connected to the input end of the third inverter.

[0063] Since the first narrowed command signal CMD_ACTD and the second command signal CMD_PRE are time-shared for address latching, only one third gated inverter GINV3 can be used to latch the addresses of the two commands when performing address latching. Moreover, by mounting the third inverter INV3 and the third gated inverter GINV3 at the output end of the command address latch circuit 112, the address information can be latched according to the command information. When the current command signal ends and the next command signal has not yet arrived, the circuit can latch the current address information, so that the command address latch circuit 112 can latch and output the corresponding storage body address information according to the command information. And only under the corresponding command will the address information of the activated storage body be transmitted to the decoding unit for decoding, and the level flip and decoding process will not occur when there is no corresponding command. Therefore, the waste of dynamic power consumption can be avoided.

[0064] In some embodiments, the circuit structure of the third gate inverter GINV3 can be as follows: Figure 6 shown. Figure 6 In the embodiment, the third gated inverter GINV3 includes an inverter formed by an NMOS and a PMOS. An NMOS is further formed between the source of the NMOS and ground to receive a control signal. The control terminal of the NMOS forms the control terminal of the third gated inverter GINV3. The control terminal of the third gated inverter GINV3 receives control signals: the first narrowing command signal CMD_ACTD and the second command signal CMD_PRE via a first OR gate. When either the first narrowing command signal CMD_ACTD or the second command signal CMD_PRE is at an active level, the third gated inverter GINV3 turns on and latches the signals received at its input terminals. When both the first narrowing command signal CMD_ACTD and the second command signal CMD_PRE are at an inactive level, the third gated inverter GINV3 turns off and no longer latches the input signals, thereby reducing power consumption.

[0065] In some embodiments, the first command signal may be an activation command Activate, and the second command signal may be one or more of multiple types of command signals different from the first command signal type, the multiple types of command signals including a pre-charge command (Pre-charge, PRE), a read command (Read), a write command (Write), a read command with automatic pre-charge (Read with Auto Pre-charge, RAP), and a read command with automatic pre-charge (Write with Auto Pre-charge, WAP). Figure 7 Take the example where the second command signal includes a plurality of command signals of different types.

[0066] Figure 7 A circuit structure diagram of another command address processing circuit provided by an embodiment of the present disclosure. Figure 3 The same parts as in the embodiment will not be described again. Figure 3 The embodiment differs in that the second command signal includes multiple decoded command signals, specifically: a precharge command CMD_PRE, a read command CMD_READ, a write command CMD_WRITE, a read command with automatic precharge CMD_RAP, and a write command with automatic precharge CMD_WAP. In some other embodiments, the second command signal may also be a portion of the above signals.

[0067] refer to Figure 7 Corresponding to the second command signal including multiple decoded command signals, the command processing circuit 111 further includes a second OR gate OR2. The second OR gate OR2 includes multiple input terminals, and all command signals of the second command signal serve as input terminals of the second OR gate OR2. When any signal in the second command signal is at an active level, the active level of the first command signal can be cut off, thereby correctly decoding the address.

[0068] Corresponding to the second command signal including a plurality of decoded command signals, the command address latch circuit 112 includes a plurality of gated inverters. The control terminal of each gated inverter receives the first command signal CMD_ACTD or a second command signal, such as Figure 7 The control terminal of the gated inverter GINVn shown in FIG receives the second command signal CMD_WAP; the input terminal of each gated inverter receives the address information corresponding to the command signal received by the control terminal, such as Figure 7 The control terminal of the gated inverter GINVn shown in FIG1 receives the second command signal WAP_BA<4:0>. Therefore, each gated inverter can transmit the address information of the operation corresponding to the command signal to the next stage under the control of the first command signal or the corresponding second command signal.

[0069] Corresponding to the second command signal including a plurality of decoded command signals, the control terminal of the third gate-controlled inverter GINV3 receives the first command signal and all the second command signals.

[0070] Through the above design, the memory address decoders of multiple commands can be reused, further saving area.

[0071] In some embodiments, the command address activation circuit 130 is connected to the command address processing circuit 110 and the address decoding circuit 120 and receives the first narrowed command signal CMD_ACTD and the second operation address signal OP2<31:0>. The command address activation circuit 130 is used to perform sampling processing and logical operation processing on the first narrowed command signal and the second command signal according to the second operation address signal OP2<31:0> to generate a storage body activation address signal OP3<31:0>.

[0072] That is, the command address activation circuit 130 directly receives the narrowed first command signal CMD_ACTD and uses this command signal in processing to avoid decoding conflicts. Furthermore, the command address activation circuit 130 samples and performs logical operations on the first and second command signals CMD_ACTD and CMD_PRE using the second operation address signals OP2<31:0> to generate the bank activation address signals OP3<31:0>. This circuit activates the corresponding address signals at the timing of the first and second command signals CMD_ACT and CMD_PRE, generating the corresponding bank activation address signals. This avoids invalid signal flips and reduces dynamic power consumption.

[0073] In another embodiment, the command address activation circuit 130 may not be connected to the command address processing circuit 110 and may not receive the first narrowed command signal CMD_ACTD, but may directly receive the first command signal CMD_ACT. In this case, the command address activation circuit 130 is also provided with a circuit similar to the command processing circuit 111, so that the command address activation circuit 130 narrows the first command signal to generate a narrowed first command signal that does not conflict with the second command signal.

[0074] In another embodiment, the command address activation circuit 130 may be disconnected from the command address processing circuit 110 and may directly receive the first command signal CMD_ACT instead of the first narrowed command signal CMD_ACTD. In this case, the command address activation circuit 130 uses its own processing logic design (e.g., a sequential circuit design similar to a latch) to give the second command signal CMD_PRE a higher priority than the first command signal CMD_ACT. When the second command signal CMD_PRE is at an active level, the command address activation circuit 130 outputs the second command signal CMD_PRE and the corresponding operation address, thereby directly using the first command signal CMD_ACT for sampling and logical operations to generate the bank activation address signals OP3<31:0>.

[0075] Figure 8 Schematic diagram of the circuit structure of a command address activation circuit provided by an embodiment of the present disclosure. Figure 8 As shown, the command address activation circuit 130 includes a first flip-flop DFF1, a second flip-flop DFF2 and a first latch LAT1, wherein,

[0076] A data input terminal D of the first flip-flop DFF1 receives the first shrink command signal CMD_ACTD, a clock input terminal Clk of the first flip-flop DFF1 receives the second operation address signal OP2<31:0>, and a data output terminal of the first flip-flop DFF1 is connected to a first input terminal of the first latch LAT1;

[0077] a data input terminal D of the second flip-flop DFF2 receiving the second command signal CMD_PRE, a clock input terminal Clk of the second flip-flop DFF2 receiving the second operation address signal OP2<31:0>, and a data output terminal of the second flip-flop DFF2 connected to the second input terminal of the first latch LAT1;

[0078] The output terminal of the first latch LAT1 outputs the bank activation address signal OP3<31:0>.

[0079] Thus, through the sequential logic of flip-flops and latches, the address information of the activated memory bank is transmitted to the subsequent stage only when the corresponding command is given. Without the corresponding command and activation address, the level flipping and decoding process will not occur, thus avoiding the waste of dynamic power consumption.

[0080] The first flip-flop DFF1 and the second flip-flop DFF2 may adopt a conventional D-type flip-flop structure. The first latch LAT1 may adopt a conventional NAND gate or NOR gate latch.

[0081] Figure 9 An embodiment of the present disclosure provides a Figure 8The detailed circuit structure diagram of the command address activation circuit is shown in the figure. Figure 9 As shown, the data output terminals of the first flip-flop DFF1 and the second flip-flop DFF2 both include a data positive output terminal Q and a data negative output terminal QN. The data negative output terminal QN of the first flip-flop DFF1 is connected to the first input terminal of the first latch LAT1; the data negative output terminal QN of the second flip-flop DFF2 is connected to the second input terminal of the first latch LAT1; the first latch LAT1 includes two NAND gates.

[0082] refer to Figure 9 The data input D of the first flip-flop DFF1 receives the first shrinkage command signal CMD_ACTD, the clock input Clk of the first flip-flop DFF1 receives the second operation address signal OP2<31:0>, and the data output of the first flip-flop DFF1 is connected to the first input of the first latch LAT1. The data input D of the second flip-flop DFF2 receives the second command signal CMD_PRE, the clock input Clk of the second flip-flop DFF2 receives the second operation address signal OP2<31:0>, and the data output of the second flip-flop DFF2 is connected to the second input of the first latch LAT1. The first latch LAT1 includes two NAND gates connected in a latch structure, with the first input of the first latch LAT1 serving as the set terminal of the latch structure, and the first input of the first latch LAT1 serving as the reset terminal of the latch structure.

[0083] The memory is configured with multiple banks, each of which receives a bit from a bank activation address signal. This article uses a 32-bank memory as an example. The bank activation address signal has 32 bits, OP3<31:0>, and each bank receives a bit from the bank activation address signal OP3<31:0>.

[0084] Correspondingly, the command activation address circuit 130 is also provided with a plurality of command activation address units, and the number of command activation address units is the same as the number of memory banks. Each command activation address unit receives one bit of the second operation address signal OP2<31:0> and performs operation processing with the corresponding command signal.

[0085] The second operation address signal OP2<31:0> serves as the clock signal for each command activation address unit. For the command activation address unit of the activated memory bank address, the corresponding second operation address signal is at an active level. At this time, when the first narrowed command signal CMD_ACTD is at an active level, the first input terminal of the first latch LAT1 receives an inactive level, and the output terminal of the first latch LAT1 outputs an active level, activating the memory bank to be activated. When the second command signal CMD_PRE is at an active level, the second input terminal of the first latch LAT1 receives an inactive level, and the output terminal of the first latch LAT1 outputs an inactive level, deactivating the activated memory bank.

[0086] Thus, the memory bank corresponding to the memory bank address is activated by the first command signal CMD_ACT, and the memory bank corresponding to the memory bank address is deactivated by the second command signal CMD_PRE, thereby controlling the memory bank.

[0087] It should be noted that in the field of electronics, while ensuring logical correctness, inputting or outputting signals after inversion, or inverting input or output signals, are easily modified in form and detail by those skilled in the art in practical applications, and do not deviate from the spirit and scope of this application. In other words, the processing of signals or the processing of inverted signals are within the scope of this application.

[0088] Figure 10 Another embodiment of the present disclosure provides Figure 8 Detailed circuit diagram of the command address activation circuit. Figure 10 Zhongyu Figure 8 and Figure 9 The similarities will not be repeated here. Figure 10 In the embodiment, the data output terminals of the first flip-flop DFF1 and the second flip-flop DFF2 both include a data positive phase output terminal Q and a data negative phase output terminal QN, the data negative phase output terminal QN of the first flip-flop DFF1 is connected to the first input terminal of the first latch LAT1; the data positive phase output terminal of the second flip-flop DFF2 is connected to the first input terminal of the second NOR gate, the second input terminal of the second NOR gate receives the full storage body control signal, and the output terminal of the second NOR gate is connected to the second input terminal of the first latch LAT1; the first latch LAT1 includes two NAND gates.

[0089] refer to Figure 10The data input D of the first flip-flop DFF1 receives the first shrinkage command signal CMD_ACTD, the clock input Clk of the first flip-flop DFF1 receives the second operation address signal OP2<31:0>, and the data inverting output QN of the first flip-flop DFF1 is connected to the first input of the first latch LAT1. The data input D of the second flip-flop DFF2 receives the second command signal CMD_PRE, the clock input Clk of the second flip-flop DFF2 receives the second operation address signal OP2<31:0>, and the data positive output Q of the second flip-flop DFF2 is connected to the first input of the second NOR gate NOR2. The second input of the second NOR gate NOR2 receives the all-bank control signal CMD_PRE All, and the output of the second NOR gate NOR2 is connected to the second input of the first latch LAT1. The first latch LAT1 includes two NAND gates connected in a latch structure, with the first input of the first latch LAT1 serving as the set terminal of the latch structure and the first input of the first latch LAT1 serving as the reset terminal of the latch structure.

[0090] Thus, the full-bank control signal CMD_PRE All is introduced through the second NOR gate NOR2, so that the activation of the bank is also controlled by the full-bank control signal CMD_PRE All. The full-bank control signal can be a signal for precharging the full bank. Specifically, the second operation address signal OP2<31:0> serves as a clock signal for each command activation address unit. For the command activation address unit of the activated bank address, its corresponding second operation address signal is a valid level. At this time, when the first narrowed command signal CMD_ACTD is a valid level, the first input end of the first latch LAT1 receives an invalid level, and the output end of the first latch LAT1 outputs a valid level, starting the bank that should be activated. When the second command signal CMD_PRE or the full-bank control signal CMD_PRE All is a valid level, the second input end of the first latch LAT1 receives an invalid level, and the output end of the first latch LAT1 outputs an invalid level, turning off the activated bank.

[0091] Therefore, the full-bank control signal is introduced through the second NOR gate to increase the control over the full-bank, thereby increasing the full-bank precharge function and the design flexibility.

[0092] Figure 11 A schematic diagram of a memory provided by an embodiment of the present disclosure. Figure 10As shown, the memory 1 includes the bank address decoder 10 described in any of the aforementioned embodiments and a plurality of memory banks 20. The plurality of memory banks 20 are connected to the bank address decoder 10 and are configured to activate corresponding memory banks according to the bank activation address signal. Specifically, the memory banks 20 include bank 0 (Bank0) through bank 31 (Bank31). Each memory bank receives one of the bank activation address signals OP3<31:0> and is enabled or disabled by the corresponding signal.

[0093] A bank is composed of multiple memory cells arranged in an array. The memory can be dynamic random access memory (DRAM), static random access memory (SRAM), NAND flash, NOR flash, ferroelectric memory (FeRAM), and other memory types, but this application does not specifically limit this.

[0094] Those skilled in the art will appreciate that the above-described embodiments are specific examples for implementing the present application, and that in actual applications, various changes in form and detail may be made thereto without departing from the spirit and scope of the present application. Any person skilled in the art may make changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be subject to the scope defined in the claims.

Claims

1. A memory bank address decoder, characterized in that: It includes a command address processing circuit, an address decoding circuit and a command address activation circuit, wherein: The command address processing circuit is configured to determine a first operation address signal based on a first command signal, a second command signal, a first undecoded address signal, and a second undecoded address signal; wherein the first undecoded address signal is an address signal corresponding to the first command signal, and the second undecoded address signal is an address signal corresponding to the second command signal; The address decoding circuit is connected to the command address processing circuit and receives the first operation address signal, and the address decoding circuit is used to decode the first operation address signal to obtain a second operation address signal; The command address activation circuit is connected to the address decoding circuit and receives the second operation address signal. The command address activation circuit is used to generate a storage body activation address signal based on the information of the first command signal, the second command signal and the second operation address signal.

2. The memory bank address decoder according to claim 1, wherein: The command address processing circuit includes a command processing circuit and a command address latch circuit, wherein: The command processing circuit is configured to narrow the effective level width of the first command signal according to the first command signal and the second command signal to generate a first narrowed command signal; wherein the effective level width of the first narrowed command signal is narrower than that of the first command signal; The command address latch circuit is connected to the command processing circuit and receives the first narrowed command signal, and is used to generate a first operation address signal according to the first narrowed command signal, the second command signal, the first undecoded address signal and the second undecoded address signal.

3. The memory bank address decoder according to claim 2, wherein: The command processing circuit includes a first inverter and a first NOR gate, the input end of the first inverter receives the first command signal, the first input end of the first NOR gate is connected to the output end of the first inverter, the second input end of the first NOR gate receives the second command signal, and the output end of the first NOR gate outputs the first narrowing command signal.

4. The memory bank address decoder according to claim 3, wherein: The command address latch circuit includes a first gated inverter and a second gated inverter; wherein, the control end of the first gated inverter receives the first narrowed command signal, and the input end of the first gated inverter receives the first undecoded address signal; the control end of the second gated inverter receives the second command signal, and the input end of the second gated inverter receives the second undecoded address signal; the output end of the first gated inverter and the output end of the second gated inverter are connected to the input end of the second inverter, and the output end of the second inverter outputs the first operation address signal.

5. The memory bank address decoder according to claim 4, wherein: The command address latch circuit also includes a third inverter and a third gated inverter; wherein, the input end of the third inverter is connected to the output end of the second inverter, the output end of the third inverter is connected to the input end of the third gated inverter, the control end of the third gated inverter receives the first narrowing command signal and the second command signal, and the output end of the third gated inverter is connected to the input end of the third inverter.

6. The memory bank address decoder according to claim 2, wherein: The command address activation circuit is connected to the command address processing circuit and the address decoding circuit and receives the first narrowed command signal and the second operation address signal. The command address activation circuit is used to perform sampling processing and logical operation processing on the first narrowed command signal and the second command signal according to the second operation address signal to generate a storage body activation address signal.

7. The memory bank address decoder according to claim 6, wherein: The command address activation circuit includes a first trigger, a second trigger and a first latch, wherein: A data input terminal of the first flip-flop receives the first shrink command signal, a clock input terminal of the first flip-flop receives the second operation address signal, and a data output terminal of the first flip-flop is connected to a first input terminal of the first latch; A data input terminal of the second flip-flop receives the second command signal, a clock input terminal of the second flip-flop receives the second operation address signal, and a data output terminal of the second flip-flop is connected to the second input terminal of the first latch; The output terminal of the first latch outputs the bank activation address signal.

8. The memory bank address decoder according to claim 7, wherein: The data output ends of the first trigger and the second trigger both include a data positive output end and a data negative output end, the data negative output end of the first trigger is connected to the first input end of the first latch; the data negative output end of the second trigger is connected to the second input end of the first latch; the first latch includes two NAND gates.

9. The memory bank address decoder according to claim 7, wherein: The data output terminals of the first trigger and the second trigger both include a data positive phase output terminal and a data negative phase output terminal, and the data negative phase output terminal of the first trigger is connected to the first input terminal of the first latch; the data positive phase output terminal of the second trigger is connected to the first input terminal of the second NOR gate, the second input terminal of the second NOR gate receives the full storage body control signal, and the output terminal of the second NOR gate is connected to the second input terminal of the first latch; the first latch includes two NAND gates.

10. A memory, characterized in that: The memory includes a memory address decoder as described in any one of claims 1 to 9 and multiple memory bodies, the multiple memory bodies are connected to the memory address decoder, and the memory is used to activate corresponding memory bodies according to the memory activation address signal.

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