Ultra-thin multilayer memory chip stack package method and system

Abstract

This invention relates to the field of chip packaging technology and discloses a method for stacking and packaging ultra-thin multilayer memory chips. The method includes: obtaining memory chips to be packaged; classifying the memory chips to be packaged according to chip quality to obtain target chips; further classifying the target chips to obtain multiple groups of chips; optimizing the thickness of the multiple groups of classified chips to obtain thickness-optimized chips; further refining the thickness-optimized chips to obtain refined chips; coating the refined chips with a material to obtain coated chips; curing the coated chips to obtain cured chips; stacking the cured chips to obtain stacked chips; performing 3D modeling on the stacked chips to plan the dispensing path and obtain the dispensing path; reinforcing the stacked chips to obtain reinforced chips; and performing internal interconnection, preliminary packaging, and outer casing injection molding on the reinforced chips to obtain packaged chips. This invention can improve the packaging quality of ultra-thin multilayer memory chips.

Description

Technical Field

[0001] This invention relates to a method for stacking and packaging ultra-thin multilayer memory chips, belonging to the field of chip packaging technology. Background Technology

[0002] With the rapid development of modern electronic devices towards miniaturization and high performance, ultra-thin multilayer memory chip stacking and packaging technology has become key to improving the capacity and performance of memory chips. By precisely stacking multiple memory chips and packaging them appropriately, it can greatly expand storage capacity within a limited space, meeting the needs of many smart terminals and other devices.

[0003] Currently, the process of implementing ultra-thin multilayer memory chip stacking and packaging involves several steps: first, preparing the initial chips through pre-processing such as dicing, cleaning, and thinning; then, fabricating intermediate layers, aligning and temporarily fixing the chips, and repeating the stacking process until the designed number of layers is reached; subsequently, vias are drilled to achieve internal interconnects, connecting the chips to the packaging substrate; after soldering, underfill and external protection are performed; and finally, the finished product is inspected to ensure quality. However, existing methods have certain drawbacks. In the chip pre-processing stage, controlling the precision of thinning operations is difficult, easily leading to uneven thickness that affects subsequent stacking. During chip stacking, relying solely on conventional positioning methods is insufficient to guarantee high-precision alignment of each chip layer; as the number of layers increases, accumulated deviations can interfere with electrical connections. In the internal interconnect stage, the via drilling and metal layer deposition processes are complex, and even slight errors can result in poor conductivity. Furthermore, soldering defects such as cold solder joints and voids are prone to occur, and uneven underfill can introduce stress hazards, leading to lower chip packaging quality. Summary of the Invention

[0004] To address the aforementioned problems, this invention provides a method for stacking and packaging ultra-thin multilayer memory chips, which can improve the packaging quality of ultra-thin multilayer memory chips.

[0005] To achieve the above objectives, the present invention provides an ultra-thin multilayer memory chip stacking and packaging method, comprising:

[0006] A memory chip to be packaged is obtained, and the memory chip to be packaged is optically scanned to obtain a scanned image. The surface defects and circuit integrity of the memory chip to be packaged are analyzed using the scanned image. Based on the surface defects and circuit integrity, the memory chip to be packaged is classified into chip quality categories. Chips that meet the preset quality after chip quality classification are extracted to obtain target chips. The chip thickness and pad distribution of the target chips are identified using the scanned image. Based on the chip thickness and pad distribution, the target chips are further classified to obtain multiple groups of chips.

[0007] Using a pre-configured thickness sensor, the chip thickness of each group of chips in the multiple groups of chips is measured to obtain thickness measurement data. Using the thickness measurement data, an optimal thickness range for the multiple groups of chips is constructed. Based on the optimal thickness range, the thickness of the multiple groups of chips is optimized to obtain thickness-optimized chips. The thickness-optimized chips are subjected to quality inspection. Based on the inspection results, the thickness-optimized chips are further selected to obtain selected chips.

[0008] The material parameters of the selected chip are queried, and based on the material parameters, the intermediate layer material of the selected chip is configured. The selected chip is coated with the intermediate layer material to obtain a coated chip. The coated chip is cured using a pre-configured curing characteristic curve to obtain a cured chip. The identification attributes and intermediate layer positions of the cured chip are identified. Based on the identification attributes and intermediate layer positions, a stacking path is planned for the cured chip to obtain a planned path. Based on the planned path, the cured chips are stacked to obtain a stacked chip.

[0009] The stacking structure of the stacked chip is queried, and a three-dimensional model of the stacked chip is performed based on the stacking structure to obtain a stacked chip model. Using the stacked chip model, a dispensing path is planned for the stacked chip to obtain a dispensing path. Based on the dispensing path, the stacked chip is reinforced to obtain a reinforced chip.

[0010] The three-dimensional model and circuit layout information of the rugged chip are queried to perform internal interconnection of the rugged chip to obtain a link chip. The stacking parameters and filling requirements of the link chip are queried to perform preliminary packaging of the link chip to obtain a preliminary packaged chip. The process parameters of the preliminary packaged chip are identified. Based on the process parameters, the preliminary packaged chip is subjected to shell injection molding to obtain a packaged chip.

[0011] Optionally, the step of analyzing the surface defects and circuit integrity of the memory chip to be packaged using the scanned image includes:

[0012] The scanned image is converted to grayscale to obtain a grayscale image;

[0013] Perform image surface detection on the grayscale image to determine the surface defect contours of the memory chip to be packaged;

[0014] The surface defect contour is processed to obtain a refined defect state.

[0015] The refined defect state is quantified to determine the surface defect degree of the memory chip to be packaged.

[0016] The circuit wiring features of the memory chip to be packaged are identified using the scanned image;

[0017] The circuit integrity of the memory chip to be packaged is identified using the circuit wiring characteristics.

[0018] Optionally, the step of using the scanned image to identify the chip thickness and pad distribution of the target chip includes:

[0019] Extract the vertical boundary contour region of the scanned image;

[0020] Calculate the vertical pixel value of the vertical boundary contour region;

[0021] The chip thickness of the target chip is obtained by performing size conversion on the vertical pixel values;

[0022] Target detection is performed on the scanned image to obtain the detected target;

[0023] Identify the feature points of the target being detected;

[0024] Based on the feature points, the shape, size, and distance characteristics of the pads corresponding to the target chip are analyzed, and the number and arrangement of the pads are counted to determine the pad distribution status.

[0025] Optionally, identifying the feature points of the detected target includes:

[0026] Construct the scale space of the target to be detected;

[0027] The target object is marked with key points in the scale space to obtain marked key points;

[0028] After assigning directions to the marked key points, feature points are determined using the following formula:

[0029]

[0030] in, Feature points This represents the image gradient value of the scanned image corresponding to the detected target. Mark the direction of key points. Indicates a scanned image. , , , Represents the origin of the scanned image in scale space. The nearest neighboring points.

[0031] Optionally, the quality inspection of the thickness-optimized chip includes:

[0032] Acquire microscopic images of the thickness-optimized chip;

[0033] Identify the refinement features of the microscopic image;

[0034] The thickness-optimized chip is subjected to appearance inspection using the refined features.

[0035] Construct multiple test modes and test vectors for the thickness-optimized chip;

[0036] After inputting a preset electrical signal into the thickness optimization chip, the circuit performance of the thickness optimization chip is tested according to the multiple test modes and test vectors.

[0037] Configure a high-temperature aging test environment and a temperature and humidity cycling test environment for the thickness-optimized chip, so as to conduct reliability tests on the thickness-optimized chip using the high-temperature aging test environment and the temperature and humidity cycling test environment;

[0038] After the appearance inspection, circuit performance inspection and reliability test are completed, the quality inspection of the thickness-optimized chip is completed.

[0039] Optionally, the step of coating the selected chip with the intermediate layer material to obtain a coated chip includes:

[0040] The material properties of the intermediate layer material and the chip size of the selected chip are queried in order to configure a suitable coating device;

[0041] Obtain the coating precision requirements of the selected chips;

[0042] Based on the coating accuracy requirements, the parameters of the coating device are set to obtain the debugging device;

[0043] Using the aforementioned debugging device, the selected chip is coated with a material to obtain a coated chip.

[0044] Optionally, the step of planning the stacking path of the solidified chip based on the identification attribute and the intermediate layer position to obtain the planned path includes:

[0045] The stacking order of the cured chips is determined based on the identification attributes;

[0046] The chip alignment method of the solidified chip during stacking is determined based on the position of the intermediate layer;

[0047] Query the device motion characteristics of the stacking equipment corresponding to the solidified chip;

[0048] Based on the stacking order, the chip alignment method, and the device motion characteristics, the stacking constraints of the solidified chips are constructed.

[0049] Construct the initial stacking path for the solidified chip;

[0050] Based on the stacking constraints, the initial stacking paths are initially filtered to obtain filtered paths;

[0051] Using a pre-configured ant colony algorithm, a global search is performed on the filtering path to obtain the search pheromone;

[0052] The search pheromone is updated using the following formula to obtain the updated pheromone:

[0053]

[0054] in, This indicates an update of pheromones. This represents the decay coefficient of the search pheromone. This represents the concentration of pheromones searched along path i to path j at time t. This represents the newly added pheromone concentration, and T represents the time when the search for pheromones began.

[0055] Based on the updated pheromone, calculate the probability value of each path being selected in the filtering path;

[0056] Based on the probability value, the stacking path of the solidified chip is selected to obtain the planned path.

[0057] Optionally, calculating the probability value of each path being selected in the filtering path based on the updated pheromone includes:

[0058] The probability of each path being selected in the filtering path is calculated using the following formula:

[0059]

[0060] in, Represents the probability value. This indicates an update to pheromone concentration. Representing heuristic information, Factors indicating the importance of pheromones Factors representing the importance of heuristic information This represents the set of the next path that can be selected at the current node k, i.e., the set of all candidate paths that satisfy the constraints.

[0061] Optionally, the step of using the stacked chip model to plan the dispensing path for the stacked chips to obtain the dispensing path includes:

[0062] Construct the initial dispensing path for the stacked chips;

[0063] Based on the stacked chip model, create a dispensing simulation scenario for the stacked chips;

[0064] The initial dispensing path is used as the simulation animation trajectory of the stacked chips;

[0065] Based on the dispensing simulation scenario and the simulation animation trajectory, dispensing simulation is performed on the stacked chips;

[0066] The dispensing path for the stacked chips is determined based on the simulation results of the dispensing simulation.

[0067] In a second aspect, the present invention provides an ultra-thin multilayer memory chip stacking and packaging system, the system comprising:

[0068] The chip classification module is used to acquire memory chips to be packaged, perform optical scanning on the memory chips to be packaged to obtain scanned images, analyze the surface defects and circuit integrity of the memory chips to be packaged using the scanned images, classify the memory chips to be packaged based on the surface defects and circuit integrity, extract chips that meet the preset quality after chip quality classification to obtain target chips, identify the chip thickness and pad distribution of the target chips using the scanned images, and further classify the target chips based on the chip thickness and pad distribution to obtain multiple groups of chips;

[0069] The chip selection module is used to measure the chip thickness of each group of chips in the multiple groups of chips using a pre-configured thickness sensor to obtain thickness measurement data. Using the thickness measurement data, an optimal thickness range for the multiple groups of chips is constructed. Based on the optimal thickness range, the thickness of the multiple groups of chips is optimized to obtain a thickness-optimized chip. The thickness-optimized chip is subjected to quality inspection. Based on the inspection results, the thickness-optimized chip is selected to obtain a selected chip.

[0070] The chip stacking module is used to query the material parameters of the selected chip, configure the intermediate layer material of the selected chip based on the material parameters, coat the selected chip with the intermediate layer material to obtain a coated chip, cure the coated chip with a pre-configured curing characteristic curve to obtain a cured chip, identify the identification attributes and intermediate layer position of the cured chip, plan the stacking path of the cured chip based on the identification attributes and intermediate layer position to obtain a planned path, and stack the cured chips based on the planned path to obtain a stacked chip.

[0071] The chip hardening module is used to query the stacking structure of the stacked chips, and based on the stacking structure, perform three-dimensional modeling of the stacked chips to obtain a stacked chip model. Using the stacked chip model, the module performs dispensing path planning for the stacked chips to obtain a dispensing path. Based on the dispensing path, the module performs chip hardening on the stacked chips to obtain a hardened chip.

[0072] The chip packaging module is used to query the three-dimensional model and circuit layout information of the rugged chip to perform internal interconnection of the rugged chip to obtain a link chip, query the stacking parameters and filling requirements of the link chip to perform preliminary packaging of the link chip to obtain a preliminary packaged chip, identify the process parameters of the preliminary packaged chip, and perform shell injection molding on the preliminary packaged chip based on the process parameters to obtain a packaged chip.

[0073] Compared to the problems described in the background art, this invention first classifies the memory chips to be packaged based on the surface defect level and the circuit integrity. This facilitates targeted processing of chips of different qualities in subsequent packaging. For example, high-quality chips can be used in packaging products with high quality requirements, while medium-quality chips can be used in scenarios with lower performance requirements or after additional processing, depending on the actual situation. This helps to rationally allocate resources, improve overall packaging efficiency, and ensure that the quality of the final packaged product meets different needs. Furthermore, embodiments of this invention utilize pre-configured thickness sensors to measure the chip thickness of each group of chips. The thickness measurement data can be used to determine whether the chip meets the expected process requirements. This also provides an accurate reference for further optimizing chip thickness, which is a crucial foundation for ensuring the accuracy and quality of the entire packaging process. Using the thickness measurement data, an optimal thickness range can be determined for the multiple chip sets, i.e., an ideal thickness range. This range is set after comprehensively considering factors such as the bonding accuracy between layers during chip stacking and the overall dimensional requirements after packaging, maximizing the smooth progress of subsequent packaging and the stability of product performance. Furthermore, by querying the material parameters of the selected chips and configuring the intermediate layer material based on these parameters, this invention can comprehensively and deeply understand the various material properties of the selected chips, including their chemical composition. Key factors such as composition, physical properties (e.g., hardness, coefficient of thermal expansion, dielectric constant), and surface condition provide an accurate data foundation for the rational selection and configuration of subsequent intermediate layer materials. This ensures that the intermediate layer and the chip can achieve good compatibility in physical, chemical, and other aspects. The selected chip is then fixed using the intermediate layer material, and the coated chip is cured using a pre-configured curing characteristic curve. The resulting cured chip better fixes the chip position, enhances the bonding force between chips, and prevents problems such as chip displacement or loosening during subsequent use. This invention, by querying the stacking structure of the stacked chips and performing 3D modeling based on that structure, provides a stacked chip model that can help... This method analyzes the overall performance characteristics of stacked chips and identifies potential weaknesses. For example, by understanding the chip stacking method, it can predict the performance in terms of heat conduction and electrical connection, providing a basis for optimizing chip performance. It can also identify reliability risks that may be caused by unreasonable stacking structure in advance. Furthermore, based on the dispensing path, the stacked chips can be reinforced to obtain reinforced chips. Through effective chip reinforcement, the structural integrity of the stacked chips is maintained, ensuring good electrical connection and heat conduction performance between chips. This ensures that the chips can continuously and stably perform their functions during long-term use, which plays an important supporting role in the performance and lifespan of the entire electronic product and helps to improve the overall quality of the product and user satisfaction.Furthermore, this invention, based on the aforementioned process parameters, performs shell injection molding on the preliminary packaged chip to obtain the packaged chip. According to the identified process parameters, a suitable injection mold and injection molding material (such as commonly used engineering plastics ABS, PP, etc.) are selected. The preliminary packaged chip is placed at a specific position in the injection mold. Using an injection molding machine, molten injection material is injected into the mold cavity according to set process parameters such as mold temperature, injection pressure, and injection speed, encapsulating the preliminary packaged chip. After cooling and solidification, a robust shell is formed, ultimately obtaining the packaged chip. By using an injection molding machine to perform shell injection molding according to parameter settings, the final packaged chip can be obtained, thereby improving the packaging quality of ultra-thin multilayer memory chips. Attached Figure Description

[0074] Figure 1 This is a flowchart illustrating an ultrathin multilayer memory chip stacking and packaging method according to an embodiment of the present invention.

[0075] Figure 2 This is a schematic diagram of a module of an ultra-thin multilayer memory chip stacking and packaging system provided in an embodiment of the present invention.

[0076] The objectives, features, and advantages of this invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0077] It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0078] This application provides a method for stacking and packaging ultra-thin multilayer memory chips. The execution subject of the ultra-thin multilayer memory chip stacking and packaging method includes, but is not limited to, at least one of the following electronic devices that can be configured to execute the method provided in this application: a server, a terminal, etc. In other words, the ultra-thin multilayer memory chip stacking and packaging method can be executed by software or hardware installed on a terminal device or a server device. The server includes, but is not limited to, a single server, a server cluster, a cloud server, or a cloud server cluster.

[0079] Example 1:

[0080] Reference Figure 1 The diagram shown is a flowchart illustrating an ultra-thin multilayer memory chip stacking and packaging method according to an embodiment of the present invention. In this embodiment, the ultra-thin multilayer memory chip stacking and packaging method includes:

[0081] S1. Obtain the memory chip to be packaged, perform optical scanning on the memory chip to be packaged to obtain a scanned image, use the scanned image to analyze the surface defects and circuit integrity of the memory chip to be packaged, classify the chip quality based on the surface defects and circuit integrity, extract the chips that meet the preset quality after chip quality classification to obtain the target chip, use the scanned image to identify the chip thickness and pad distribution of the target chip, and classify the target chip further based on the chip thickness and pad distribution to obtain multiple groups of chips.

[0082] The present invention, through the acquisition of the memory chip to be packaged, clarifies the start of the work, ensuring that there are corresponding chips available for processing in subsequent packaging processes, which is a prerequisite for the orderly conduct of the entire packaging process. The memory chip to be packaged refers to an ultra-thin memory chip that has completed the main circuit manufacturing and wafer processing steps in the chip manufacturing process, but has not yet undergone packaging.

[0083] Optionally, the memory chip to be packaged can be obtained by selecting a suitable batch of memory chips from the inventory according to the packaging project requirements.

[0084] The embodiments of the present invention obtain intuitive image information of the appearance and some internal structure of the memory chip by performing optical scanning on the memory chip to be packaged. The actual physical state of the chip is presented in a visual form. These images can reflect many detailed features of the chip and provide a data foundation for subsequent analysis.

[0085] Optionally, the scanned image can be scanned using a specialized chip surface inspection scanner, such as a laser chip scanner.

[0086] Furthermore, by utilizing the scanned image, this embodiment of the invention can accurately grasp the key quality indicators of the chip by analyzing the surface defects and circuit integrity of the memory chip to be packaged. Surface defects are related to the stability and reliability of the chip after packaging, while circuit integrity directly determines whether the chip can work normally. Through this analysis, chips with potential quality problems can be identified in advance, avoiding the subsequent packaging of problematic chips, thereby ensuring the quality of the final packaged product.

[0087] As an embodiment of the present invention, the step of analyzing the surface defects and circuit integrity of the memory chip to be packaged using the scanned image includes: converting the scanned image to grayscale to obtain a grayscale image; performing image surface detection on the grayscale image to determine the surface defect contour of the memory chip to be packaged; performing defect morphology processing on the surface defect contour to obtain a refined defect state; performing quantization processing on the refined defect state to determine the surface defects of the memory chip to be packaged; using the scanned image to identify the circuit wiring features of the memory chip to be packaged; and using the circuit wiring features to identify the circuit integrity of the memory chip to be packaged.

[0088] The grayscale image refers to an image representation that contains only brightness information and no color information. The surface defect contour refers to the boundary shape of the defective part of the object's surface in the image (usually an image that has undergone certain processing, such as a binarized image). It outlines the boundary between the defective area and the normal area. Through this contour, one can intuitively understand the shape, size, and specific location of the defect on the object's surface. The circuit wiring features refer to the characteristics of the layout, direction, width, spacing, and interconnection of circuits on the substrate (such as a PCB board) or inside the chip in electronic circuits.

[0089] Optionally, the grayscale image can be obtained by binarizing the scanned image. The surface defect contour of the memory chip to be packaged can be obtained by using the Canny edge detection algorithm to perform edge detection on the grayscale image to identify defects such as scratches and cracks on the chip surface. The refinement of the defect state can be obtained by performing erosion and dilation operations on the image area corresponding to the surface defect contour. The quantification of the refinement of the defect state to determine the surface defect degree of the memory chip to be packaged can be achieved by using a threshold segmentation algorithm to separate the defect area from the background based on the difference in grayscale values ​​between the chip surface material and the defective part, and statistically analyzing the area, quantity, and other indicators of the defective area to quantify the surface defect degree. The circuit wiring features can be obtained by extracting the width, continuity, and other features of the circuit lines using a roll-to-roll model. The identification of the circuit integrity of the memory chip to be packaged using the circuit wiring features can be achieved by using a pattern recognition algorithm to compare the circuit wiring features with a standard, defect-free circuit wiring template to check for the existence of line interruptions, short circuits, etc.

[0090] The present invention categorizes the memory chips to be packaged based on the surface defect rate and the circuit integrity, which facilitates targeted processing of chips of different qualities. For example, high-quality chips can be used in packaging products with high quality requirements, while medium-quality chips can be used in scenarios with lower performance requirements or after additional processing, depending on the actual situation. This helps to rationally allocate resources, improve overall packaging efficiency, and ensure that the quality of the final packaged product meets different needs.

[0091] Optionally, the chip quality classification of the memory chip to be packaged based on the surface defect rate and circuit integrity is determined according to the specific requirements of the packaging project and the general industry standards for memory chip quality. Detailed chip quality classification standards are established. For example, a threshold is set for the proportion of the total surface defect area to the total chip area (e.g., less than 0.1% is high quality, 0.1% - 0.5% is medium quality, etc.). Simultaneously, regarding circuit integrity, different evaluation criteria are specified, such as high quality if there are no open circuits or short circuits and all functional modules are connected normally, and medium quality if there are a few repairable circuit problems. The data obtained from the surface defect rate and circuit integrity analysis are compared with the established quality classification standards. By writing corresponding program code or using professional data analysis software, each chip is automatically labeled with a quality level, classifying the chips into different quality sets such as high quality, medium quality, and low quality, thus achieving chip quality classification.

[0092] Furthermore, by extracting chips that meet the preset quality criteria after chip quality classification, the present invention can further ensure that the chips involved in packaging meet the expected quality, reduce the possibility of packaging failure or poor performance of the packaged product due to initial chip quality problems, and lay the foundation for creating high-quality packaged memory chip products.

[0093] Optionally, the target chip can be determined based on the objectives of this packaging task. For example, if the goal is to produce high-quality memory chip packages for high-end electronic products, then the preset quality can be set as high-quality chips. If the goal is only to package ordinary electronic products with slightly lower performance requirements, then the requirements can be relaxed appropriately, and chips of medium quality or above can be selected. The specific preset quality level range can be determined and extracted from the memory chips to be packaged after the chip quality classification.

[0094] Furthermore, by utilizing the scanned image to identify the chip thickness and pad distribution of the target chip, this embodiment of the invention ensures that subsequent packaging processes can be precisely adapted and optimized based on the actual situation of the chip, thereby improving the accuracy and reliability of packaging.

[0095] As an embodiment of the present invention, the step of using the scanned image to identify the chip thickness and pad distribution of the target chip includes: extracting the vertical boundary contour region of the scanned image, calculating the vertical pixel value of the vertical boundary contour region, performing size conversion on the vertical pixel value to obtain the chip thickness of the target chip, performing target detection on the scanned image to obtain the detected target, identifying the feature points of the detected target, analyzing the shape, size, and distance features of the corresponding pads of the target chip based on the feature points, and counting the number and arrangement of the pads to determine the pad distribution state.

[0096] Optionally, the extraction of the vertical boundary contour region of the scanned image can be achieved using image processing software (such as ImageJ, OpenCV, etc.). Edge detection algorithms (such as Canny edge detection) can be used to identify the vertical boundaries in the image, and then a contour extraction function can be applied to extract the vertical boundary contour region. The vertical pixel values ​​of the vertical boundary contour region can be obtained by selecting the extracted vertical boundary contour region using OpenCV and statistically analyzing the vertical pixel values ​​within that region using pixel value statistics tools. The chip thickness can be calculated based on the known ratio between image pixels and actual size (determined in advance through calibration). The vertical pixel values ​​are converted to the actual physical size according to this ratio, thus determining the chip thickness. For example, 1 pixel corresponds to 0.1 mm. The target detection can be achieved using deep learning target detection frameworks (such as YOLO, Faster R-CNN). (etc.), input scanned image data with the target chip category already labeled for training, and then use the trained model to detect new scanned images. The distribution state of the pads can be obtained by analyzing information such as feature point coordinates and distribution, combined with geometric calculation methods, to calculate the approximate shape, size and distance between the pads, and at the same time, to count the number and arrangement order of the pads corresponding to the feature points, thereby determining their distribution state.

[0097] Furthermore, as an optional embodiment of the present invention, the identification of feature points of the detected target includes: constructing a scale space of the detected target; marking key points of the detected target in the scale space to obtain marked key points; assigning directions to the marked key points; and using the following formula to determine feature points from the marked key points to obtain feature points:

[0098]

[0099] in, Representing feature points, This represents the image gradient value of the scanned image corresponding to the detected target. Indicates the direction of the marked key points. Indicates a scanned image. , , , Represents the origin of the scanned image in scale space. The nearest neighboring points.

[0100] Furthermore, this embodiment of the invention further classifies the target chip based on the chip thickness and the pad distribution state to obtain multiple groups of chips, thereby improving the accuracy and efficiency of the chip packaging process. This facilitates more precise and efficient operations during the packaging process. For example, when chips in the same group are stacked, it is easier to ensure the alignment accuracy between layers and to better match them when making electrical connections. This helps to improve the orderliness of the entire packaging process and the quality consistency of the final packaged product.

[0101] Optionally, based on the chip thickness and the pad distribution state, the target chip is further classified to obtain multiple groups of chips. The classification intervals and grouping rules for chip thickness and pad distribution state can be determined according to the actual needs of chip packaging process and experience. For example, the chip thickness can be divided into groups at certain micrometer intervals (such as 0-50 micrometers as a group, 50-100 micrometers as a group, etc.). For the pad distribution state, it can be classified according to the arrangement and spacing range of the pads (such as grouping those with the same array arrangement and similar spacing into one group, etc.).

[0102] S2. Using a pre-configured thickness sensor, measure the chip thickness of each group of chips in the multiple groups of chips to obtain thickness measurement data. Using the thickness measurement data, construct an optimal thickness range for the multiple groups of chips. Based on the optimal thickness range, optimize the thickness of the multiple groups of chips to obtain thickness-optimized chips. Perform quality inspection on the thickness-optimized chips. Based on the inspection results of the quality inspection, refine the thickness-optimized chips to obtain refined chips.

[0103] In this embodiment of the invention, the thickness of each chip in the multiple chip groups is measured by using a pre-configured thickness sensor. The obtained thickness measurement data can be used to determine whether the chip meets the expected process requirements, and at the same time, it provides an accurate reference for further optimization of chip thickness. It is an important basic link to ensure the accuracy and quality of the entire packaging process.

[0104] The thickness sensor mentioned above refers to a sensor used to measure the thickness of an object. It can convert the physical quantity of the object's thickness into a measurable and analyzable electrical signal or other form of signal, thereby obtaining a specific value of the thickness. The appropriate thickness sensor can be selected according to factors such as the size of the chip, accuracy requirements, and measurement environment. For example, for cases with high accuracy requirements and small chip size, a laser thickness sensor can be selected, which measures distance by emitting a laser beam and receiving reflected light, thereby obtaining the chip thickness. For scenarios with larger chips and moderate accuracy requirements, capacitive or inductive thickness sensors can also be selected, which detect thickness based on the influence of different media on electric or magnetic fields.

[0105] By utilizing the thickness measurement data, this invention can determine an ideal thickness range, or preferred thickness range, for constructing a preferred thickness range for the multiple chip sets. This range is set after comprehensively considering factors such as the bonding accuracy between layers during chip stacking and the overall size requirements after packaging, which can maximize the smooth progress of subsequent packaging and the stability of product performance.

[0106] Optionally, the preferred thickness range can be determined by comprehensively considering the chip thickness requirements of subsequent stacking and packaging processes, relevant industry standards and specifications, and practical production experience. On the one hand, it analyzes the maximum and minimum allowable thickness range during chip stacking to ensure good adhesion between layers and avoid structural instability caused by cumulative thickness errors. On the other hand, it refers to the chip thickness range used in successfully packaged products of the same type as a reference. For example, based on analysis and experience, for a specific type of memory chip, its preferred thickness range is determined to be [50μm, 80μm], meaning that chips with thicknesses within this range can better meet process requirements in subsequent packaging processes. The specific setting needs to be determined based on actual application.

[0107] The embodiments of the present invention optimize the thickness of multiple chips based on the preferred thickness range to obtain thickness-optimized chips. This reduces problems such as alignment deviation and poor connection caused by thickness differences, improves the electrical performance and overall stability of the packaged product, and ensures that the packaging quality reaches a high level.

[0108] Optionally, the thickness optimization of the multiple chip groups to obtain thickness-optimized chips involves comparing the thickness measurement data of each chip group with a predetermined preferred thickness range. By writing program scripts or using database queries, the chips are categorized into three types based on their thickness: chips with a thickness greater than the upper limit of the range (requiring thinning), chips with a thickness within the range (requiring no processing and directly included in the thickness optimization), and chips with a thickness less than the lower limit of the range (requiring thickening or other compensatory measures). Processing is then performed according to the thickness range, such as thinning (for chips exceeding the upper limit): For chips requiring thinning, they are placed on a high-precision chip grinding machine with precise control over rotation speed, pressure, and grinding time. Based on the specific value by which the chip exceeds the preferred thickness range, combined with factors such as chip material and size, appropriate grinding parameters are set. For example, if the chip thickness exceeds the upper limit of 10μm, the grinding equipment can be set to a rotation speed of 5000 rpm, a grinding pressure of 0.5 N / cm², and a grinding time of 2 minutes. During the grinding process, the chip thickness is monitored in real time using an online thickness monitoring system. When the chip thickness reaches the preferred range, the grinding operation is stopped.

[0109] Thickening or compensatory measures (for chips with thickness below the lower limit): For chips with a thickness slightly below the lower limit, if the chip structure allows, the chip can be appropriately thickened by adding a thin, chip-compatible polymer material as an intermediate layer on the chip surface. Using high-precision coating equipment, the flow rate and coating speed of the coating material are precisely controlled according to the calculated required thickness value to uniformly coat the intermediate layer material on the chip surface, so that the chip thickness reaches the optimal range; or in subsequent stacking processes, the thickness of other matching chips or intermediate layers is adjusted to ensure that the overall thickness of the stacked structure meets the requirements, ultimately optimizing the thickness of all chips to obtain a thickness-optimized chip.

[0110] The embodiments of the present invention can comprehensively check the various performance indicators and quality status of the thickness-optimized chip by performing quality inspection on the thickness-optimized chip. It is not limited to the thickness parameter, but also includes multiple aspects such as chip surface quality (whether there are scratches, cracks and other defects), circuit performance (whether there are short circuits, open circuits and other problems), and electrical parameters (whether the resistance, capacitance and other parameters meet the standards).

[0111] As an embodiment of the present invention, the quality inspection of the thickness-optimized chip includes: acquiring a microscopic image of the thickness-optimized chip, identifying the refinement features of the microscopic image, performing an appearance inspection of the thickness-optimized chip using the refinement features, constructing multiple test modes and test vectors for the thickness-optimized chip, inputting a preset electrical signal to the thickness-optimized chip, performing circuit performance testing on the thickness-optimized chip according to the multiple test modes and test vectors, configuring a high-temperature aging test environment and a temperature and humidity cycling test environment for the thickness-optimized chip, and performing reliability testing on the thickness-optimized chip using the high-temperature aging test environment and the temperature and humidity cycling test environment. After the appearance inspection, circuit performance testing, and reliability testing are completed, the quality inspection of the thickness-optimized chip is completed.

[0112] The preset electrical signals refer to a series of electrical signals with specific parameters that are pre-set and input to the chip pins during circuit performance testing. These parameters typically include voltage amplitude, frequency, phase, and current magnitude, aiming to simulate various excitation signals that the chip may receive in actual working scenarios. This comprehensively tests the response of the chip's internal circuitry, determines whether the chip can function normally, and whether its performance indicators meet design requirements. The multiple test modes refer to a set of specific test methods or strategies adopted for different functional characteristics, working states, or testing focuses of the chip. Each test mode focuses on evaluating the chip's performance and functional integrity from a specific perspective, often covering a series of related test operations and corresponding electrical signal input and output monitoring processes. The test vector refers to a set of electrical signal input values ​​arranged in a specific order with a clear logical relationship and their corresponding expected output values ​​under a specific test mode. It can be figuratively understood as a "signal instruction set" that guides the chip to complete a specific test process and is used to verify specific functions or performance of the chip.

[0113] Optionally, the microscopic image can be acquired using a high-resolution optical microscope, and the refinement features can be extracted and identified using convolutional networks in a deep learning model. The appearance inspection of the thickness-optimized chip using the refinement features can be achieved by using ImageJ / Fiji tools in conjunction with the refinement features to identify and mark areas of appearance defects in the thickness-optimized chip. The chip's appearance is then judged to be acceptable according to preset appearance quality standards (such as the total area of ​​surface defects being less than a certain percentage of the total chip area). The preset electrical signal can be input using an integrated circuit tester.

[0114] The multiple test modes can be set through detailed design information in the chip design document, including the internal circuit architecture, logic module composition, and connection relationships between modules. The test vectors can be set using binary code through the chip logic function truth table. The high-temperature aging test environment can be obtained by placing the chip in a high-temperature environment chamber and setting a specific high temperature value (e.g., 125°C) and duration (e.g., 168 hours). The temperature and humidity cycle test environment can be obtained by placing the chip in a temperature and humidity test chamber and cyclically switching the temperature and humidity of the test chamber.

[0115] In this embodiment of the invention, by selecting the thickness-optimized chip based on the quality inspection results, the selected chip can further ensure that the chips participating in the final packaging are of high quality, thus avoiding packaging failure or performance defects in the packaged product due to chip quality problems from the source.

[0116] Optionally, based on the quality inspection results, the thickness-optimized chips are selected by summarizing the results of various quality inspections, such as appearance inspection, circuit performance inspection, and reliability testing. All inspection data are integrated into a quality assessment report, with each chip corresponding to a detailed inspection result record. Data analysis methods are used to comprehensively analyze these results and determine which chips meet or exceed the standard requirements in various indicators according to the preset high-quality chip screening criteria.

[0117] S3. Query the material parameters of the selected chip, and based on the material parameters, configure the intermediate layer material of the selected chip. Using the intermediate layer material, coat the selected chip to obtain a coated chip. Using a pre-configured curing characteristic curve, cure the coated chip to obtain a cured chip. Identify the identification attributes and intermediate layer position of the cured chip. Based on the identification attributes and intermediate layer position, plan the stacking path of the cured chip to obtain a planned path. Based on the planned path, stack the cured chips to obtain a stacked chip.

[0118] This invention, through querying the material parameters of the selected chip and configuring the intermediate layer material based on these parameters, provides a comprehensive and in-depth understanding of the chip's various material characteristics, including key elements such as chemical composition, physical properties (e.g., hardness, coefficient of thermal expansion, dielectric constant), and surface state. This provides an accurate data foundation for the subsequent rational selection and configuration of the intermediate layer material, ensuring good compatibility between the intermediate layer and the chip in terms of physics, chemistry, and other aspects. Ultimately, the intermediate layer material is used to fix the selected chip.

[0119] The intermediate layer material refers to a functional material coated on the chip surface, situated between two or more chips to be stacked. Its purpose is to fill the tiny gaps between chips, enabling better connection and collaborative operation. It also plays multiple roles, such as electrical insulation, stress buffering, and enhanced bonding, thereby improving the stability, reliability, and electrical performance of the entire chip stacking package structure. It includes organic polymer materials such as epoxy resin and polyimide, as well as inorganic materials such as ceramics and metal oxides.

[0120] Optionally, the material parameters can be obtained from chip specification sheets, technical documents, and other materials provided by the chip manufacturer. The intermediate layer material can be selected by comprehensively considering the functional requirements of the intermediate layer in the entire packaging structure (such as providing electrical insulation, buffering stress, and enhancing the bonding force between chips) based on the selected chip material parameters found. For example, if the chip generates a large amount of heat during operation, an intermediate layer material with high thermal conductivity is needed to help dissipate heat; if the chip has stringent requirements for electrical insulation performance, a material with low dielectric constant and good insulation performance is selected.

[0121] It should be noted that after the intermediate layer material is prepared, corresponding pretreatment operations are required according to its characteristics. For example, for some materials that need to be stored under specific temperature and humidity conditions to ensure stable performance, the environmental conditions should be adjusted in advance to reach the optimal state. For powdered or granular materials, grinding, sieving and other operations may be required to ensure uniform particle size so that the subsequent coating operation can be carried out uniformly.

[0122] In this embodiment of the invention, the selected chip is coated with the intermediate layer material to obtain a coated chip that is covered by the intermediate layer material, forming an intermediate layer film of specific thickness and uniformity. This ensures that the intermediate layer material can fully perform its function in the packaging structure, such as providing an electrical insulation barrier or acting as a stress buffer layer.

[0123] As an embodiment of the present invention, the step of coating the selected chip with the intermediate layer material to obtain a coated chip includes: querying the material properties of the intermediate layer material and the chip size of the selected chip, configuring a suitable coating device, obtaining the coating accuracy requirements of the selected chip, setting the parameters of the coating device based on the coating accuracy requirements to obtain a debugging device, and using the debugging device to coat the selected chip to obtain a coated chip.

[0124] The material properties refer to the viscosity and flowability of the coating material corresponding to the selected chip. The coating precision requirements include, for example, a lower coating viscosity or the need for patterned coating in specific areas of the chip. The material properties can be obtained by consulting the material parameter table of the coating material corresponding to the selected chip.

[0125] Optionally, the coating device can be configured with a spin coater, screen printer, or spray coating equipment. The debugging device can be used to install and debug the selected coating equipment, and set key coating parameters according to the specific conditions of the selected intermediate layer material and chip. Taking a spin coater as an example, parameters such as rotation speed, acceleration time, and coating time need to be adjusted. Generally, a small amount of trial coating is performed first to observe the coating effect, such as the uniformity and thickness of the film, and the parameters are gradually optimized to achieve the ideal coating quality requirements.

[0126] Furthermore, in this embodiment of the invention, the coated chip is cured using a pre-configured curing characteristic curve. The resulting cured chip can better fix the chip position, enhance the bonding force between chips, and prevent problems such as chip displacement or loosening during subsequent use.

[0127] The pre-configured curing characteristic curve refers to the curing time curve of the chip coating material at different temperatures. The curing characteristic curve can be obtained in advance through experiments. Prepare multiple sets of identical intermediate layer material samples and place them under different combinations of curing conditions such as temperature and time for curing treatment. For example, set different isothermal temperatures (such as 80℃, 100℃, 120℃, etc.) and corresponding isothermal times (such as 1 hour, 2 hours, 3 hours, etc.). At the same time, monitor the changes in key performance indicators of the material during the curing process, such as the increase in hardness and the stability of dielectric constant. The curing characteristic curve of the material is plotted based on these data.

[0128] Optionally, the coated chip is cured using a pre-configured curing characteristic curve. The resulting cured chip can be cured using appropriate curing equipment selected based on the curing requirements of the intermediate layer material (e.g., heating method, temperature range, whether light irradiation is required). Common equipment includes thermal ovens, UV curing chambers, and infrared curing ovens. Based on the optimal curing conditions determined by the curing characteristic curve, the relevant parameters of the equipment are set, such as the heating rate, constant temperature, and constant temperature time for thermal ovens; for UV curing chambers, parameters such as UV intensity and irradiation time are set. The coated chip is then placed on the platform of the curing equipment, ensuring that the chips are neatly arranged and appropriately spaced to avoid mutual interference during curing. The curing equipment is then started, and the curing operation is performed according to the set parameters, causing the intermediate layer material to undergo a chemical reaction under the corresponding temperature and light conditions, transforming from a liquid or flowable state to a solid state, thus achieving curing.

[0129] The present invention, by identifying the identification attributes of the solidified chip and the position of the intermediate layer, helps to accurately distinguish different types and functions of chips during the stacking process, and to combine them in an orderly manner according to design requirements, avoiding packaging errors caused by chip confusion, ensuring the rationality and correctness of chip layout in the packaging structure, thereby achieving the expected functional and performance requirements.

[0130] The identification attributes refer to the chip's serial number, model number, pin layout features, and arrangement.

[0131] Optionally, the identification attributes can be acquired by using high-resolution optical microscopes, electron microscopes (selecting the appropriate microscope type according to the chip's precision requirements and size), or industrial cameras. The cured chip is placed on the stage of the device, and the focal length, lighting conditions, magnification, and other parameters of the device are adjusted to ensure that the image information of the chip surface and intermediate layer can be clearly obtained. At the same time, the contrast and brightness of the image are guaranteed to meet the requirements of subsequent analysis. Then, the acquired image is processed and analyzed by image analysis software (such as ImageJ, Image-Pro Plus, etc.) to identify the identification attributes of the cured chip. The position of the intermediate layer can also be obtained by analyzing with the help of image analysis software, so it will not be elaborated further.

[0132] This invention, through the identification attributes and the intermediate layer position, performs stacking path planning for the solidified chip. The planned path can optimize the entire stacking process in advance, clarify the operation trajectory of each chip at different stages, enable the stacking device to perform tasks in an orderly manner, reduce unnecessary repetitive operations, avoid collisions between chips, and improve the accuracy and speed of stacking.

[0133] As an embodiment of the present invention, the step of planning the stacking path of the solidified chip based on the identification attribute and the intermediate layer position to obtain the planned path includes: determining the stacking order of the solidified chip according to the identification attribute; determining the chip alignment method of the solidified chip during stacking according to the intermediate layer position; querying the device motion characteristics of the stacking device corresponding to the solidified chip; constructing the stacking constraints of the solidified chip based on the stacking order, the chip alignment method, and the device motion characteristics; constructing the initial stacking path of the solidified chip; performing preliminary screening on the initial stacking path based on the stacking constraints to obtain the filtered path; performing a global search on the filtered path using a pre-configured ant colony algorithm to obtain the search pheromone; and updating the search pheromone using the following formula to obtain the updated pheromone:

[0134]

[0135] in, This indicates an update of pheromones. This represents the decay coefficient of the search pheromone. This represents the concentration of pheromones searched along path i to path j at time t. This represents the newly added pheromone concentration, and T represents the time when the search for pheromones began.

[0136] Based on the updated pheromone, the probability value of each path in the filtering path is calculated, and the stacking path of the solidified chip is selected based on the probability value to obtain the planned path.

[0137] The motion characteristics refer to the limiting attributes of different chip stacking devices (such as robotic arm systems), such as their range of motion, speed of motion, and operable angles.

[0138] It should be explained that the solidified chips are scattered on a large plane and are stacked into a tight multi-layer structure. Therefore, it is necessary to analyze how to pick up each chip sequentially and place it to the target stacking position with the shortest movement distance. At this time, the chip's identification attributes such as number and model determine its order in the stacking structure, and the position of the intermediate layer on the chip determines the alignment method when adjacent chips are stacked. In order to achieve the shortest path, it is necessary to consider how to plan the optimal movement trajectory of the chip from the initial position to the stacking position under the condition of ensuring accurate alignment of the intermediate layer. For example, the intermediate layers of adjacent chips need to be completely overlapped and aligned. Therefore, when planning the path, it is necessary to avoid detours and unnecessary adjustment actions, so that the chip can move to the position that can be accurately aligned in the most direct way, thereby reducing unnecessary travel distance.

[0139] Optionally, the stacking constraints of the solidified chip, based on the stacking order, the chip alignment method, and the device motion characteristics, can be constructed by building constraints based on the device motion characteristics, such as analyzing motion range limitations: comprehensively understanding the motion range parameters of each moving part of the stacking device (such as a robotic arm, automated stacking machine, etc.). For example, the extension length of a robotic arm has maximum and minimum limits, and the rotation angle range of each joint is also determined. Based on this information, the operable area range constraint of the chip in space is defined. It is stipulated that the chip's pick-up and placement positions must be within the space that the device can effectively reach, preventing the planning of paths beyond the device's motion capabilities and avoiding situations where the device cannot reach the designated position for operation; considering speed and acceleration limitations: based on the device's motion speed and acceleration capabilities in different directions, speed and acceleration constraints are set during the chip's movement. For example, if the maximum moving speed of the device in the X-axis direction is defined as v1 and the maximum acceleration as a1, then when planning the chip's movement from the initial position to the target position along the X-axis... When moving along the axial direction, the speed variation and maximum speed must not exceed the corresponding limits to ensure that the equipment can operate the chip smoothly and safely, while also avoiding damage to the equipment or affecting the stacking accuracy due to unreasonable speed planning. Define the constraints for gripping and placement operations: For the specific methods and related parameters of the equipment gripping and placing the chip, formulate corresponding constraints. For example, if the equipment grips the chip using a vacuum chuck, specify the minimum and maximum suction range of the chuck to ensure stable gripping without damaging the chip. For placement operations, determine the required pressing depth and placement angle when the chip is placed at the target position to ensure that the chip can be accurately and stably placed in the stacking position, achieving a good stacking effect. Finally, integrate and summarize the various constraints constructed based on the stacking order, chip alignment method, and equipment motion characteristics to form a complete set of solidified chip stacking constraints. This set of constraints covers requirements ranging from time sequence and spatial alignment to equipment operation. These constraints must be strictly followed during the subsequent initial stacking path construction, screening, and optimization processes to ensure that the planned chip stacking path is feasible and meets actual production requirements. For example, the final stacking constraint set may include detailed and specific constraints such as: "Chips must be stacked in the order of model A - B - C; the angular deviation of chips around each axis during movement shall not exceed the specified value; the extension length of the robotic arm must be within the range of [L1, L2]; the pressing depth when placing chips is h centimeters..." This provides clear specifications and limitations for the entire chip stacking path planning.

[0140] The initial stacking path can be automatically planned by computer-aided design (CAD) software. Based on the stacking constraints, the initial stacking path is initially screened to obtain a filtered path. The initial stacking path can be checked against the stacking constraints one by one by a reinforcement learning algorithm. Paths that do not meet the constraints such as chip stacking order, alignment method, and device motion characteristics are removed. The remaining paths are the filtered paths. Based on the updated pheromone, the probability value of each path in the filtered path is calculated. Based on the probability value, the stacking path of the solidified chip is selected to obtain the planned path.

[0141] Furthermore, as an optional embodiment of the present invention, calculating the probability value of each path in the filtering path being selected based on the updated pheromone includes: calculating the probability value of each path in the filtering path being selected using the following formula:

[0142]

[0143] in, Represents the probability value. This indicates an update to pheromone concentration. Representing heuristic information, Factors indicating the importance of pheromones Factors representing the importance of heuristic information This represents the set of the next path that can be selected at the current node k, i.e., the set of all candidate paths that satisfy the constraints.

[0144] Optionally, the step of selecting the stacking path of the solidified chip based on the probability value to obtain the planned path can be achieved by selecting the path with a higher probability value, such as the path corresponding to a probability greater than 80%. The specific selection needs to be combined with the actual application.

[0145] The embodiments of the present invention stack the solidified chips based on the planned path to obtain stacked chips. This stacked chip stack can ensure the accuracy and quality of the stacking, reduce problems such as chip alignment errors and poor connection caused by human operation errors or insufficient equipment accuracy, improve the stability and reliability of the packaging structure, and lay the foundation for the final packaged product to have good electrical performance, mechanical performance and long-term use stability.

[0146] S4. Query the stacking structure of the stacked chip, and based on the stacking structure, perform three-dimensional modeling of the stacked chip to obtain a stacked chip model. Using the stacked chip model, perform dispensing path planning for the stacked chip to obtain a dispensing path. Based on the dispensing path, perform chip reinforcement on the stacked chip to obtain a reinforced chip.

[0147] In this embodiment of the invention, by querying the stacking structure of the stacked chip and performing a three-dimensional model of the stacked chip based on the stacking structure, the resulting stacked chip model can help analyze the overall performance characteristics of the stacked chip and potential weaknesses. For example, by understanding the chip stacking method, its performance in terms of heat conduction and electrical connection can be predicted, providing a basis for optimizing chip performance. At the same time, it can also identify reliability risks that may be caused by unreasonable stacking structure in advance.

[0148] Optionally, the stacked structure can be identified by querying the design drawings corresponding to the stacked chips. For example, for a multilayer memory chip, the design drawings will specify the length and width of each layer of memory chip, the distribution of memory cells, and the position of the connection pins between it and other functional chips (such as control chips). The manufacturing process specification will mention what kind of insulating material is used for the intermediate layer and how the coating and curing processes are used to achieve electrical isolation and physical connection between the chips. The assembly process record will specify which layer of chip is placed first and whether there are specific alignment marks. The stacked chip model can be constructed using SolidWorks tools.

[0149] Furthermore, in this embodiment of the invention, by utilizing the stacked chip model to plan the dispensing path for the stacked chips, the dispensing path can effectively control the amount of adhesive used, avoid waste, reduce production costs, and at the same time reduce electrical or thermal performance problems such as short circuits and poor heat dissipation caused by uneven adhesive distribution or excessive use. This ensures the normal operation of the stacked chips and the stability of overall performance, which is of great significance for improving product quality and market competitiveness.

[0150] As an embodiment of the invention, the step of using the stacked chip model to plan the dispensing path for the stacked chip to obtain the dispensing path includes: constructing an initial dispensing path for the stacked chip; creating a dispensing simulation scene for the stacked chip based on the stacked chip model; using the initial dispensing path as the simulation animation trajectory of the stacked chip; performing dispensing simulation on the stacked chip based on the dispensing simulation scene and the simulation animation trajectory; and determining the dispensing path for the stacked chip based on the simulation results of the dispensing simulation.

[0151] Optionally, the operating principle and steps of the initial dispensing path are the same for planning the stacking path of the cured chip, so the principle of obtaining the planned path is not repeated. The step of creating a dispensing simulation scene for the stacked chip based on the stacked chip model can be achieved by importing the constructed 3D model of the stacked chip into dispensing simulation software (such as RoboDK). In the process of setting up a dispensing equipment model, adhesive properties, and other relevant parameters in the software, a virtual scene simulating a real dispensing operation is built. The initial dispensing path is used as the simulation animation trajectory of the stacked chips. In the dispensing simulation software, the previously constructed initial dispensing path is imported and associated with the stacked chip model in the scene. Animation parameters such as the path movement speed are set to make it the trajectory for animation display. According to the dispensing simulation scene and the simulation animation trajectory, the dispensing simulation of the stacked chips is performed by starting the simulation function of the dispensing simulation software. Based on the set scene, trajectory, and corresponding physical simulation algorithm, the dynamic process of the dispensing equipment dispensing adhesive to the chip along the trajectory is simulated, and the distribution of adhesive on the chip is observed. Based on the simulation results of the dispensing simulation, the dispensing path of the stacked chips is determined. Problems such as uneven adhesive coverage and unreasonable paths (such as intersections or excessive lengths) that occur in the simulation can be analyzed. The initial path is adjusted and optimized in the software, and repeated simulation verification is performed until a final dispensing path that meets the requirements is obtained.

[0152] Furthermore, in this embodiment of the invention, the stacked chips are reinforced based on the dispensing path. The reinforced chips maintain the structural integrity of the stacked chips through effective chip reinforcement, ensuring good electrical connection and thermal conductivity between chips. This ensures that the chips can continuously and stably perform their functions during long-term use, which plays an important supporting role in the performance and lifespan of the entire electronic product, and helps to improve the overall quality of the product and user satisfaction.

[0153] S5. Query the 3D model and circuit layout information of the rugged chip to perform internal interconnection of the rugged chip to obtain a link chip. Query the stacking parameters and filling requirements of the link chip to perform preliminary packaging of the link chip to obtain a preliminary packaged chip. Identify the process parameters of the preliminary packaged chip. Based on the process parameters, perform shell injection molding on the preliminary packaged chip to obtain a packaged chip.

[0154] In this embodiment of the invention, by querying the three-dimensional model and circuit layout information of the rugged chip, the internal interconnection of the rugged chip is performed. The resulting interconnected chips can help to analyze and predict the electrical performance and signal transmission characteristics after interconnection in advance, so as to optimize the interconnection scheme according to actual needs, improve the overall function and performance of the chip, and enable it to better meet the requirements of application scenarios for chip computing speed, signal integrity, etc.

[0155] Optionally, the interconnect chip can be constructed by building interconnects inside the chip according to the layout using micro-nano fabrication technology (such as photolithography, electron beam exposure combined with metal deposition process) to achieve internal interconnection and obtain the interconnect chip.

[0156] Furthermore, in this embodiment of the invention, by querying the stacking parameters and filling requirements of the linked chip, the linked chip is initially packaged. The resulting pre-packaged chip can optimize the chip's heat dissipation performance, enhance the bonding force between the chip and the package shell, and at the same time provide a certain degree of protection for the chip, preventing damage to the chip from external environmental factors (such as moisture, dust, etc.) and extending the chip's service life.

[0157] The stacking parameters refer to a series of key dimensions and layout data related to the physical structure of the chip during the multi-layer stacking process. The filling requirements refer to the specific regulations on the materials, related characteristics, dosage, and filling positions that need to be filled in the gaps between the chip and the substrate and inside the chip during the chip packaging process in order to meet the requirements of chip performance, protection and structural stability.

[0158] The optional preliminary packaged chip can be obtained by finding the stacking parameters and filling requirements of the linked chips in the chip design document, and then using flip chip packaging and other processes (in conjunction with bottom filling equipment for filling and soldering equipment to connect the chip to the substrate), and operating according to the parameters and requirements to complete the preliminary packaging.

[0159] It should be further noted that the process parameters of the preliminary packaged chip can be obtained by testing the preliminary packaged chip using professional testing equipment (such as calipers to measure dimensions, thermal analysis instruments to measure thermal performance, etc.).

[0160] Based on the aforementioned process parameters, the pre-packaged chip undergoes shell injection molding to obtain the packaged chip. According to the identified process parameters, a suitable injection mold and injection molding material (such as commonly used engineering plastics like ABS and PP) are selected. The pre-packaged chip is placed at a specific position in the injection mold. Using an injection molding machine, molten injection material is injected into the mold cavity according to the set mold temperature, injection pressure, injection speed, and other process parameters, encapsulating the pre-packaged chip. After cooling and solidification, a robust shell is formed, ultimately obtaining the packaged chip. The final packaged chip can be obtained by performing shell injection molding using an injection molding machine according to the set parameters.

[0161] Example 2:

[0162] like Figure 2 The diagram shown is a system functional block diagram of an embodiment of the present invention for implementing an ultra-thin multilayer memory chip stacking and packaging method.

[0163] The ultra-thin multilayer memory chip stacking and packaging system 200 described in this invention can be installed in electronic devices. Depending on the functions implemented, the ultra-thin multilayer memory chip stacking and packaging system may include a chip sorting module 201, a chip selection module 202, a chip stacking module 203, a chip hardening module 204, and a chip packaging module 205. The modules described in this invention can also be referred to as units, which are a series of computer program segments that can be executed by the processor of an electronic device and perform a fixed function, and are stored in the memory of the electronic device.

[0164] In this embodiment of the invention, the functions of each module / unit are as follows:

[0165] The chip classification module 201 is used to acquire the memory chip to be packaged, perform optical scanning on the memory chip to be packaged to obtain a scanned image, analyze the surface defects and circuit integrity of the memory chip to be packaged using the scanned image, classify the memory chip to be packaged based on the surface defects and circuit integrity, extract the chips that meet the preset quality after chip quality classification to obtain the target chip, identify the chip thickness and pad distribution of the target chip using the scanned image, and further classify the target chip based on the chip thickness and pad distribution to obtain multiple groups of chips;

[0166] The chip selection module 202 is used to measure the chip thickness of each group of chips in the plurality of chips using a pre-configured thickness sensor to obtain thickness measurement data, construct an optimal thickness range for the plurality of chips using the thickness measurement data, optimize the thickness of the plurality of chips based on the optimal thickness range to obtain a thickness-optimized chip, perform quality inspection on the thickness-optimized chip, and select chips from the thickness-optimized chip based on the quality inspection results to obtain a selected chip.

[0167] The chip stacking module 203 is used to query the material parameters of the selected chip, configure the intermediate layer material of the selected chip based on the material parameters, coat the selected chip with the intermediate layer material to obtain a coated chip, cure the coated chip with a pre-configured curing characteristic curve to obtain a cured chip, identify the identification attributes and intermediate layer position of the cured chip, plan the stacking path of the cured chip based on the identification attributes and intermediate layer position to obtain a planned path, and stack the cured chips based on the planned path to obtain a stacked chip.

[0168] The chip hardening module 204 is used to query the stacking structure of the stacked chips, and based on the stacking structure, perform three-dimensional modeling of the stacked chips to obtain a stacked chip model. Using the stacked chip model, it performs dispensing path planning on the stacked chips to obtain a dispensing path. Based on the dispensing path, it performs chip hardening on the stacked chips to obtain a hardened chip.

[0169] The chip packaging module 205 is used to query the three-dimensional model and circuit layout information of the rugged chip to perform internal interconnection of the rugged chip to obtain a link chip, query the stacking parameters and filling requirements of the link chip to perform preliminary packaging of the link chip to obtain a preliminary packaged chip, identify the process parameters of the preliminary packaged chip, and perform shell injection molding on the preliminary packaged chip based on the process parameters to obtain a packaged chip.

[0170] In detail, the modules in the ultra-thin multilayer memory chip stacking packaging system 200 described in this embodiment of the invention employ the same methods as described above during use. Figure 1 The method is the same as the ultra-thin multilayer memory chip stacking and packaging method described in the article, and can produce the same technical effect, so it will not be repeated here.

[0171] In the several embodiments provided by this invention, it should be understood that the disclosed systems and methods can be implemented in other ways. For example, the system embodiments described above are merely illustrative; for instance, the division of modules is only a logical functional division, and other division methods may be used in actual implementation.

[0172] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0173] Furthermore, the functional modules in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or in the form of hardware plus software functional modules.

[0174] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0175] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0176] The above description is merely a specific embodiment of the present invention, enabling those skilled in the art to understand or implement the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features of the invention herein.

Claims

1. A method for stacking and packaging ultra-thin multilayer memory chips, characterized in that, The method includes: A memory chip to be packaged is obtained, and the memory chip to be packaged is optically scanned to obtain a scanned image. The surface defects and circuit integrity of the memory chip to be packaged are analyzed using the scanned image. Based on the surface defects and circuit integrity, the memory chip to be packaged is classified into chip quality categories. Chips that meet the preset quality after chip quality classification are extracted to obtain target chips. The chip thickness and pad distribution of the target chips are identified using the scanned image. Based on the chip thickness and pad distribution, the target chips are further classified to obtain multiple groups of chips. Using a pre-configured thickness sensor, the chip thickness of each group of chips in the multiple groups of chips is measured to obtain thickness measurement data. Using the thickness measurement data, an optimal thickness range for the multiple groups of chips is constructed. Based on the optimal thickness range, the thickness of the multiple groups of chips is optimized to obtain thickness-optimized chips. The thickness-optimized chips are subjected to quality inspection. Based on the inspection results, the thickness-optimized chips are further selected to obtain selected chips. The material parameters of the selected chip are queried, and based on the material parameters, the intermediate layer material of the selected chip is configured. The selected chip is coated with the intermediate layer material to obtain a coated chip. The coated chip is cured using a pre-configured curing characteristic curve to obtain a cured chip. The identification attributes and intermediate layer positions of the cured chip are identified. Based on the identification attributes and intermediate layer positions, a stacking path is planned for the cured chip to obtain a planned path. Based on the planned path, the cured chips are stacked to obtain a stacked chip. The stacking structure of the stacked chip is queried, and a three-dimensional model of the stacked chip is performed based on the stacking structure to obtain a stacked chip model. Using the stacked chip model, a dispensing path is planned for the stacked chip to obtain a dispensing path. Based on the dispensing path, the stacked chip is reinforced to obtain a reinforced chip. The three-dimensional model and circuit layout information of the rugged chip are queried to perform internal interconnection of the rugged chip to obtain a link chip. The stacking parameters and filling requirements of the link chip are queried to perform preliminary packaging of the link chip to obtain a preliminary packaged chip. The process parameters of the preliminary packaged chip are identified. Based on the process parameters, the preliminary packaged chip is subjected to shell injection molding to obtain a packaged chip.

2. The ultra-thin multilayer memory chip stacking and packaging method as described in claim 1, characterized in that, The step of analyzing the surface defects and circuit integrity of the memory chip to be packaged using the scanned image includes: The scanned image is converted to grayscale to obtain a grayscale image; Perform image surface detection on the grayscale image to determine the surface defect contours of the memory chip to be packaged; The surface defect contour is processed to obtain a refined defect state. The refined defect state is quantified to determine the surface defect degree of the memory chip to be packaged. The circuit wiring features of the memory chip to be packaged are identified using the scanned image; The circuit integrity of the memory chip to be packaged is identified using the circuit wiring characteristics.

3. The ultra-thin multilayer memory chip stacking and packaging method as described in claim 1, characterized in that, The step of identifying the chip thickness and pad distribution of the target chip using the scanned image includes: Extract the vertical boundary contour region of the scanned image; Calculate the vertical pixel value of the vertical boundary contour region; The chip thickness of the target chip is obtained by performing size conversion on the vertical pixel values; Target detection is performed on the scanned image to obtain the detected target; Identify the feature points of the target being detected; Based on the feature points, the shape, size, and distance characteristics of the pads corresponding to the target chip are analyzed, and the number and arrangement of the pads are counted to determine the pad distribution status.

4. The ultra-thin multilayer memory chip stacking and packaging method as described in claim 3, characterized in that, The identification of feature points of the detected target includes: Construct the scale space of the target to be detected; The target object is marked with key points in the scale space to obtain marked key points; After assigning directions to the marked key points, feature points are determined using the following formula: in, Feature points This represents the image gradient value of the scanned image corresponding to the detected target. Mark the direction of key points. Indicates a scanned image. , , , Represents the origin of the scanned image in scale space. The nearest neighboring points.

5. The ultra-thin multilayer memory chip stacking and packaging method as described in claim 1, characterized in that, The quality inspection of the thickness-optimized chip includes: Acquire microscopic images of the thickness-optimized chip; Identify the refinement features of the microscopic image; The thickness-optimized chip is subjected to appearance inspection using the refined features. Construct multiple test modes and test vectors for the thickness-optimized chip; After inputting a preset electrical signal into the thickness optimization chip, the circuit performance of the thickness optimization chip is tested according to the multiple test modes and test vectors. Configure a high-temperature aging test environment and a temperature and humidity cycling test environment for the thickness-optimized chip, so as to conduct reliability tests on the thickness-optimized chip using the high-temperature aging test environment and the temperature and humidity cycling test environment; After the appearance inspection, circuit performance inspection and reliability test are completed, the quality inspection of the thickness-optimized chip is completed.

6. The ultra-thin multilayer memory chip stacking and packaging method as described in claim 1, characterized in that, The process of coating the selected chip with the intermediate layer material to obtain a coated chip includes: The material properties of the intermediate layer material and the chip size of the selected chip are queried in order to configure a suitable coating device; Obtain the coating precision requirements of the selected chips; Based on the coating accuracy requirements, the parameters of the coating device are set to obtain the debugging device; Using the aforementioned debugging device, the selected chip is coated with a material to obtain a coated chip.

7. The ultra-thin multilayer memory chip stacking and packaging method as described in claim 1, characterized in that, The stacking path planning for the solidified chip based on the identification attribute and the intermediate layer position, to obtain the planned path, includes: The stacking order of the cured chips is determined based on the identification attributes; The chip alignment method of the solidified chip during stacking is determined based on the position of the intermediate layer; Query the device motion characteristics of the stacking equipment corresponding to the solidified chip; Based on the stacking order, the chip alignment method, and the device motion characteristics, the stacking constraints of the solidified chips are constructed. Construct the initial stacking path for the solidified chip; Based on the stacking constraints, the initial stacking paths are initially filtered to obtain filtered paths; Using a pre-configured ant colony algorithm, a global search is performed on the filtering path to obtain the search pheromone; The search pheromone is updated using the following formula to obtain the updated pheromone: in, This indicates an update of pheromones. This represents the decay coefficient of the search pheromone. This represents the concentration of pheromones searched along path i to path j at time t. This represents the newly added pheromone concentration, and T represents the time when the search for pheromones began. Based on the updated pheromone, calculate the probability value of each path being selected in the filtering path; Based on the probability value, the stacking path of the solidified chip is selected to obtain the planned path.

8. The ultra-thin multilayer memory chip stacking and packaging method as described in claim 7, characterized in that, The step of calculating the probability value of each path being selected in the filtering path based on the updated pheromone includes: The probability of each path being selected in the filtering path is calculated using the following formula: in, Represents the probability value. This indicates an update to pheromone concentration. Representing heuristic information, Factors indicating the importance of pheromones Factors representing the importance of heuristic information This represents the set of the next path that can be selected at the current node k, i.e., the set of all candidate paths that satisfy the constraints.

9. The ultra-thin multilayer memory chip stacking and packaging method as described in claim 1, characterized in that, The step of using the stacked chip model to plan the dispensing path for the stacked chips and obtaining the dispensing path includes: Construct the initial dispensing path for the stacked chips; Based on the stacked chip model, create a dispensing simulation scenario for the stacked chips; The initial dispensing path is used as the simulation animation trajectory of the stacked chips; Based on the dispensing simulation scenario and the simulation animation trajectory, dispensing simulation is performed on the stacked chips; The dispensing path for the stacked chips is determined based on the simulation results of the dispensing simulation.

10. An ultra-thin multilayer memory chip stacking and packaging system, characterized in that, The system includes: The chip classification module is used to acquire memory chips to be packaged, perform optical scanning on the memory chips to be packaged to obtain scanned images, analyze the surface defects and circuit integrity of the memory chips to be packaged using the scanned images, classify the memory chips to be packaged based on the surface defects and circuit integrity, extract chips that meet the preset quality after chip quality classification to obtain target chips, identify the chip thickness and pad distribution of the target chips using the scanned images, and further classify the target chips based on the chip thickness and pad distribution to obtain multiple groups of chips; The chip selection module is used to measure the chip thickness of each group of chips in the multiple groups of chips using a pre-configured thickness sensor to obtain thickness measurement data. Using the thickness measurement data, an optimal thickness range for the multiple groups of chips is constructed. Based on the optimal thickness range, the thickness of the multiple groups of chips is optimized to obtain a thickness-optimized chip. The thickness-optimized chip is subjected to quality inspection. Based on the inspection results, the thickness-optimized chip is selected to obtain a selected chip. The chip stacking module is used to query the material parameters of the selected chip, configure the intermediate layer material of the selected chip based on the material parameters, coat the selected chip with the intermediate layer material to obtain a coated chip, cure the coated chip with a pre-configured curing characteristic curve to obtain a cured chip, identify the identification attributes and intermediate layer position of the cured chip, plan the stacking path of the cured chip based on the identification attributes and intermediate layer position to obtain a planned path, and stack the cured chips based on the planned path to obtain a stacked chip. The chip hardening module is used to query the stacking structure of the stacked chips, and based on the stacking structure, perform three-dimensional modeling of the stacked chips to obtain a stacked chip model. Using the stacked chip model, the module performs dispensing path planning for the stacked chips to obtain a dispensing path. Based on the dispensing path, the module performs chip hardening on the stacked chips to obtain a hardened chip. The chip packaging module is used to query the three-dimensional model and circuit layout information of the rugged chip to perform internal interconnection of the rugged chip to obtain a link chip, query the stacking parameters and filling requirements of the link chip to perform preliminary packaging of the link chip to obtain a preliminary packaged chip, identify the process parameters of the preliminary packaged chip, and perform shell injection molding on the preliminary packaged chip based on the process parameters to obtain a packaged chip.

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