A semiconductor radio frequency filter with a three-dimensional inductor structure and its fabrication method

Abstract

The application discloses a semiconductor radio frequency filter adopting a three-dimensional inductor structure and a manufacturing method thereof, and relates to the technical field of filtering. The semiconductor radio frequency filter comprises a first substrate as a carrier, a bulk acoustic wave resonator on the first substrate, and a three-dimensional inductor structure, wherein the three-dimensional inductor structure comprises a second substrate and a three-dimensional inductor arranged in the second substrate, and the second substrate is multiplexed as a cover plate of the bulk acoustic wave resonator. Therefore, an additional substrate as a cover plate is not needed for the bulk acoustic wave resonator, but the carrier (i.e. the second substrate) of the three-dimensional inductor is directly used as the protective cover plate of the bulk acoustic wave resonator, the requirement for an additional cover plate structure is eliminated, the layer structure of the semiconductor radio frequency filter is simplified, the semiconductor radio frequency filter is more compact, and the miniaturization process of the semiconductor radio frequency filter is promoted. Furthermore, the problems of the semiconductor radio frequency filter integrated with the bulk acoustic wave resonator and the inductor in the prior art in the miniaturization are solved.

Description

Technical Field

[0001] This application relates to the field of filtering technology, and in particular to a semiconductor radio frequency filter employing a three-dimensional inductor structure and its fabrication method. Background Technology

[0002] As a core component of wireless communication systems, the performance improvement and structural optimization of semiconductor radio frequency (RF) filters are crucial to meeting the demands of modern communication technologies. With the rapid development of wireless communication technology, this importance is increasingly evident. Traditional semiconductor RF filter designs typically employ a structure combining a bulk acoustic wave (BAW) resonator with an inductor.

[0003] In this structural design, a first substrate is provided as the carrier of the entire structure. The bulk acoustic wave resonator is formed on the first substrate, involving the deposition of multiple layers of material (including electrode layers and piezoelectric material layers) on the substrate, and the resonant cavity is carefully formed through specific process steps (such as photolithography, etching, etc.). Next, a planar inductor is placed above or near the bulk acoustic wave resonator. A common practice is to add an additional dielectric layer or a second substrate above the resonator, and then fabricate the planar inductor, which consists of metal coils, oxide layers, etc., on this layer. Finally, in order to protect the resonator and inductor structure below and reduce electromagnetic interference, an additional cover plate is placed above the planar inductor.

[0004] As a crucial component in millimeter-wave communication systems, the miniaturization of semiconductor RF filters has become a significant research focus. However, in the aforementioned traditional semiconductor RF filter designs, although the combination of planar inductors and bulk acoustic wave resonators brings performance improvements, the requirement for an additional cover plate structure above the planar inductor structure increases the overall thickness and weight of the filter, limiting its miniaturization potential.

[0005] Currently, there is no effective solution to the miniaturization challenges faced by existing semiconductor RF filters that integrate bulk acoustic wave resonators and inductors. Therefore, exploring novel semiconductor RF filter structures to achieve more efficient and compact designs has become an urgent research need. Summary of the Invention

[0006] Embodiments of this disclosure provide a semiconductor radio frequency filter employing a three-dimensional inductor structure and a method for fabricating the same. This addresses at least the miniaturization challenges faced by existing semiconductor radio frequency filters that integrate bulk acoustic wave resonators and inductors.

[0007] According to one aspect of the present disclosure, a semiconductor radio frequency filter employing a three-dimensional inductor structure is provided, comprising: a first substrate serving as a carrier, a bulk acoustic wave resonator located on the first substrate, and a three-dimensional inductor structure, wherein the three-dimensional inductor structure includes a second substrate and a three-dimensional inductor disposed within the second substrate; wherein the second substrate is multiplexed as a cover plate for the bulk acoustic wave resonator.

[0008] Optionally, the bulk acoustic wave resonator includes a piezoelectric layer, a first electrode, a second electrode, and a resonant cavity; wherein the first electrode is located on the side of the piezoelectric layer away from the first substrate; the second electrode is located on the side of the piezoelectric layer close to the first substrate; and the resonant cavity is formed between the piezoelectric layer and the first substrate.

[0009] Optionally, the 3D inductor includes a first 3D inductor, and the semiconductor RF filter further includes: a first dielectric layer located on the side of the second substrate near the piezoelectric layer; a third electrode located on the side of the first dielectric layer away from the second substrate; a second dielectric layer located on the side of the first dielectric layer away from the second substrate and covering the third electrode; and a fourth electrode, a portion of which penetrates the second dielectric layer and the first dielectric layer and is electrically connected to the first 3D inductor, and another portion extends to a surface covering the side of the second dielectric layer away from the second substrate; wherein the third electrode, the second dielectric layer, and the fourth electrode constitute a first capacitor.

[0010] Optionally, the three-dimensional inductor includes a second three-dimensional inductor, and the semiconductor RF filter further includes: a fifth electrode, a portion of which penetrates the first dielectric layer and is electrically connected to the second three-dimensional inductor, and another portion which extends to cover the surface of the first dielectric layer away from the second substrate; and a sixth electrode located on the side of the second dielectric layer near the piezoelectric layer; wherein the second dielectric layer covers the fifth electrode, and the fifth electrode, the second dielectric layer, and the sixth electrode constitute a second capacitor.

[0011] Optionally, the semiconductor radio frequency filter further includes: a first conductive layer electrically connected to the first electrode and bonded to the fourth electrode; and a second conductive layer electrically connected to the second electrode and bonded to the sixth electrode.

[0012] Optionally, the semiconductor radio frequency filter further includes a seed layer located on the surface of the first electrode away from the piezoelectric layer; the first electrode includes a first portion and a second portion separated from each other, the seed layer includes a third portion and a fourth portion separated from each other, the first portion corresponds to the third portion, and the second portion corresponds to the fourth portion; and the first conductive layer penetrates the third portion of the seed layer and is electrically connected to the first portion of the first electrode; the second conductive layer sequentially penetrates the fourth portion of the seed layer, the second portion of the first electrode, and the piezoelectric layer and is electrically connected to the second electrode.

[0013] Optionally, the semiconductor radio frequency filter further includes: a third dielectric layer located on the surface of the second electrode away from the piezoelectric layer; a sacrificial layer located on the surface of the third dielectric layer away from the piezoelectric layer; a cutoff boundary layer located on the surface of the sacrificial layer away from the third dielectric layer; a bonding layer located on the side of the cutoff boundary layer away from the third dielectric layer; and the first conductive layer sequentially penetrates the first substrate, the bonding layer, the cutoff boundary layer, the sacrificial layer, and the piezoelectric layer and is electrically connected to the first electrode; the second conductive layer sequentially penetrates the first substrate, the bonding layer, the cutoff boundary layer, the sacrificial layer, and the third dielectric layer and is electrically connected to the second electrode.

[0014] Optionally, the 3D inductor includes a second 3D inductor, and the semiconductor RF filter further includes: a first dielectric layer located on the side of the second substrate near the piezoelectric layer; a fifth electrode, a portion of which penetrates the first dielectric layer and is electrically connected to the second 3D inductor, and another portion extending to cover the surface of the first dielectric layer away from the second substrate; a second dielectric layer located on the side of the first dielectric layer near the piezoelectric layer and covering the fifth electrode; and a sixth electrode located on the side of the second dielectric layer near the piezoelectric layer; wherein the fifth electrode, the second dielectric layer, and the sixth electrode constitute a second capacitor.

[0015] According to another aspect of the present disclosure, a method for fabricating a semiconductor radio frequency filter employing a three-dimensional inductor structure is also provided, comprising: providing a first substrate as a carrier; forming a bulk acoustic wave resonator on one side of the first substrate; providing a second substrate and arranging a three-dimensional inductor within the second substrate; and covering the second substrate on the side of the bulk acoustic wave resonator away from the first substrate to form a cover plate for the bulk acoustic wave resonator.

[0016] Optionally, the bulk acoustic wave resonator includes a piezoelectric layer, a first electrode, a second electrode, and a resonant cavity; wherein the first electrode is located on the side of the piezoelectric layer away from the first substrate; the second electrode is located on the side of the piezoelectric layer close to the first substrate; and the resonant cavity is formed between the piezoelectric layer and the first substrate; the 3D inductor includes a first 3D inductor, and the fabrication method further includes: fabricating a first dielectric layer, the first dielectric layer being located on the side of the second substrate close to the piezoelectric layer; fabricating a third electrode, the third electrode being located on the side of the first dielectric layer away from the second substrate; fabricating a second dielectric layer, the second dielectric layer being located on the side of the first dielectric layer away from the second substrate and covering the third electrode; and fabricating a fourth electrode, a portion of the fourth electrode penetrating... The third electrode, the second dielectric layer, and the fourth electrode form a first capacitor; and the third electrode, the second dielectric layer, and the fourth electrode constitute a first capacitor; and the third electrode includes a second three-dimensional inductor. The fabrication method further includes: fabricating a fifth electrode, a portion of which penetrates the first dielectric layer and is electrically connected to the second three-dimensional inductor, and another portion extending to a surface covering the first dielectric layer away from the second substrate; and fabricating a sixth electrode, which is located on the side of the second dielectric layer near the piezoelectric layer; wherein the second dielectric layer covers the fifth electrode, and the fifth electrode, the second dielectric layer, and the sixth electrode constitute a second capacitor.

[0017] Optionally, the fabrication method further includes: fabricating a first conductive layer, the first conductive layer being electrically connected to the first electrode and bonded to the fourth electrode; and fabricating a second conductive layer, the second conductive layer being electrically connected to the second electrode and bonded to the sixth electrode.

[0018] Optionally, the semiconductor radio frequency filter further includes: a seed layer located on the surface of the first electrode away from the piezoelectric layer; the first electrode includes a first portion and a second portion separated from each other, the seed layer includes a third portion and a fourth portion separated from each other, the first portion corresponding to the third portion, and the second portion corresponding to the fourth portion; and the first conductive layer penetrating the third portion of the seed layer and electrically connected to the first portion of the first electrode; the second conductive layer sequentially penetrating the fourth portion of the seed layer, the second portion of the first electrode, and the piezoelectric layer and electrically connected to the second electrode; or a third dielectric layer located on the surface of the second electrode away from the piezoelectric layer; a sacrificial layer located on the surface of the third dielectric layer away from the piezoelectric layer; a cutoff boundary layer located on the surface of the sacrificial layer away from the third dielectric layer; a bonding layer located on the side of the cutoff boundary layer away from the third dielectric layer; and the first conductive layer sequentially penetrating the first substrate, the bonding layer, the cutoff boundary layer, the sacrificial layer, and the piezoelectric layer and electrically connected to the first electrode; the second conductive layer sequentially penetrating the first substrate, the bonding layer, the cutoff boundary layer, the sacrificial layer, and the third dielectric layer and electrically connected to the second electrode.

[0019] In the semiconductor RF filter and its fabrication method using a three-dimensional inductor structure proposed in this application, the semiconductor RF filter includes a first substrate as a carrier, a bulk acoustic wave resonator located on the first substrate, and a three-dimensional inductor structure. The three-dimensional inductor structure includes a second substrate and a three-dimensional inductor disposed within the second substrate, and the second substrate is reused as a cover plate for the bulk acoustic wave resonator. Therefore, there is no need to add an additional substrate as a cover plate for the bulk acoustic wave resonator; instead, the carrier of the three-dimensional inductor (i.e., the second substrate) is directly used as a protective cover plate for the bulk acoustic wave resonator, eliminating the need for an additional cover plate structure, simplifying the layer structure of the semiconductor RF filter, making it more compact, and promoting the miniaturization process of semiconductor RF filters. This solves the miniaturization problems faced by existing semiconductor RF filters integrating bulk acoustic wave resonators and inductors. Attached Figure Description

[0020] The accompanying drawings, which are included to provide a further understanding of this disclosure and form part of this application, illustrate exemplary embodiments of this disclosure and are used to explain this disclosure, but do not constitute an undue limitation of this disclosure. In the drawings:

[0021] Figures 1-26 This is a schematic diagram of the various structures in the fabrication process of the semiconductor radio frequency filter with a three-dimensional inductor structure provided in Embodiment 1 of this application.

[0022] Figures 27-39This is a schematic diagram of the various structures in the fabrication process of the semiconductor radio frequency filter with a three-dimensional inductor structure provided in Embodiment 2 of this application. Detailed Implementation

[0023] To enable those skilled in the art to better understand the technical solutions of this disclosure, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this disclosure.

[0024] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this disclosure described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0025] Secondly, this application provides a detailed description in conjunction with schematic diagrams. When detailing the embodiments of this application, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged, not adhering to the usual scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of this application. In addition, actual fabrication should include three-dimensional spatial dimensions of length, width, and depth.

[0026] As described in the background section, miniaturization of semiconductor RF filters, as a crucial component in millimeter-wave communication systems, has become an important research direction. However, in traditional semiconductor RF filter designs, although the combination of planar inductors and bulk acoustic wave resonators brings performance improvements, the need for an additional cover plate structure on top of the planar inductor structure increases the overall thickness and weight of the filter, limiting its miniaturization potential.

[0027] In view of this, embodiments of this application provide a semiconductor radio frequency filter with a three-dimensional inductor structure and a method for manufacturing the same. The carrier of the three-dimensional inductor (i.e., the second substrate) is directly used as a protective cover for the bulk acoustic wave resonator, eliminating the need for an additional cover structure, simplifying the layer structure of the semiconductor radio frequency filter, making it more compact, and promoting the miniaturization process of semiconductor radio frequency filters.

[0028] The semiconductor radio frequency filter employing a three-dimensional inductor structure and its fabrication method provided in this application will be described below with reference to specific embodiments. For ease of understanding, this application will first describe the fabrication method of the semiconductor radio frequency filter employing a three-dimensional inductor structure.

[0029] The method for fabricating a semiconductor radio frequency filter with a three-dimensional inductor structure provided in this application includes: providing a first substrate as a carrier; forming a bulk acoustic wave resonator on one side of the first substrate; providing a second substrate and arranging a three-dimensional inductor in the second substrate; and covering the bulk acoustic wave resonator on the side away from the first substrate with the second substrate to form a cover plate for the bulk acoustic wave resonator.

[0030] Therefore, there is no need to add an additional substrate as a cover plate for the bulk acoustic wave resonator. Instead, the carrier of the three-dimensional inductor (i.e., the second substrate) is directly used as the protective cover plate for the bulk acoustic wave resonator, eliminating the need for an additional cover plate structure, simplifying the layer structure of the semiconductor RF filter, making it more compact, and promoting the miniaturization process of semiconductor RF filters. This solves the miniaturization problems faced by existing semiconductor RF filters that integrate bulk acoustic wave resonators and inductors.

[0031] It should be noted that, in this embodiment, the semiconductor radio frequency filter employing a three-dimensional inductor structure includes: a first substrate serving as a carrier, a bulk acoustic wave resonator located on the first substrate, and a three-dimensional inductor structure, wherein the three-dimensional inductor structure includes a second substrate and a three-dimensional inductor disposed within the second substrate; wherein the second substrate is reused as a cover plate for the bulk acoustic wave resonator.

[0032] The semiconductor radio frequency filter with a three-dimensional inductor structure and its fabrication method provided in this application are described below with reference to specific embodiments. Example 1

[0033] The method for fabricating a semiconductor radio frequency filter with a three-dimensional inductor structure provided in this application includes:

[0034] like Figure 1 As shown, a transition layer 110, a seed layer 120, a first electrode layer 130, a piezoelectric layer 140, and a second electrode layer 150 are sequentially fabricated on a substrate 100 used as a temporary substrate. The first electrode layer is used to fabricate a first electrode, and the second electrode layer is used to fabricate a second electrode.

[0035] Optionally, in one embodiment of this application, the substrate 100 is a silicon substrate, a silicon-on-insulator substrate, a glass substrate, a silicon carbide substrate, or a gallium arsenide (GaAs) substrate, etc.

[0036] The transition layer 110 can be a silicon oxide (SiO2) layer or a silicon nitride (SiNx) layer, etc., and can be formed by thermal oxidation process, physical vapor deposition (PVD) process or chemical vapor deposition (CVD) process, etc.

[0037] The seed layer 120 can be an aluminum nitride (AlN) layer, formed by physical vapor deposition (PVD) process, specifically magnetron sputtering process;

[0038] The first electrode layer 130 can be an Al layer, Cu layer, Mo layer, Au layer or Pt layer, and can be formed by physical vapor deposition (PVD) process; similarly, the second electrode layer 150 can be an Al layer, Cu layer, Mo layer, Au layer or Pt layer, and can be formed by physical vapor deposition (PVD) process.

[0039] The piezoelectric layer 140 can be an AlN layer, a scandium-doped aluminum nitride (AlxSc1-xN) layer, a lithium niobate (LiNbO3) layer, a lithium tantalate (LiTaO3) layer, or a quartz layer, etc. It can be a polycrystalline layer or a single-crystal layer, and can be formed by PVD or metal-organic chemical vapor deposition (MOCVD), etc.

[0040] like Figure 2 As shown, the first region of the second electrode layer 150 is etched to form a stepped structure 151 in the second electrode layer 150 to improve the performance of the bulk acoustic wave resonator. It should be noted that in this embodiment, the distance between the boundary of the first region and the boundary of the second electrode layer is greater than zero.

[0041] Specifically, in one embodiment of this application, the etching process for the second electrode layer can be a dry etching process or a wet etching process, but this application does not limit it and it depends on the specific circumstances.

[0042] like Figure 3 As shown, a dielectric layer 160 is formed on the side of the second electrode layer 150 away from the substrate 100. Optionally, the dielectric layer 160 is formed by a deposition process, specifically PVD or CVD, etc. The material of the dielectric layer 160 can be SiO2, SiNx or AlN, etc. This application does not limit this, and it depends on the specific situation.

[0043] It should be noted that, in this embodiment of the application, the dielectric layer 160 is a protective layer for the second electrode layer 150 to prevent the second electrode layer 150 from being oxidized. Optionally, the dielectric layer 160 also serves as a dielectric layer for the capacitor to be formed subsequently.

[0044] like Figure 4As shown, the second region of the second electrode layer 150 and the portion of the dielectric layer 160 located on the surface of the second region of the second electrode layer are etched to obtain a lower electrode pattern structure. The lower electrode pattern structure includes the remaining portion of the second electrode layer (i.e., the second electrode 152) and the portion of the dielectric layer 160 located on the surface of the second electrode 152. In a plane parallel to the substrate 100, the second region is located on the first side of the stepped structure. Optionally, the etching process for the dielectric layer 160 and the second electrode layer can be a wet etching process or a dry etching process.

[0045] A seventh electrode is formed on the surface of the dielectric layer 160 away from the piezoelectric layer. This seventh electrode, together with the dielectric layer 160 and the second electrode, constitutes a third capacitor. Specifically, forming the seventh electrode on the surface of the dielectric layer 160 away from the piezoelectric layer includes:

[0046] like Figure 5 As shown, a seventh electrode 170 is formed in the third region of the surface of the lower electrode pattern structure. Specifically, the seventh electrode 170 is formed in the third region of the surface of the dielectric layer 160 on the side away from the piezoelectric layer 140. In a plane parallel to the substrate 100, the third region is located on the second side of the stepped structure 151, opposite to the first side. It should be noted that in this embodiment, the seventh electrode 170, the dielectric layer 160, and the second electrode 152 constitute a third capacitor. Optionally, the material of the seventh electrode can be Al, Cu, Mo, Au, or Pt, etc. This application does not limit this; the specific material depends on the circumstances.

[0047] Specifically, in one embodiment of this application, forming a seventh electrode in the third region of the lower electrode pattern structure surface includes:

[0048] A third electrode layer is formed on the surface of the lower electrode pattern structure and the exposed surface of the piezoelectric layer. The formation process of the third electrode layer can be PVD, electroplating, or chemical plating, etc.

[0049] The third electrode layer is etched to remove the portion of the third electrode layer located on the surface of the piezoelectric layer and the portion of the third electrode layer located on the surface of the lower electrode pattern structure, while retaining the portion of the third electrode layer located on the surface of the lower electrode pattern structure (i.e., retaining the portion of the third electrode layer located in the third region of the lower electrode pattern structure surface), thus forming the seventh electrode. Optionally, the etching process of the third electrode layer can be wet etching or dry etching.

[0050] like Figure 6As shown, a sacrificial layer 180 is formed on the side of the lower electrode pattern structure away from the piezoelectric layer 140. The sacrificial layer 180 also covers the exposed portion of the piezoelectric layer 140 and the seventh electrode 170. That is, a sacrificial layer is formed on the side of the seventh electrode 170 away from the dielectric layer 160. The projection of the sacrificial layer on the substrate 100 coincides with the substrate 100. Optionally, the material of the sacrificial layer 180 can be SiO2, PSG, USG, a-Si, or photoresist, etc.; the formation process of the sacrificial layer 180 can be PVD, CVD, or spin coating, etc.

[0051] like Figure 7 As shown, the sacrificial layer 180 is etched to form vias 181 and 182, wherein via 181 exposes a portion of the surface of the piezoelectric layer 140, and via 182 exposes a portion of the surface of the dielectric layer 160. Specifically, the etching process of the sacrificial layer 180 can be either dry etching or wet etching.

[0052] like Figure 8 As shown, a cutoff boundary layer 190 is formed on the side of the sacrificial layer 180 away from the dielectric layer 160. The cutoff boundary layer 190 also fills the vias 181 and 182, that is, the cutoff boundary layer 190 covers the sacrificial layer 180 and the sidewalls, bottoms, and sidewalls of the vias 181 and 182. It should be noted that, in this embodiment, the cutoff boundary layer 190 has a first protrusion and a second protrusion facing the piezoelectric layer 140. The first protrusion corresponds to the via 181 and contacts the exposed area of ​​the piezoelectric layer, and the second protrusion corresponds to the via 182 and contacts the dielectric layer 160.

[0053] It should also be noted that, in this embodiment, the stop boundary layer 190 and the sacrificial layer 180 are made of different materials, so that the chemical substances used to etch the sacrificial layer 180 will not damage the stop boundary layer 190. Optionally, the material of the stop boundary layer 190 can be SiO2 or polycrystalline silicon (poly-Si), and the formation process can be PVD, CVD, etc.

[0054] like Figure 9 As shown, a bonding layer 200 is formed on the side of the cutoff boundary layer 190 away from the piezoelectric layer 140. The bonding layer 200 covers the surface of the cutoff boundary layer 190 and also fills the vias 181 and 182. Optionally, the material of the bonding layer can be SiO2, and the formation process can be PVD or CVD, etc. This application does not limit this, and it depends on the specific circumstances.

[0055] like Figure 10As shown, a substrate 210 (corresponding to the first substrate) is bonded as a carrier on the side of the bonding layer 200 away from the cutoff boundary layer 190.

[0056] like Figure 11 As shown, the wafer composed of the above-prepared structures is flipped, and the substrate 100 and the transition layer 110 are removed from the side of the substrate 100 away from the substrate 210. Optionally, the removal process of the substrate 100 and the transition layer 110 can be grinding or chemical mechanical polishing (CMP). This application does not limit this, and it depends on the specific circumstances.

[0057] like Figure 12 As shown, a fourth region of the seed layer 120 and the first electrode layer 130 is etched to expose a portion of the surface of the piezoelectric layer 140, forming an upper electrode pattern structure. The upper electrode pattern includes the first electrode 131 and the portion of the seed layer 120 located on the surface of the first electrode 131. Furthermore, the etched fourth region divides the first electrode layer 130 into a first portion 131a and a second portion 131b, which are separate from each other, and divides the seed layer 120 into a third portion 120a and a fourth portion 120b, which are also separate from each other. The third portion 120a corresponds to the first portion 131a, and the fourth portion 120b corresponds to the second portion 131b.

[0058] Optionally, the etching process for the seed layer 120 and the first electrode layer 130 can be either wet etching or dry etching.

[0059] like Figure 13 As shown, a through-hole 1401 is formed in the fourth portion 120b of the seed layer 120. The through-hole 1401 sequentially penetrates the fourth portion 120b, the second portion 131b, and the piezoelectric layer 140, exposing a portion of the surface of the second electrode 152 to facilitate the extraction of the second electrode 152. The second electrode 152 is located in the fifth region on the second side of the piezoelectric layer 140, and the first electrode 131 is located in the sixth region on the first side of the piezoelectric layer 140. In a first direction, the fifth region and the sixth region overlap.

[0060] Optionally, the through hole 1401 can be formed by a wet etching process or a dry etching process.

[0061] like Figure 14 As shown, a through-hole 1402 is formed in the third portion 120a of the seed layer 120. The through-hole 1402 exposes a portion of the surface of the first portion 131a of the first electrode 131 to facilitate the lead-out of the first electrode 131. Specifically, the through-hole 1402 can be formed using either a wet etching process or a dry etching process.

[0062] like Figure 15 As shown, a first conductive layer 230 is formed within the through-hole 1402, covering the sidewalls and bottom of the through-hole 1402, and extending to a portion of the surface of the third portion 120a of the seed layer 120; a second conductive layer 220 is formed within the through-hole 1401, covering the sidewalls and bottom of the through-hole 1401, and extending to a portion of the surface of the fourth portion 120b of the seed layer 120. It should be noted that in this embodiment, the first conductive layer is electrically connected to the first electrode, and has a higher conductivity than the first electrode; the second conductive layer is electrically connected to the second electrode, and has a higher conductivity than the second electrode.

[0063] Optionally, in one embodiment of this application, the material of the first conductive layer can be Au, Cu, or Al, and the formation method can be PVD or electroplating, etc.; similarly, the material of the second conductive layer can be Au, Cu, or Al, and the formation method can be PVD or electroplating, etc.

[0064] Optionally, the second conductive layer and the first conductive layer are formed simultaneously to simplify the formation process of the semiconductor radio frequency filter. Specifically, in one embodiment of this application, the method for forming the first conductive layer and the second conductive layer includes:

[0065] A conductive layer is formed on the side of the seed layer away from the piezoelectric layer, and the conductive layer covers the surface of the seed layer, the surface of the via 1402, the exposed surface of the piezoelectric layer, and the surface of the via 1401.

[0066] The conductive layer is etched to form a first conductive layer and a second conductive layer. The first conductive layer covers the sidewall and bottom of the via 1402 and extends to a portion of the surface covering a third part of the seed layer. The second conductive layer covers the sidewall and bottom of the via 1401 and extends to a portion of the surface covering a fourth part of the seed layer.

[0067] It should be noted that, in this embodiment, the etching process of the conductive layer can be either a wet etching process or a dry etching process.

[0068] like Figure 16As shown, a predetermined region of the sacrificial layer 180 is released to form a resonant cavity 1801 below the bulk acoustic resonator. The predetermined region is located between the first protrusion and the second protrusion. Specifically, the portion of the sacrificial layer 180 located between the first and second protrusions is released, while the portion of the sacrificial layer located on the side of the first protrusion away from the second protrusion is retained, forming a first sacrificial layer. The portion of the second protrusion located on the side of the second protrusion away from the first protrusion forms a second sacrificial layer. The resonant cavity 1801 is the region defined by the piezoelectric layer 140, the dielectric layer 160, the first protrusion, the second protrusion, and the cutoff boundary layer 190. At least a portion of the resonant cavity 1801 is in contact with the piezoelectric layer 140.

[0069] Optionally, in one embodiment of this application, releasing the preset region of the sacrificial layer to form a resonant cavity 1801 below the bulk acoustic wave resonator includes: using liquid phase etching or vapor phase etching to release the preset region of the sacrificial layer and form a resonant cavity 1801 below the bulk acoustic wave resonator.

[0070] Specifically, in one embodiment of this application, a predetermined region of the sacrificial layer is released using liquid phase etching or vapor phase etching to form a resonant cavity 1801 below the bulk acoustic wave resonator, including:

[0071] The predetermined area of ​​the sacrificial layer is etched using a liquid etching solution such as hydrofluoric acid solution (HF) or buffered oxide etchant (BOE) to form a resonant cavity 1801 below the bulk acoustic resonator.

[0072] Alternatively, a predetermined area of ​​the sacrificial layer can be etched using gases such as gaseous hydrogen fluoride (HF) or xenon difluoride (XeF2) to form a resonant cavity 1801 below the bulk acoustic resonator.

[0073] like Figure 17 As shown, a substrate 240 (corresponding to the second substrate) is prepared having a first three-dimensional inductor 242 and a second three-dimensional inductor 241. Optionally, the material of the substrate 240 can be silicon, glass, SiC, GaAs, etc., and this application does not limit this, depending on the specific circumstances.

[0074] Specifically, in one embodiment of this application, the manufacturing process of the first stereo inductor 242 includes the following steps:

[0075] Provide a glass wafer as a substrate 240;

[0076] Through-glass vias (TGVs) are fabricated on glass wafers.

[0077] A Ti / Cu seed layer is first deposited on the sidewall of the TGV by sputtering, followed by the formation of a copper layer by electroplating, and finally the TGV is completely filled with polymer material.

[0078] A redistribution layer (RDL) is fabricated on the front side of the glass wafer using a 10μm copper electroplating process. This layer is used for interconnection and for forming 3D inductors on the front side.

[0079] The back side of the glass wafer is ground to expose the TGV; for example, the original glass thickness is 700 μm, which will be thinned to 250 μm after grinding. After thinning, the TGV opening on the back side is approximately 40 μm, and the copper ring and polymer filler material are visible.

[0080] On the back side of the glass wafer, a Ti / Cu seed layer is deposited by sputtering, and 10µm copper is applied directly to the glass by electroplating to form the back redistribution layer (RDL); thus, the first three-dimensional inductor 242 is formed through the front redistribution layer, the through-glass via, and the back redistribution layer.

[0081] It should be noted that the manufacturing process of the second stereo inductor 241 is the same as that of the first stereo inductor 242, and will not be described again here.

[0082] It should also be noted that the first stereo inductor 242 and the second stereo inductor 241 have a Q value of over 60 at 1 GHz, thus the first stereo inductor 242 and the second stereo inductor 241 have high Q value performance.

[0083] It should also be noted that, Figure 17 The semiconductor radio frequency filter shown includes both a first three-dimensional inductor 242 and a second three-dimensional inductor 241, but this application does not limit it. In other embodiments of this application, the semiconductor radio frequency filter may include only the first three-dimensional inductor 242 or only the second three-dimensional inductor 241, depending on the specific circumstances.

[0084] like Figure 18 As shown, a dielectric layer 250 (corresponding to the first dielectric layer) is deposited on one side of the substrate 240 to cover the first 3D inductor 242 and the second 3D inductor 241. Optionally, the material of the dielectric layer 250 can be SiO2 or SiNx, etc., and the formation process can be CVD, etc. This application does not limit this, and it depends on the specific circumstances.

[0085] like Figure 19 As shown, a through-hole 251 is formed on the dielectric layer 250, the through-hole 251 penetrating the dielectric layer 250 and exposing a portion of the second stereo inductor 241. Specifically, in one embodiment of this application, the through-hole 251 is obtained by exposing and developing the dielectric layer 250.

[0086] like Figure 20As shown, a metal layer 260 is formed on the side of the dielectric layer 250 away from the substrate 240, and the metal layer 260 covers the surface of the via 251 and the exposed surface of the second three-dimensional inductor 241.

[0087] like Figure 21 As shown, the metal layer 260 is etched to remove a portion of the metal layer 260 located on the surface of the dielectric layer 250, retaining the portion of the metal layer 260 located on the surface of the via 251 and extending to cover a portion of the surface of the dielectric layer 250 and at least partially overlapping with the second three-dimensional inductor 241 in the first direction, and retaining the portion of the metal layer 260 that at least partially overlaps with the first three-dimensional inductor 242 in the first direction, thus forming the third electrode 262 and the fifth electrode 261.

[0088] like Figure 22 As shown, a dielectric layer 270 (corresponding to the second dielectric layer) is formed on the side of the dielectric layer 250 away from the substrate 240, and the dielectric layer 270 covers the third electrode 262 and the fifth electrode 261. It should be noted that in this embodiment, the dielectric layer 270 is the capacitor dielectric layer for the subsequently formed first and second capacitors. Optionally, the material of the dielectric layer 270 can be SiO2 or SiNx, etc., and the formation process can be CVD, etc. This application does not limit this, and the specific method depends on the circumstances.

[0089] like Figure 23 As shown, a through hole 271 is formed in the exposed portion of the dielectric layer 270 and the dielectric layer 250. The through hole 271 penetrates the dielectric layer 270 and the dielectric layer 250, exposing a portion of the surface of the first three-dimensional inductor 242 to facilitate the lead-out of the first three-dimensional inductor 242.

[0090] Optionally, the through hole 271 can be formed by a wet etching process or a dry etching process.

[0091] like Figure 24 As shown, a metal layer 280 is formed on the side of the dielectric layer 270 away from the substrate 240, and the metal layer 280 covers the surface of the via 271 and the exposed surface of the first three-dimensional inductor 242.

[0092] like Figure 25As shown, the metal layer 280 is etched to remove the portion of the metal layer 280 located on the surface of the dielectric layer 270, retaining the portion of the metal layer 280 located on the surface of the via 271 and extending to cover a portion of the dielectric layer 270 surface and at least partially overlapping with the first three-dimensional inductor 242 and the third electrode 262 in a first direction, and retaining the portion of the metal layer 280 that at least partially overlaps with the second three-dimensional inductor 241 and the fifth electrode 261 in the first direction, forming a fourth electrode 282 and a sixth electrode 281. The third electrode 262, the dielectric layer 270, and the fourth electrode 282 constitute a first capacitor. The fifth electrode 261, the dielectric layer 270, and the sixth electrode 281 constitute a second capacitor.

[0093] It should be noted that, Figure 25 The semiconductor radio frequency filter shown includes both a first capacitor and a second capacitor, but this application does not limit it. In other embodiments of this application, the semiconductor radio frequency filter may include only the first capacitor or only the second capacitor, depending on the specific circumstances.

[0094] like Figure 26 As shown, Figure 25 After the corresponding structure is vertically flipped, it is the same as... Figure 16 Bonding is then performed. Specifically, the first conductive layer 230 is bonded to the fourth electrode 282, and the second conductive layer 220 is bonded to the sixth electrode 281. Thus, bonding can be achieved directly through metal bonding between the first and second conductive layers 230 and the fourth and sixth electrodes 282 and 281, eliminating the need for bonding layers. This further simplifies the layer structure of the semiconductor RF filter and further promotes the miniaturization of semiconductor RF filters.

[0095] Furthermore, embodiments of this application also provide a semiconductor radio frequency filter employing a three-dimensional inductor structure manufactured using the manufacturing method provided in any of the above embodiments.

[0096] like Figure 26 As shown, the semiconductor radio frequency filter with a three-dimensional inductor structure provided in this application embodiment includes: a substrate 210 (corresponding to a first substrate) serving as a carrier, a bulk acoustic wave resonator located on the substrate 210, and a three-dimensional inductor structure. The three-dimensional inductor structure includes a substrate 240 (corresponding to a second substrate) and a three-dimensional inductor disposed within the substrate 240; wherein the substrate 240 is reused as a cover plate for the bulk acoustic wave resonator.

[0097] Optionally, the bulk acoustic wave resonator includes a piezoelectric layer 140, a first electrode 131, a second electrode 152, and a resonant cavity 1801; wherein the first electrode 131 is located on the side of the piezoelectric layer 140 away from the substrate 210; the second electrode 152 is located on the side of the piezoelectric layer 140 close to the substrate 210; and the resonant cavity 1801 is formed between the piezoelectric layer 140 and the substrate 210.

[0098] Optionally, the 3D inductor includes a first 3D inductor 242, and the semiconductor RF filter further includes: a dielectric layer 250 (corresponding to the first dielectric layer) located on the side of the substrate 240 near the piezoelectric layer 140; a third electrode 262 located on the side of the dielectric layer 250 away from the substrate 240; a dielectric layer 270 (corresponding to the second dielectric layer) located on the side of the dielectric layer 250 away from the substrate 240 and covering the third electrode 262; and a fourth electrode 282, a portion of which penetrates the dielectric layer 270 and the dielectric layer 250 and is electrically connected to the first 3D inductor 242, and another portion extends to cover the surface of the dielectric layer 270 away from the substrate 240; wherein the third electrode 262, the dielectric layer 270, and the fourth electrode 282 constitute a first capacitor.

[0099] Optionally, the 3D inductor includes a second 3D inductor 241, and the semiconductor RF filter further includes: a fifth electrode 261, a portion of which penetrates the dielectric layer 250 and is electrically connected to the second 3D inductor 241, and another portion which extends to cover the surface of the dielectric layer 250 away from the substrate 240; and a sixth electrode 281 located on the dielectric layer 270 near the piezoelectric layer; wherein the dielectric layer 270 covers the fifth electrode 261, and the fifth electrode 261, the dielectric layer 270, and the sixth electrode 281 constitute a second capacitor.

[0100] Optionally, the semiconductor radio frequency filter further includes: a first conductive layer 230, which is electrically connected to the first electrode 131 and bonded to the fourth electrode 282; and a second conductive layer 220, which is electrically connected to the second electrode 152 and bonded to the sixth electrode 281.

[0101] Optionally, the semiconductor radio frequency filter further includes a seed layer 120 located on the surface of the first electrode 131 away from the piezoelectric layer 140; the first electrode 131 includes a first portion 131a and a second portion 131b separated from each other, the seed layer 120 includes a third portion 120a and a fourth portion 120b separated from each other, the first portion 131a corresponds to the third portion 120a, and the second portion 131b corresponds to the fourth portion 120b; and the first conductive layer 230 penetrates the third portion 120a of the seed layer 120 and is electrically connected to the first portion 131a of the first electrode 131; the second conductive layer 220 sequentially penetrates the fourth portion 120b of the seed layer 120, the second portion 131b of the first electrode 131, and the piezoelectric layer 140 and is electrically connected to the second electrode 152.

[0102] It should be noted that since the detailed structure of the semiconductor radio frequency filter has been described in detail in the semiconductor radio frequency filter manufacturing method, it will not be repeated here.

[0103] In summary, the semiconductor RF filter and its fabrication method using a three-dimensional inductor structure proposed in this application include a first substrate as a carrier, a bulk acoustic wave resonator located on the first substrate, and a three-dimensional inductor structure. The three-dimensional inductor structure includes a second substrate and a three-dimensional inductor disposed within the second substrate, and the second substrate is reused as a cover plate for the bulk acoustic wave resonator. Therefore, there is no need to add an additional substrate as a cover plate for the bulk acoustic wave resonator; instead, the carrier of the three-dimensional inductor (i.e., the second substrate) is directly used as a protective cover plate for the bulk acoustic wave resonator, eliminating the need for an additional cover plate structure, simplifying the layer structure of the semiconductor RF filter, making it more compact, and promoting the miniaturization process of semiconductor RF filters. This solves the miniaturization problems faced by existing semiconductor RF filters integrating bulk acoustic wave resonators and inductors. Example 2

[0104] The invention scheme in this embodiment is basically the same as that in Embodiment 1, except that in the present invention, the first conductive layer 230 and the second conductive layer 220 are electrically connected to the first electrode 131 and the second electrode 152 from the other side of the bulk acoustic resonator, and the bulk acoustic resonator includes not only the resonant cavity 1801, but also the resonant cavity 3300.

[0105] Specifically, in Example 1 Figure 12 On the basis of, such as Figure 27As shown, portions of the seed layer 120 and the first electrode layer 130 are etched to expose a portion of the surface of the piezoelectric layer 140, forming an upper electrode pattern structure. The upper electrode pattern includes a first electrode 131 and a portion of the seed layer located on the surface of the first electrode 131. The first electrode 131 is located in the sixth region on the first side of the piezoelectric layer 140.

[0106] Optionally, the etching process for the seed layer 120 and the first electrode layer 130 can be either wet etching or dry etching.

[0107] like Figure 28 As shown, a through hole 1403 is formed in the exposed portion of the piezoelectric layer 140. The through hole 1403 penetrates the piezoelectric layer 140 and exposes part of the surface of the second electrode 152 to facilitate the lead-out of the second electrode 152.

[0108] Optionally, the through-hole 1403 can be formed by a wet etching process or a dry etching process.

[0109] like Figure 29 As shown, a through-hole 1404 is formed in the seed layer 120, exposing a portion of the surface of the first electrode 131 to facilitate the extraction of the first electrode 131. Specifically, the through-hole 1404 can be formed using either a wet etching process or a dry etching process.

[0110] like Figure 30 As shown, a third conductive layer 310 is formed within the through-hole 1404, covering the sidewalls and bottom of the through-hole 1404, and extending to cover a portion of the surface of the seed layer 120; a fourth conductive layer 320 is formed within the through-hole 271, covering the sidewalls and bottom of the through-hole 271, and extending to cover a portion of the surface of the piezoelectric layer 140. It should be noted that in this embodiment, the third conductive layer 310 is electrically connected to the first electrode 131, and has a higher conductivity than the first electrode 131; the fourth conductive layer 320 is electrically connected to the second electrode 152, and has a higher conductivity than the second electrode 152.

[0111] Optionally, in one embodiment of this application, the material of the third conductive layer can be Au, Cu, or Al, and the forming method can be PVD or electroplating, etc.; similarly, the material of the fourth conductive layer can be Au, Cu, or Al, and the forming method can be PVD or electroplating, etc.

[0112] Optionally, the third conductive layer and the fourth conductive layer are formed simultaneously to simplify the fabrication process of the filter device. Specifically, in one embodiment of this application, the method for forming the third conductive layer and the fourth conductive layer includes:

[0113] A conductive layer is formed on the side of the seed layer away from the piezoelectric layer, and the conductive layer covers the surface of the seed layer, the surface of the via 1404, the exposed surface of the piezoelectric layer, and the surface of the via 1403.

[0114] The conductive layer is etched to form a third conductive layer and a fourth conductive layer. The fourth conductive layer covers the sidewall and bottom of the via 1404 and extends to cover a portion of the surface of the seed layer. The third conductive layer covers the sidewall and bottom of the via 1403 and extends to cover a portion of the surface of the piezoelectric layer.

[0115] It should be noted that, in this embodiment, the etching process of the conductive layer can be either a wet etching process or a dry etching process.

[0116] like Figure 31 As shown, a predetermined region of the sacrificial layer 180 is released to form a resonant cavity 1801 below the bulk acoustic resonator. The predetermined region is located between the first protrusion and the second protrusion. Specifically, the portion of the sacrificial layer 180 located between the first and second protrusions is released, while the portion of the sacrificial layer located on the side of the first protrusion away from the second protrusion is retained, forming a first sacrificial layer. The portion of the second protrusion located on the side of the second protrusion away from the first protrusion forms a second sacrificial layer. The resonant cavity 1801 is the region defined by the piezoelectric layer 140, the dielectric layer 160, the first protrusion, the second protrusion, and the cutoff boundary layer 190. At least a portion of the resonant cavity 1801 is in contact with the piezoelectric layer 140.

[0117] Optionally, in one embodiment of this application, releasing the preset region of the sacrificial layer to form a resonant cavity 1801 below the bulk acoustic wave resonator includes: using liquid phase etching or vapor phase etching to release the preset region of the sacrificial layer and form a resonant cavity 1801 below the bulk acoustic wave resonator.

[0118] Specifically, in one embodiment of this application, a predetermined region of the sacrificial layer is released using liquid phase etching or vapor phase etching to form a resonant cavity 1801 below the bulk acoustic wave resonator, including:

[0119] The predetermined area of ​​the sacrificial layer is etched using a liquid etching solution such as hydrofluoric acid solution (HF) or buffered oxide etchant (BOE) to form a resonant cavity 1801 below the bulk acoustic resonator.

[0120] Alternatively, a predetermined area of ​​the sacrificial layer can be etched using gases such as gaseous hydrogen fluoride (HF) or xenon difluoride (XeF2) to form a resonant cavity 1801 below the bulk acoustic resonator.

[0121] like Figure 32 As shown, a bonding layer 330 is formed, which is located on the side of the first electrode 131 away from the piezoelectric layer 140, that is, the bonding layer 330 is located on the side of the seed layer 120 away from the piezoelectric layer 140, and the bonding layer 330 also covers the exposed surface of the piezoelectric layer 140.

[0122] Optionally, in one embodiment of this application, the bonding layer 330 is made of SiO2 or SiNx, and the forming process can be PVD or CVD, etc.; in another embodiment of this application, the bonding layer 330 is a photoresist-like dry film material, formed by spin coating, photolithography, etc. This application does not limit this, and it depends on the specific circumstances.

[0123] like Figure 33 As shown, a resonant cavity 3300 is formed above the bulk acoustic resonator, and at least a portion of the resonant cavity 3300 is in contact with the piezoelectric layer 140. Figure 34 As shown, a substrate 340 is bonded to the bonding layer 330 on the side away from the seed layer 120. The area defined by the substrate 340, the bonding layer 330, the first electrode 131, and the piezoelectric layer 140 is the resonant cavity 3300. Optionally, the material of the substrate 340 can be silicon, glass, SiC, GaAs, etc. This application does not limit this, and it depends on the specific circumstances.

[0124] like Figure 35 As shown, the substrate 340 is thinned.

[0125] like Figure 36 As shown, the wafer composed of the above-mentioned structures is flipped.

[0126] like Figure 37 As shown, through-holes 2101 and 2102 are formed starting from the substrate 210. Through-hole 2101 penetrates the substrate 210, the bonding layer 200, the cutoff boundary layer 190, the sacrificial layer 180, and the piezoelectric layer 140, exposing a portion of the surface of the first electrode 131 for lead-out. Through-hole 2102 penetrates the substrate 210, the bonding layer 200, the cutoff boundary layer 190, the sacrificial layer 180, and the dielectric layer 160, exposing a portion of the surface of the second electrode 152 for lead-out.

[0127] Optionally, in one embodiment of this application, the vias 2101 and 2102 are formed using a dry etching process. Specifically, deep reactive ion etching (DRIE) equipment and processes are used to dry etch the substrate 210, bonding layer 200, cutoff boundary layer 190, sacrificial layer 180, and piezoelectric layer 140 to form via 2101. Similarly, deep reactive ion etching (DRIE) equipment and processes are used to dry etch the substrate 210, bonding layer 200, cutoff boundary layer 190, sacrificial layer 180, and dielectric layer 160 to form via 2102.

[0128] like Figure 38 As shown, a first conductive layer 230 is formed on the surface of the through hole 2101, the first conductive layer 230 covers the sidewall and bottom of the through hole 2101, and extends to cover a portion of the surface of the substrate 210; a second conductive layer 220 is formed on the surface of the through hole 2102, the second conductive layer 220 covers the sidewall and bottom of the through hole 2102, and extends to cover a portion of the surface of the substrate 210.

[0129] It should be noted that, in this embodiment, the first conductive layer 230 is electrically connected to the first electrode 131, and the first conductive layer 230 has a higher conductivity than the first electrode 131; the second conductive layer 220 is electrically connected to the second electrode 152, and the second conductive layer 220 has a higher conductivity than the second electrode 152.

[0130] Optionally, in one embodiment of this application, the material of the first conductive layer 230 can be Au, Cu or Al, etc., and the formation method can be PVD or electroplating, etc.; similarly, the material of the second conductive layer 220 can be Au, Cu or Al, etc., and the formation method can be PVD or electroplating, etc.

[0131] Optionally, the first conductive layer 230 and the second conductive layer 220 are formed simultaneously to simplify the fabrication process of the filtering device. Specifically, in one embodiment of this application, the method for forming the first conductive layer 230 and the second conductive layer 220 includes:

[0132] A conductive layer is formed on the side of the substrate 210 away from the piezoelectric layer 140, and the conductive layer covers the surface of the substrate 210, the surface of the via 2101, the exposed surface of the piezoelectric layer 140, and the surface of the via 2102.

[0133] The conductive layer is etched to form a first conductive layer 230 and a second conductive layer 220. The first conductive layer 230 covers the sidewalls and bottom of the via 2101 and the exposed surface of the piezoelectric layer 140, and extends to cover a portion of the surface of the substrate 210. The second conductive layer 220 covers the sidewalls and bottom of the via 2102 and the exposed surface of the piezoelectric layer 140, and extends to cover a portion of the surface of the substrate 210.

[0134] It should be noted that, in this embodiment, the etching process of the conductive layer can be either a wet etching process or a dry etching process.

[0135] like Figure 39 As shown, the first embodiment... Figure 25 After the corresponding structure is vertically flipped, it is the same as... Figure 38 The first conductive layer 230 is bonded to the fourth electrode 282, and the second conductive layer 220 is bonded to the sixth electrode 281. Thus, bonding can be achieved directly through metal bonding between the first and second conductive layers 230 and the fourth and sixth electrodes 282 and 281, eliminating the need for bonding layers. This further simplifies the layer structure of the semiconductor RF filter and promotes its miniaturization.

[0136] The various sections in this manual are described in a progressive manner, with each section focusing on the differences from the others. Similar or identical parts can be referred to each other.

[0137] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A semiconductor radio frequency filter employing a three-dimensional inductive structure, comprising a first substrate as a carrier and bulk acoustic wave resonators located on the first substrate; characterized in that, Also comprising: a three-dimensional inductor structure comprising a second substrate and a three-dimensional inductor embedded inside the second substrate; wherein the second substrate is arranged on a side of the bulk acoustic resonator away from the first substrate and is multiplexed as a cover plate of the bulk acoustic resonator; the three-dimensional inductor comprises a first three-dimensional inductor; a first dielectric layer located on a side of the second substrate close to the piezoelectric layer of the bulk acoustic resonator; a third electrode located on a side of the first dielectric layer away from the second substrate; a second dielectric layer located on a side of the first dielectric layer away from the second substrate and covering the third electrode; and a fourth electrode, a part of which is electrically connected with the first three-dimensional inductor through the second dielectric layer and the first dielectric layer, and another part extends to a surface covering a side of the second dielectric layer away from the second substrate; wherein the third electrode, the second dielectric layer and the fourth electrode constitute a first capacitor.

2. The semiconductor radio frequency filter of claim 1, wherein, The bulk acoustic resonator comprises a piezoelectric layer, a first electrode, a second electrode and a resonant cavity; wherein the first electrode is located on a side of the piezoelectric layer away from the first substrate; the second electrode is located on a side of the piezoelectric layer close to the first substrate; and the resonant cavity is formed between the piezoelectric layer and the first substrate.

3. The semiconductor RF filter of claim 2, wherein, The three-dimensional inductor comprises a second three-dimensional inductor, and the semiconductor radio frequency filter further comprises: a fifth electrode, a part of which is electrically connected with the second three-dimensional inductor through the first dielectric layer, and another part extends to a surface covering a side of the first dielectric layer away from the second substrate; and a sixth electrode located on a side of the second dielectric layer close to the piezoelectric layer; wherein the second dielectric layer covers the fifth electrode, the fifth electrode, the second dielectric layer and the sixth electrode constitute a second capacitor.

4. The semiconductor RF filter of claim 3, wherein, The semiconductor radio frequency filter further comprises: a first conductive layer electrically connected with the first electrode and bonded connected with the fourth electrode; and a second conductive layer electrically connected with the second electrode and bonded connected with the sixth electrode.

5. The semiconductor RF filter of claim 4, wherein, The semiconductor radio frequency filter further comprises a seed layer located on a surface of the first electrode away from the piezoelectric layer; the first electrode comprises a first part and a second part separated from each other, the seed layer comprises a third part and a fourth part separated from each other, the first part corresponds to the third part, and the second part corresponds to the fourth part; and the first conductive layer is electrically connected with the first part of the first electrode through the third part of the seed layer; the second conductive layer is electrically connected with the second electrode through the fourth part of the seed layer, the second part of the first electrode and the piezoelectric layer in turn.

6. The semiconductor RF filter of claim 4, wherein, The semiconductor radio frequency filter further comprises: a third dielectric layer located on a surface of the second electrode away from the piezoelectric layer; a sacrificial layer located on a surface of the third dielectric layer away from the piezoelectric layer; a cutoff boundary layer located on a surface of the sacrificial layer away from the third dielectric layer; and a bonding layer located on a side of the cutoff boundary layer away from the third dielectric layer; And the first conducting layer is electrically connected through the first substrate, the bonding layer, the cutoff boundary layer, the sacrifice layer, the piezoelectric layer and the first electrode in sequence; and the second conducting layer is electrically connected through the first substrate, the bonding layer, the cutoff boundary layer, the sacrifice layer, the third dielectric layer and the second electrode in sequence.

7. The semiconductor RF filter of claim 2, wherein, The three-dimensional inductor includes a second three-dimensional inductor, and the semiconductor radio frequency filter further includes: A first dielectric layer is located on a side of the second substrate close to the piezoelectric layer; A fifth electrode, a part of the fifth electrode is electrically connected with the second three-dimensional inductor through the first dielectric layer, and another part of the fifth electrode extends to a surface of the first dielectric layer away from the second substrate; A second dielectric layer is located on a side of the first dielectric layer close to the piezoelectric layer and covers the fifth electrode; and A sixth electrode is located on a side of the second dielectric layer close to the piezoelectric layer; The fifth electrode, the second dielectric layer and the sixth electrode constitute a second capacitor.

8. A method for fabricating a semiconductor radio frequency filter employing a three-dimensional inductor structure, characterized in that, It includes: A first substrate is provided as a carrier; A bulk acoustic wave resonator is formed on a side of the first substrate; A second substrate is provided, and a three-dimensional inductor is embedded in the second substrate; The second substrate is arranged on a side of the bulk acoustic wave resonator away from the first substrate to form a cover plate of the bulk acoustic wave resonator; The three-dimensional inductor includes a first three-dimensional inductor, and the manufacturing method further includes: manufacturing a first dielectric layer located on a side of the second substrate close to a piezoelectric layer of the bulk acoustic wave resonator; manufacturing a third electrode located on a side of the first dielectric layer away from the second substrate; manufacturing a second dielectric layer located on a side of the first dielectric layer away from the second substrate and covering the third electrode; and manufacturing a fourth electrode, a part of the fourth electrode is electrically connected with the first three-dimensional inductor through the second dielectric layer and the first dielectric layer, and another part of the fourth electrode extends to a surface of the second dielectric layer away from the second substrate; wherein the third electrode, the second dielectric layer and the fourth electrode constitute a first capacitor.

9. The production method according to claim 8, characterized by, The bulk acoustic wave resonator includes a piezoelectric layer, a first electrode, a second electrode and a resonant cavity; wherein the first electrode is located on a side of the piezoelectric layer away from the first substrate; the second electrode is located on a side of the piezoelectric layer close to the first substrate; The resonant cavity is formed between the piezoelectric layer and the first substrate; and The three-dimensional inductor includes a second three-dimensional inductor, and the manufacturing method further includes: manufacturing a fifth electrode, a part of the fifth electrode is electrically connected with the second three-dimensional inductor through the first dielectric layer, and another part of the fifth electrode extends to a surface of the first dielectric layer away from the second substrate; and manufacturing a sixth electrode located on a side of the second dielectric layer close to the piezoelectric layer; wherein the second dielectric layer covers the fifth electrode, the fifth electrode, the second dielectric layer and the sixth electrode constitute a second capacitor. The manufacturing method further includes:

10. The method of manufacturing according to claim 9, wherein, ​ The first conductive layer is made, which is electrically connected with the first electrode and is bonded with the fourth electrode; and The second conductive layer is made, which is electrically connected with the second electrode and is bonded with the sixth electrode.

11. The method of manufacturing according to claim 10, wherein, The semiconductor radio frequency filter further comprises: A seed layer is located on the surface of the first electrode away from the piezoelectric layer; the first electrode comprises a first part and a second part separated from each other, the seed layer comprises a third part and a fourth part separated from each other, the first part corresponds to the third part, and the second part corresponds to the fourth part; the first conductive layer is electrically connected with the first part of the first electrode through the third part of the seed layer; and the second conductive layer is electrically connected with the second electrode through the fourth part of the seed layer, the second part of the first electrode, and the piezoelectric layer in sequence; or A third dielectric layer is located on the surface of the second electrode away from the piezoelectric layer; a sacrifice layer is located on the surface of the third dielectric layer away from the piezoelectric layer; a cutoff boundary layer is located on the surface of the sacrifice layer away from the third dielectric layer; a bonding layer is located on the surface of the cutoff boundary layer away from the third dielectric layer; the first conductive layer is electrically connected with the first electrode through the first substrate, the bonding layer, the cutoff boundary layer, the sacrifice layer, and the piezoelectric layer in sequence; and the second conductive layer is electrically connected with the second electrode through the first substrate, the bonding layer, the cutoff boundary layer, the sacrifice layer, and the third dielectric layer in sequence.

Images