Data clock recovery device and method based on fractional frequency division

Abstract

The present invention relates to the field of duplex communication technologies, and particularly to a data clock recovery device and method based on fractional frequency division. The device includes a phase detector, a digital filter, a sigma-delta modulator, and a frequency divider. The output end of the phase detector is connected to the input end of the digital filter, the output end of the digital filter is connected to the input end of the sigma-delta modulator, the output end of the sigma-delta modulator is connected to the input end of the frequency divider, the input end of the frequency divider is simultaneously connected to a local high-speed clock signal, the output end of the frequency divider is connected to the input end of the phase detector, and the input end of the phase detector is simultaneously connected to a low-speed input signal. The present invention is based on a digital structure, has a simple circuit, can reduce the complexity of clock recovery of in-vehicle display serdes, and thus brings advantages such as chip power consumption and area.

Description

Technical Field

[0001] The present invention relates to the technical field of duplex communication, and in particular to a data clock recovery device and method based on fractional frequency division. Background Art

[0002] At present, the demand for high-speed data transmission using coaxial cables in the automotive field is increasing rapidly. To save cable costs, duplex communication is generally adopted, that is, there are both upstream signals and downstream signals on the cable. Usually, the upstream signal rate is relatively low, and the downstream signal rate is relatively high, as Figure 1 shown. Since the cable only transmits data without a clock signal, both the downstream high-speed signal and the upstream low-speed signal need to use CDR (Clock Data Recovery). The high-speed signal CDR generally adopts a structure based on PI (Phase Interpolator), and the traditional low-speed signal is also based on the PI structure, and its implementation circuit is complex.

[0003] The main function of CDR is to extract clock information from the input signal. Generally, it is necessary to adjust the phase of the local clock to synchronize with the input signal. The phase difference between the local clock and the input signal is adjusted through feedback so that this phase difference is 0. As Figure 2 shown, in the traditional PI (Phase Interpolator) - based scheme, the phase of the local high-speed clock is adjusted by controlling the phase interpolator. The phase interpolator is an analog circuit, and the circuit structure is complex. For a low-speed input signal, the local high-speed clock also needs to be frequency-divided to obtain a recovered clock, and finally the frequency and phase of the recovered clock are the same as those of the input signal. Summary of the Invention

[0004] In view of this, the present invention provides a data clock recovery device and method based on fractional frequency division, which can greatly reduce the complexity of the circuit.

[0005] To achieve the foregoing object, the present invention provides the following technical solutions:

[0006] A data clock recovery device based on fractional frequency division includes a phase detector, a digital filter, a sigma-delta modulator, and a frequency divider. The output end of the phase detector is connected to the input end of the digital filter, the output end of the digital filter is connected to the input end of the sigma-delta modulator, the output end of the sigma-delta modulator is connected to the input end of the frequency divider, the input end of the frequency divider is simultaneously connected to a local high-speed clock signal, the output end of the frequency divider is connected to the input end of the phase detector, and the input end of the phase detector is simultaneously connected to a low-speed input signal.

[0007] In the above solution, a sigma-delta modulator is used in cooperation with a frequency divider to replace the traditional phase interpolator. The sigma-delta modulator is a digital circuit, and its circuit structure is much simpler. At this time, the filter can also be implemented by a digital circuit. Therefore, the structure of the overall device is simpler than the traditional solution, greatly reducing the circuit complexity.

[0008] In a further optimized solution, the phase detector uses a bang bang non-linear phase detector, which includes four flip-flops, three exclusive-OR gates, and two AND gates. The input low-speed signal and the recovered clock output by the frequency divider are input into the flip-flops, and after being processed by the exclusive-OR gates and the AND gates, a pe signal and a pl signal with values of 0 or 1 are output.

[0009] In the above solution, the bang bang non-linear phase detector is a fully digital circuit, and its output is a digital signal, which is convenient for subsequent digital circuit integration. Using this phase detector does not require a complex analog circuit, has a simple structure, low power consumption, and small occupied area. Moreover, this structure can effectively suppress noise and improve the stability of the device by binarizing the phase.

[0010] In a further optimized solution, the digital filter uses a first-order filter. In this solution, using a first-order filter has a simpler structure than a second-order filter, and the first-order filter can also ensure stable and reliable performance in this solution.

[0011] The digital filter includes three adders and two multipliers. The pe signal and the pl signal are subtracted by an adder to obtain a pd value. The pd value is multiplied by the integration path gain by a multiplier and then added to the result of its one-beat delay by another adder to obtain an accumulated result. The pd value is multiplied by the proportional path gain by another multiplier and then added to the accumulated result by another adder to output a control quantity sdm_ctrl.

[0012] The filter in the traditional solution is a second-order filter. For example Figure 2 In the shown structure, the second-order filter is more complex than the first-order filter of this structure. For the filter in this solution, this structure only requires three adders and two multipliers. The multiplier can be implemented by shifting binary numbers to the left. It has a simple structure, less hardware resource occupation, and low power consumption. And from the performance perspective, this structure is first-order, has high stability, and is not prone to oscillation.

[0013] In a further optimized solution, the sigma-delta modulator is a first-order SDM modulator. Using a first-order SDM modulator in this solution can reduce jitter and ensure performance.

[0014] The first-order SDM modulator includes three adders. The control quantity sdm_ctrl is first added to 2^16 through an adder to become a positive number, obtaining an accumulated value. The lower 16 bits of the accumulated value are delayed by one beat and then added to the accumulated value through another adder. After the high bits perform an int operation, they are subtracted by 1 through another adder and then the fractional division value f is output.

[0015] Generally, it is difficult for the input of the SDM to be a positive number to meet the requirements of this solution. The modulator structure in the above solution makes improvements and innovations to the general first-order SDM, enabling the input to be a negative number and having more advanced functions. This structure uses 16-bit sdm, with an accuracy of up to 1 / 2^16 and relatively high control accuracy. Moreover, this structure can be implemented with only 3 adders. Compared with higher-order SDMs, the complexity is reduced a lot, the delay is reduced, and both the power consumption and the area are smaller. And from the perspective of the CDR performance index, the jitter index of this structure is the best.

[0016] In a further optimized solution, it further includes an automatic gain control module. The automatic gain control module exchanges data with the digital filter and is used to dynamically adjust the gain of the digital filter to accelerate the convergence speed.

[0017] In the above solution, by dynamically adjusting the gain of the digital filter, for example, if it is not locked, a larger gain value is used to adjust the digital filter to achieve fast locking. If it is already locked, a smaller gain value is used to reduce the bandwidth and noise, thereby reducing the jitter after convergence. Therefore, by adopting the above solution, the CDR can not only converge and lock quickly, but also have a smaller jitter after convergence. And with automatic control, the operation is simple.

[0018] A data clock recovery method based on fractional division. The phase discriminator outputs phase difference information according to the difference between the recovered clock and the phase of the input signal; the digital filter outputs the control quantity sdm_ctrl according to the phase difference information; the sigma-delta modulator outputs the fractional division value f according to the control quantity sdm_ctrl; the division coefficient of the frequency divider is an integer N, and the frequency divider performs (N + f)-times division on the input local high-speed clock signal and then outputs the recovered clock.

[0019] In a further optimized solution, during the process that the digital filter outputs the control quantity sdm_ctrl according to the phase difference information, it is detected whether the current data clock recovery has been locked. If it is not locked, the digital filter is adjusted to adopt a first gain value; if it is locked, the digital filter is adjusted to adopt a second gain value, and the first gain value is greater than the second gain value.

[0020] Compared with the prior art, the present invention is based on a digital structure, has a simple circuit, and greatly reduces the circuit complexity compared with the PI method. It can reduce the complexity of clock recovery for in-vehicle display serdes, thus bringing advantages such as chip power consumption and area. The present invention is particularly applicable to scenarios where the rate difference between high-speed signals and low-speed signals is large. The low-speed clock data recovery utilizes both high-speed clocks and fractional frequency division, and the clock jitter is completely acceptable. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Referring to the accompanying drawings, the disclosure of the present invention will become more apparent. It should be understood that these drawings are only for illustrative purposes and are not intended to limit the scope of protection of the present invention. In the figures:

[0022] Figure 1 is a schematic diagram of duplex communication.

[0023] Figure 2 is a schematic structural diagram of a data clock recovery device with a traditional PI structure.

[0024] Figure 3 is a schematic structural diagram of the data clock recovery device in Embodiment 1 of the present invention.

[0025] Figure 4 is a schematic circuit diagram of the phase detector in Embodiment 1 of the present invention.

[0026] Figure 5 is a schematic diagram of the recovered clock signal in Embodiment 1 of the present invention.

[0027] Figure 6 is a schematic circuit diagram of the filter in Embodiment 1 of the present invention.

[0028] Figure 7 is a schematic circuit diagram of the SDM modulator in Embodiment 1 of the present invention.

[0029] Figure 8 is a simulation diagram of the convergence process of the modulation control signal sdm_ctrl in Embodiment 1 of the present invention.

[0030] Figure 9 is the recovered clock eye diagram in Embodiment 1 of the present invention.

[0031] Figure 10 is a schematic structural diagram of the data clock recovery device in Embodiment 2 of the present invention.

[0032] Figure 11 is a schematic circuit diagram of the filter in Embodiment 2 of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0033] With reference to the accompanying drawings and specific embodiments, the structure, composition, features, advantages, etc. of the vehicle-mounted high-speed transmission circuit of the present invention, the serializer / deserializer including the same, and its usage method will be described by way of example below. However, all descriptions should not be used to form any limitation to the present invention.

[0034] Embodiment 1: Please refer to Figure 3 , a data clock recovery device based on fractional frequency division provided in this embodiment includes a phase detector, a digital filter, a sigma-delta modulator, and a frequency divider; the output end of the phase detector is connected to the input end of the digital filter, the output end of the digital filter is connected to the input end of the sigma-delta modulator, the output end of the sigma-delta modulator is connected to the input end of the frequency divider, the input end of the frequency divider is simultaneously connected to a local high-speed clock signal, the output end of the frequency divider is connected to the input end of the phase detector, and the input end of the phase detector is simultaneously connected to a low-speed input signal.

[0035] It is easy to understand that the high-speed signal and the low-speed signal described herein are relative concepts rather than absolute concepts, that is, among two signals, the transmission rate of one signal is higher than that of the other signal, especially when the rate difference is large. For example, the low speed is 100 Mbps and the high speed is 3.2 Gbps.

[0036] The input signal provided to the input end of the phase detector is a low-speed signal. For example, the signal is a random NRZ (non-return-to-zero code) modulation signal, or it can also be pam4, pam8, etc. The phase detector outputs phase difference information according to the difference between the recovered clock and the input signal phase. In this embodiment, a bang bang non-linear phase detector is adopted, and pe (phase lead) signal and pl (phase lag) signal are output, with values of 0 or 1. The digital filter adopts a first-order filter and outputs the control quantity sdm_ctrl of the sigma-delta modulator according to the pe information and the pl information. This control quantity represents the fractional frequency division value. The sigma-delta modulator adopts a first-order SDM modulator to convert the fractional sdm_ctrl into an integer sequence composed of 0 and 1, that is, an integer sequence is output. The frequency division coefficient of the frequency divider is N (integer frequency division), which is added to the fractional frequency division value f output by the first-order SDM modulator to obtain N + f. The local high-speed clock signal is frequency-divided by N + f to output the recovered clock. Therefore, the recovered clock frequency = high-speed clock / (N + f).

[0037] Please refer to Figure 4 , in this embodiment, the phase detector adopts a bang bang non-linear phase detector, which includes four flip-flops, three exclusive-OR gates, and two AND gates. The input low-speed signal and the recovered clock output by the frequency divider are input to the flip-flops, and after being processed by the exclusive-OR gates and the AND gates, pe signals and pl signals with values of 0 or 1 are output.

[0038] Please refer to Figure 6 , in this embodiment, the digital filter adopts a first-order filter, and this structure is a proportional-integral structure. The digital filter includes three adders and two multipliers. "++" means adding the two, "+-" means subtracting the two, and subtracting the signal corresponding to "-" from the signal corresponding to "+". The pe signal and the pl signal are subtracted by an adder to obtain the pd value. Kp is the proportional path gain, and Ki is the integral path gain. The pd value is multiplied by the integral path gain through a multiplier, and then added to the result after delaying one beat (Z -1 ) through another adder to obtain the accumulated result. The pd value is multiplied by the proportional path gain through another multiplier, and then added to the accumulated result through another adder to output the control quantity sdm_ctrl.

[0039] The digital filter can also adopt higher-order filters such as second-order filters. However, the first-order filter is simple to control, has good stability, is sufficient for applications, and has a simpler structure.

[0040] Please refer to Figure 7 , in this embodiment, a first-order SDM modulator is adopted, which includes three adders. The adder adopts a 16-bit accumulator. The input sdm_ctrl is first added to 2^16 through an adder to make the input become a positive number to obtain the accumulated value. The lower 16 bits of the accumulated value are delayed by one beat and then added to the accumulated value through another adder. After the high bits perform the int operation (rounding down), they are subtracted by 1 through another adder and then output f.

[0041] The sigma-delta modulator can also adopt higher-order modulators such as second-order modulators. However, the higher-order modulator will cause an increase in jitter. That is, adopting a first-order modulator in this embodiment can reduce jitter.

[0042] Currently, there are two types of signals, high-speed and low-speed, in in-vehicle serdes, and the rates differ greatly, for example, by 30 times or more. The previous clock data recovery only had one rate signal and mainly adopted the Figure 2 shown structure for clock data recovery. Where there is a high-speed signal, there is a high-speed clock. The present invention directly uses the high-speed clock for fractional frequency division for low-speed clock data recovery. The sigma-delta modulator cooperates with the frequency divider, and the circuit structure is much simpler.

[0043] When the integer frequency division N of the frequency divider takes the value of 80, the recovered clock is as shown in Figure 5 , and the simulation waveform is as shown in Figure 8 . The low-speed signal is 100 Mbps, and sdm_ctrl finally converges and fluctuates up and down near 0, indicating that the recovered clock correctly tracks the input signal.

[0044] Figure 9For the eye diagram of the finally recovered clock, it can be seen that the clock jitter is very small, and the peak-to-peak jitter accounts for 5% of the clock period (limited by simulation accuracy), and the jitter is sufficient to meet the requirements.

[0045] Embodiment 2: Please refer to Figure 10 and Figure 11 , the data clock recovery device based on fractional division provided in this embodiment, compared with Embodiment 1, is different in that an automatic gain control module is added on the digital filter side.

[0046] As Figure 11 shown, the automatic gain control module interacts with the digital filter to dynamically adjust the gain of the digital filter to accelerate the convergence speed. The adjustment mechanism can be: detecting whether the current data clock recovery has been locked. If not locked, the digital filter is adjusted to adopt the first gain value; if locked, the digital filter is adjusted to adopt the second gain value, and the first gain value is greater than the second gain value. That is, when not locked, the digital filter is adjusted to adopt a larger gain value to achieve quick locking, and if already locked, a smaller gain value is adopted to reduce the bandwidth and noise, thereby reducing the jitter after convergence.

[0047] In this embodiment, as Figure 11 shown, an int_val signal (the delayed value after multiplying the pd value by the integration path gain) is introduced into the digital filter, and whether the CDR is locked is detected by the change of the int_val signal. The int_val signal is collected for the first time, and after a period of timing, the int_val signal is collected for the second time. If the absolute difference between the two collected values is greater than the set threshold, it means that the CDR is not locked. If the absolute difference between the two collected values is less than or equal to the set threshold, it means that the CDR is locked. That is, with the set time period as the collection period, the current collected value is subtracted from the previous collected value. If the absolute difference is greater than the set threshold, it means that the CDR is not locked, otherwise it means that the CDR is locked.

[0048] The above-described embodiments are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention can easily think of various equivalent modifications, substitutions, and improvements, etc. These modifications, substitutions, and improvements should all be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A data clock recovery device based on fractional frequency division, characterized in that: It comprises a phase detector, a digital filter, a sigma-delta modulator and a frequency divider, wherein the output end of the phase detector is connected to the input end of the digital filter, the output end of the digital filter is connected to the input end of the sigma-delta modulator, the output end of the sigma-delta modulator is connected to the input end of the frequency divider, the input end of the frequency divider is simultaneously connected to a local high-speed clock signal, the output end of the frequency divider is connected to the input end of the phase detector, and the input end of the phase detector is simultaneously connected to a low-speed input signal; It also includes an automatic gain control module, which interacts with the digital filter for data and is used to dynamically adjust the gain of the digital filter to speed up the convergence speed; detects whether the current data clock recovery has been locked, and if not, adjusts the digital filter to use a first gain value; if locked, adjusts the digital filter to use a second gain value, and the first gain value is greater than the second gain value.

2. The data clock recovery device based on fractional frequency division according to claim 1, characterized in that: The phase detector adopts a bang-bang nonlinear phase detector, which includes four triggers, three XOR gates and two AND gates. The input low-speed signal and the recovered clock output by the divider are input into the trigger, and after being processed by the XOR gate and the AND gate, the PE signal and the PL signal with the value of 0 or 1 are output.

3. The data clock recovery device based on fractional frequency division according to claim 2, characterized in that: The digital filter is a first-order filter.

4. The data clock recovery device based on fractional frequency division according to claim 3, characterized in that: The digital filter includes three adders and two multipliers. The PE signal and the PL signal are subtracted by an adder to obtain a PD value. The PD value is multiplied by an integral path gain by a multiplier and the result delayed by one beat is accumulated by another adder to obtain the accumulated result. The PD value is multiplied by another multiplier and the proportional path gain and the result is added by another adder to output the control quantity sdm_ctrl.

5. The data clock recovery device based on fractional frequency division according to claim 3, characterized in that: The sigma-delta modulator is a first-order SDM modulator.

6. The data clock recovery device based on fractional frequency division according to claim 5, characterized in that: The first-order SDM modulator includes three adders. The control quantity sdm_ctrl is first added to 2^16 through an adder to become a positive number to obtain an accumulated value. The lower 16 bits of the accumulated value are delayed for one beat and then accumulated with the accumulated value through another adder. The high bits perform int operation and then pass through another adder to subtract 1 to output the fractional frequency division value f.

7. A data clock recovery method based on fractional frequency division, characterized in that: The phase detector outputs phase difference information according to the difference between the recovered clock and the input low-speed signal phase; The digital filter outputs a control value sdm_ctrl according to the phase difference information; the sigma-delta modulator outputs a fractional frequency division value f according to the control value sdm_ctrl; the frequency division coefficient of the frequency divider is an integer N, and the frequency divider divides the input local high-speed clock signal by N+f times and then outputs the recovered clock; In the process of the digital filter outputting the control amount sdm_ctrl according to the phase difference information, it is detected whether the current data clock recovery has been locked. If not locked, the digital filter is adjusted to use the first gain value; if locked, the digital filter is adjusted to use the second gain value, and the first gain value is greater than the second gain value.

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