Power adaptive frame synchronization module and synchronization method in high dynamic environment

Abstract

The present invention discloses a power adaptive frame synchronization method in a high dynamic environment, which mainly solves the problem of frame synchronization performance degradation caused by power fluctuation in the prior art in a high dynamic environment. The implementation scheme is as follows: the data received by the receiving end is pre-processed and divided into two data paths, one of which is cached, and the other path is used to calculate and integrate the differential correlation values ​​of the frame header and the physical layer signaling, and perform addition and subtraction operations on them, and the maximum modulus value is selected as the total correlation value C A ; In direct output correlation value mode according to C A Calculate the differential correlation peak-to-average ratio and calculate the C A After accumulation, the differential correlation peak-to-average ratio is calculated; the position where the peak-to-average ratio exceeds the decision threshold is stored and counting begins at this position; the frame length is compared with the count value to determine the frame header position; a frame of data is output from the frame header position, completing frame synchronization for the frame. This invention can reduce the impact of frequency shift and power fluctuation on frame synchronization performance and can be used in satellite communication systems.

Description

Technical Field

[0001] The present invention belongs to the field of satellite communication technology, and in particular relates to a power adaptive frame synchronization method, which can be used in satellite communication systems with high dynamic, large-range Doppler frequency shift and large fluctuation of received signal power. Background Art

[0002] Frame synchronization is a crucial component of communication systems, encompassing two key components: acquisition and tracking. The probability of successful acquisition and the accuracy of the synchronization position are crucial to the communication system. Acquisition is the first stage of the frame synchronization process, aiming to quickly detect the start of the frame. Tracking, performed after acquisition, aims to continuously track frame boundaries after successful acquisition, ensuring the receiver remains synchronized throughout the entire signal transmission process.

[0003] Patent application number CN200910056967.0 discloses a method for achieving frame synchronization in a frame detection system with correlation characteristics. This method performs a correlation operation on the received signal, obtains the absolute value of the correlation operation, and then uses two sliding windows of unequal lengths to determine the peak and mean values ​​of the correlation values ​​based on the absolute value. When both the peak value and the peak-to-average ratio are greater than their respective thresholds, synchronization information is considered to have been achieved. However, this method cannot handle the large-scale Doppler frequency deviation caused by the high dynamics of satellite communication scenarios. This affects the phase of the received signal, which in turn affects the correlation operation results and degrades frame synchronization performance.

[0004] Patent application number CN201110435510.8 discloses a joint multi-strategy OFDM frame synchronization method. This method first calculates the cross-correlation value between a received signal sequence and a local training sequence, then calculates the autocorrelation value of the received signal sequence. If both the cross-correlation value and the autocorrelation value are greater than a set decision threshold, a peak search is performed on the autocorrelation result to obtain a timing position. Finally, the position of the received signal sequence is adjusted based on the timing position to obtain a frame synchronization result. While this method can effectively resist missynchronization caused by interference such as noise, carrier frequency offset, and co-frequency signals, it cannot cope with the effects of received signal power fluctuations in satellite communication scenarios. Therefore, when the received signal power decreases, the correlation peak may fall below the fixed decision threshold, resulting in missed detections. When the received signal power increases, the spurious correlation peak may exceed the fixed decision threshold, resulting in false alarms. Frequent missed detections and false alarms can affect frame synchronization performance. Summary of the Invention

[0005] The purpose of the present invention is to address the deficiencies of the above-mentioned prior art and propose a power adaptive frame synchronization method in a high dynamic environment to reduce the impact of large-scale Doppler frequency shift on the correlation operation results, reduce the impact of the received signal power fluctuation range on the fixed decision threshold, and improve the performance of frame synchronization.

[0006] The technical ideas for achieving the purpose of the present invention are: by performing a differential correlation operation on the received signal and a locally pre-stored sequence, the influence of a large range of Doppler frequency shift on the correlation operation result is reduced; by calculating the differential correlation peak-to-average ratio, the influence of the received signal power fluctuation range on the fixed decision threshold is reduced; and by combining multi-frame decisions, the accuracy of frame synchronization is improved.

[0007] According to the above ideas, the technical solutions of the present invention are as follows:

[0008] 1. A power adaptive frame synchronization module for high dynamic environments, implemented by FPGA, characterized by comprising:

[0009] The data storage submodule is used to cache the input data and output the data after waiting for the synchronization success indication;

[0010] The differential correlation submodule is used to calculate the differential correlation value of the input data and send the calculated differential correlation value to the data shift register submodule;

[0011] The data shift register submodule is used to shift and register the calculated differential correlation value, and provide the stored result to the correlation value integration submodule;

[0012] The correlation value integration submodule has two working modes. The first mode is used to calculate the integral value of all data in the data shift register submodule, perform addition and subtraction operations on the integral value and take the modulus, and output the largest modulus value to the sliding window submodule. The second mode is used to calculate the integral value of all data in the data shift register submodule, perform addition and subtraction operations on the integral value and take the modulus, cache the largest modulus value, add the cached value to the new maximum modulus value after the cache is full, and output the result to the sliding window submodule.

[0013] The sliding window submodule is used to store the calculated integral value, calculate the differential correlation peak-to-average ratio, and output it to the peak-to-average ratio judgment submodule;

[0014] The peak-to-average ratio decision submodule is used to compare the differential correlation peak-to-average ratio with the decision threshold, record the position of the peak-to-average ratio greater than the decision threshold, and send the recorded position to the joint multi-frame decision submodule;

[0015] The joint multi-frame decision submodule is used to calculate the distance between the positions given by the peak-to-average ratio decision submodule, and make a decision on the synchronization result based on the calculated distance, and then output the decision result and the position to the output control submodule;

[0016] The output control submodule is used to control the data of the data storage submodule to be output from the received location.

[0017] 2. A method for power adaptive frame synchronization in a high dynamic environment using the frame synchronization module of claim 1, characterized by comprising the following:

[0018] 1) Pre-process the data received by the receiving antenna and divide the pre-processed data into two paths. The first path of data enters the data storage submodule and outputs the data after waiting for frame synchronization to succeed; the second path of data enters the differential correlation submodule and performs frame header differential correlation value C Sn and the physical layer signaling differential correlation value C Pk Calculation of

[0019] 2) The frame header differential correlation value C Sn and the physical layer signaling differential correlation value C Pk Input into two data shift register submodules and data shift register submodule respectively, and after they are filled with data, integrate the data therein to obtain the integral value C S and C P , then C S and C P Perform addition and subtraction operations, and take the modulus of the results of the addition and subtraction operations, and select the largest modulus value as the total correlation value C A :

[0020] 3) According to the different working modes of the correlation value integration submodule, C A Perform different processing and calculate the differential correlation peak-to-average ratio P A :

[0021] When the correlation value integration submodule is in the first mode, C A Enter the sliding window and find the maximum value C m When it appears in the center of the sliding window, first calculate the mean μ1 of the data in the sliding window, and then calculate the differential correlation peak-to-average ratio P based on the mean. A ;

[0022] When the correlation value integration submodule is in the second mode, the C A Cache, and when the cache is full, the newly cached C A Compared with the original C A Add up to get the cumulative correlation value C B , and C B Enter the sliding window, at the maximum value Cm When it appears in the center of the sliding window, first calculate the mean μ2 of the data in the sliding window, and then calculate the differential correlation peak-to-average ratio P based on the mean. A ;

[0023] 4) The differential correlation peak-to-average ratio P A and the preset decision threshold T h For comparison:

[0024] If P A ≥T h , then record the position of the differential correlation peak-to-average ratio and execute step 5);

[0025] If P A <T h , no processing is done;

[0026] 5) The joint multi-frame decision submodule first stores the positions sent by the peak-to-average ratio decision submodule, and then checks the number of positions in the joint multi-frame decision submodule:

[0027] If there is only one position in the joint multi-frame decision submodule, start counting and return to step 1);

[0028] If there are two positions in the joint multi-frame decision submodule, stop counting and execute step 6);

[0029] 6) Set the count value C n With a frame length L f For comparison:

[0030] If C n =L f , then the position when counting starts is considered to be the frame head position P h , proceed to step 7)

[0031] If C n ≠L f , the position at which counting started is considered invalid and discarded. At this time, only the position at which counting stopped remains in the joint multi-frame decision submodule, and counting starts again from this position, and returns to step 1);

[0032] 7) Outputting the frame header position to the output control submodule, the output control submodule controls the data storage submodule to output a frame of data starting from the frame header position according to the received frame header position.

[0033] Compared with the prior art, the present invention has the following advantages:

[0034] Firstly, the present invention adopts differential correlation to calculate the correlation value between the received signal and the locally pre-stored sequence, thereby offsetting the frequency shift of the received signal, reducing the influence of the Doppler effect, and improving the accuracy and stability of the correlation operation.

[0035] Secondly, since the present invention adopts the differential correlation peak-to-average ratio as the decision condition for frame synchronization, it can reduce the impact of the received signal power fluctuation on the fixed decision threshold, thereby reducing the impact of signal power changes during satellite communication.

[0036] Thirdly, since the present invention adopts a joint multi-frame decision method, by accumulating the differential correlation values ​​of two adjacent frames of data, the amount of data used to calculate the differential correlation peak-to-average ratio is increased, thereby improving the accuracy of the differential correlation peak-to-average ratio; at the same time, since the judgment result of the previous frame data is verified by calculating the distance between two peak-to-average ratio positions greater than the decision threshold, the accuracy of frame synchronization is further improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 This is a block diagram of the adaptive frame synchronization module in the present invention;

[0038] Figure 2 yes Figure 1 Schematic diagram of the sliding window module in;

[0039] Figure 3 This is the implementation process of the power adaptive frame synchronization method in a high dynamic environment of the present invention;

[0040] Figure 4 It is a data flow diagram of the receiving end of the present invention. DETAILED DESCRIPTION

[0041] The embodiments of the present invention are described in further detail below with reference to the accompanying drawings.

[0042] Embodiment 1: A power adaptive frame synchronization module in a high dynamic environment.

[0043] Reference Figure 1 The adaptive frame synchronization module of this embodiment includes a data storage submodule 1, a differential correlation submodule 2, a data shift register submodule 3, a correlation value integration submodule 4, a sliding window submodule 5, a peak-to-average ratio decision submodule 6, a joint multi-frame decision submodule 7, and an output control submodule 8, wherein:

[0044] The data storage submodule 1 is used to store data input to the frame synchronization module and output the data from the frame header position after the output control submodule provides output enable and frame header position. Since the FIFO memory in the FPGA can only use the first-in-first-out mode and cannot start output from a specified position, this example uses but is not limited to using a RAM memory with a specified depth to store data;

[0045] The differential correlation submodule 2 is used to calculate the differential correlation value of the input data and send the calculated differential correlation value to the data shift register submodule, wherein the calculation of the differential correlation value is divided into two parts, one is the differential correlation value of the frame header, and the other is the differential correlation value of the physical layer signaling; because directly using the multiplication sign to perform multiplication operations when writing code in the FPGA consumes a large amount of lookup table resources and is prone to timing violations when the data is large, this example adopts but is not limited to using a complex multiplier to perform multiplication operations;

[0046] The data shift register submodule 3 is used to shift and register the calculated differential correlation value and provide the stored result to the correlation value integration submodule. Since the FPGA can only calculate the differential correlation value between the current input data and the locally pre-stored sequence in each cycle, it is necessary to register the calculated result. This example uses, but is not limited to, a register of the reg type with a specified length, and shifts and registers the data in the register in each cycle.

[0047] The correlation value integration submodule 4 has two operating modes. The first mode is used to calculate the integral value of all data in the data shift register submodule, perform addition and subtraction operations on the integral value, and take the modulus, and output the maximum modulus value to the sliding window submodule. The second mode is used to calculate the integral value of all data in the data shift register submodule, perform addition and subtraction operations on the integral value, and take the modulus, cache the maximum modulus value, add the cached value to the new maximum modulus value after the cache is full, and output the result to the sliding window submodule. Because FPGA is a sequential logic, processing too much data in one cycle may cause timing violations. Therefore, in this example, a binary division method is used for multiple addition and assignment. That is, in the first cycle, the sum of two adjacent data in the data shift register is first calculated and the summed data is stored. In the second cycle, the data obtained in the previous cycle are summed again. Similarly, in the nth cycle, the data obtained in the previous (n-1)th cycle are summed together until a final data sum is obtained.

[0048] The sliding window submodule 5 is used to store the calculated data sum, calculate the differential correlation peak-to-average ratio, and output it to the peak-to-average ratio judgment submodule. In this example, a register of the reg type of specified length is used but not limited to. When new data enters each cycle, the register is shifted, and the data input in the current cycle is compared with the old data input in the previous cycle to find the maximum value of the data in the sliding window. When new data enters each cycle, the data is accumulated to find the mean of the data in the sliding window. When the maximum value of the data appears in the center of the sliding window, the differential correlation peak-to-average ratio is obtained by dividing the maximum value of the data by the mean. The length of the sliding window in this example is 16. The length of the sliding window can be set to any value, but if the length of the sliding window is too short, the differential correlation peak-to-average ratio will be inaccurate, thereby affecting the frame synchronization performance. If the length of the sliding window is too long, the delay will increase and the mean will decrease, causing the calculated differential correlation peak-to-average ratio to increase. If the preset judgment threshold is not modified at this time, a large number of false alarms will occur in the frame synchronization, such as Figure 2 shown.

[0049] The peak-to-average ratio decision submodule 6 is used to compare the differential correlation peak-to-average ratio with a preset decision threshold, record the position of the differential correlation peak-to-average ratio greater than the decision threshold, and send the recorded position to the joint multi-frame decision submodule;

[0050] The joint multi-frame decision submodule 7 is used to calculate the distance between the positions given by the peak-to-average ratio decision submodule, and to make a decision on the synchronization result based on the calculated distance, and then output the decision result and the position to the output control submodule; in this example, a reg type register of a specified length is used as a counter but is not limited to the use of the reg type register as a counter to count the distance between the positions.

[0051] The output control submodule 8 is used to control the data of the data storage submodule to be output from the received location. In this embodiment, a three-stage state machine is used but not limited to control the data output of the data storage submodule.

[0052] Embodiment 2: A power adaptive frame synchronization method in a high dynamic environment.

[0053] Reference Figure 3 The implementation steps of this example include the following:

[0054] Step 1: pre-process the analog signal received by the antenna.

[0055] 1.1) Perform analog-to-digital conversion on the analog signal received by the antenna. In this example, an analog-to-digital converter with chip model ADS54J69 is used for analog-to-digital conversion, but is not limited to the chip model ADS54J69. The implementation includes the following:

[0056] 1.1.1) The received analog signal is sampled using the analog-to-digital converter's clock to obtain sampled data. Since the sampled data becomes discrete data and cannot represent continuous amplitude values, it is necessary to quantize the sampled data using a preset quantization level;

[0057] 1.1.2) Encoding the quantized data using binary data to convert the analog signal into a binary digital signal;

[0058] 1.2) Demodulate the signal after analog-to-digital conversion:

[0059] 1.2.1) Generate a demodulation carrier: This example uses, but is not limited to, a DDS signal generator embedded in the FPGA to generate a demodulation carrier. The carrier uses, but is not limited to, a sine wave and a cosine wave with an intermediate frequency of 365.25 MHz.

[0060] 1.2.2) Use a multiplier to multiply the analog-to-digital converted signal by the generated sine wave and cosine wave, respectively, to obtain the in-phase and quadrature components of the signal. The in-phase component is used as the real part, and the quadrature component is used as the imaginary part to form a complex signal.

[0061] 1.3) Match filtering is performed on the complex signal to maximize the signal-to-noise ratio. In this example, a root raised cosine filter with a roll-off coefficient of 0.35 is used to perform matched filtering on the complex signal. A multiplier is used to multiply the input complex signal by a preset filter coefficient to obtain a matched filtered signal, completing the preprocessing of the analog signal. The preprocessed data enters the frame synchronization module, such as Figure 4 shown.

[0062] Step 2: Store the preprocessed data and calculate the differential correlation value.

[0063] This step is to divide the pre-processed data into two paths, one for storage and the other for differential correlation value calculation. The specific implementation is as follows:

[0064] 2.1) Send the first channel of data to the data storage submodule:

[0065] This example uses but is not limited to using RAM memory to store data. When the pre-processed data arrives, the data storage submodule generates a write enable and a corresponding write address to write the pre-processed data into the RAM memory;

[0066] 2.2) Send the second data to the differential correlation submodule and perform frame header differential correlation value C Sn and the physical layer signaling differential correlation value C Pk Calculation:

[0067] 2.2.1) Use a complex multiplier to multiply the pre-processed signal by the locally stored frame header sequence to obtain the frame header differential correlation value C Sn :

[0068]

[0069] where R n+i is the n+ith number received, n=1,2,…,25-i, i is the differential distance,

[0070] R n is the nth number received, Indicates taking R n The complex conjugate of

[0071] C SOF is a locally pre-stored frame header related sequence, which is expressed as:

[0072] C SOF =j*(1,1,1,1,-1,-1,-1,-1,1,-1,-1,-1,1,-1,-1,1,1,-1,1,1,-1,1,-1,-1,1),

[0073] C SOF (n) means C SOF The nth data in , j represents the imaginary unit;

[0074] 2.2.2) Use a complex multiplier to multiply the pre-processed signal by the locally stored physical layer signaling correlation sequence to obtain the physical layer signaling differential correlation value C Pk :

[0075]

[0076] where R 2k-1 is the 2k-1th number received, k=14,15,…,45,

[0077] R 2k is the 2kth number received, Indicates taking R 2k The complex conjugate of

[0078] C PLS is a locally stored physical layer signaling related sequence, which is expressed as:

[0079] C PLS =j*(-1,1,1,-1,-1,-1,1,-1,-1,1,1,1,1,1,-1,-1,-1,-1,1,1,-1,1,1,-1,1,-1,1,-1,1,1,-1,-1),

[0080] CPLS (k-13) represents C PLS The k-13th data in .

[0081] Step 3: Differential correlation value C of the frame header Sn and the physical layer signaling differential correlation value C Pk Integrate and get the integral value C S and C P .

[0082] 3.1) The frame header differential correlation value C Sn Input to the first data shift register submodule, and when it is filled with data, add the data in it two by two and store the result in a new shift register; add the result in two by two and store it; and so on, until the final data sum is obtained, which is the integral value C S ;

[0083] 3.2) The frame header differential correlation value C Pk Input to the second data shift register submodule, and when it is filled with data, add the data in pairs and store the result in a new shift register; add the result in pairs and store it; and so on, until the final data sum is obtained, which is the integral value C P .

[0084] Step 4: For the integral value C S and C P Perform addition and subtraction operations, and take the modulus of the results of the addition and subtraction operations, and select the largest modulus value as the total correlation value C A :

[0085] C A =max(|C S +C P |,|C S -C P |)

[0086] Among them, |C S +C P | means take C S +C P The modulus value,

[0087] |C S -C P | means take C S -C P The modulus value of .

[0088] Step 5: C A Perform different processing and calculate the differential correlation peak-to-average ratio P A .

[0089] The working modes of this example are divided into two modes: directly outputting correlation values ​​and caching correlation values. The post-module of the frame synchronization module calculates the signal-to-noise ratio of the current signal and returns it to the frame synchronization module. When the signal-to-noise ratio is greater than or equal to 10dB, the correlation value integration submodule adopts the direct output correlation value mode. When the signal-to-noise ratio is less than 10dB, the correlation value integration submodule adopts the cached correlation value mode.

[0090] When the correlation value integration submodule is in the direct output correlation value mode, C A The data is sent to the sliding window, and when the maximum value Cm1 of the data appears in the center of the sliding window, the mean μ1 of the data in the sliding window is calculated first, and then the differential correlation peak-to-average ratio P is calculated based on the mean. A1 :

[0091]

[0092] Among them C A d represents the dth data in the sliding window, L represents the length of the sliding window, C m1 It is the maximum value of the data in the center of the sliding window in the output correlation value mode.

[0093] When the correlation value integration submodule is in the cache correlation value mode, A Cache, and when the cache is full, the newly cached C A Compared with the original C A Add up to get the cumulative correlation value C B , and C B Enter the sliding window, at the maximum value C m2 When it appears in the center of the sliding window, first calculate the mean μ2 of the data in the sliding window, and then calculate the differential correlation peak-to-average ratio P based on the mean. A ;

[0094]

[0095] Among them C Be represents the e data in the sliding window, L represents the length of the sliding window, C m2 The maximum value of the data in the center of the sliding window in the cache related value mode.

[0096] Step 6: The differential correlation peak-to-average ratio P A and the preset decision threshold T h Make a comparison.

[0097] The differential correlation peak-to-average ratio P A Including P A1 and P A2 , that is, when the correlation value integration submodule is in the direct output correlation value mode, it is P A =PA1 , when the correlation value integration submodule is in the cache correlation value mode, it is P A =P A2 .

[0098] The decision threshold T in this step h The threshold value is adopted but not limited to 100. This threshold value is the value when the frame synchronization performance is better after board debugging.

[0099] If P A ≥T h , then record the position of the differential correlation peak-to-average ratio and send the position to the joint multi-frame decision submodule to execute step 7;

[0100] If P A <T h , then return to step 1;

[0101] Step 7: Determine whether to start or stop the counter according to the number of positions in the joint multi-frame decision submodule.

[0102] In this step, the counter uses but is not limited to a reg type register of a specified length, which is implemented as follows:

[0103] If there is only one position in the joint multi-frame decision submodule, start counting and return to step 1;

[0104] If there are two positions in the joint multi-frame decision submodule, stop counting and execute step 8;

[0105] Step 8, by counting value C n Get the frame header position P h .

[0106] 8.1) According to the frame structure, the length of a frame data is L f Set to 11232. In practice, different frame lengths will be obtained according to different frame structures.

[0107] 8.2) Set the count value C n With a frame length L f For comparison:

[0108] If C n =L f , then the position when counting starts is considered to be the frame head position P h , go to step 9;

[0109] If C n ≠L f , the position at which counting started is considered invalid and discarded. At this time, only the position at which counting stopped remains in the joint multi-frame decision submodule, and counting starts again from this position, returning to step 1.

[0110] Step 9: According to the frame header position P h , start outputting a frame of data.

[0111] Set the frame header position P h The data is sent to the output control submodule to control it to start outputting data. In this step, the output control submodule adopts but is not limited to a three-stage state machine to control the data storage submodule. The specific implementation is as follows:

[0112] When the frame header position P is not received h When , the state machine is in idle state, and the data storage submodule does not output data;

[0113] When the frame header position P is received h After that, the data storage submodule generates a read enable and sets the P h As the starting read address, start outputting a frame of data.

[0114] After one frame of data is output, return to step 1 and start frame synchronization for the new frame of data.

[0115] The above descriptions are merely two specific examples of the present invention and do not constitute any limitation to the present invention. Obviously, after understanding the content and principles of the present invention, professionals in this field may make various modifications and changes in form and details without departing from the principles and structure of the present invention. However, these modifications and changes based on the ideas of the present invention are still within the scope of protection of the claims of the present invention.

[0116] It should be noted that the step numbers in the specification and claims of the present invention are only for the purpose of clearly describing the embodiments of the present invention and facilitating understanding, and the order of the step numbers is not limited.

Claims

1. A power adaptive frame synchronization module for high dynamic environments, implemented using FPGA, characterized by: include: A data storage submodule (1) is used to cache input data and output the data after waiting for a synchronization success indication; The differential correlation submodule (2) is used to calculate the differential correlation value of the input data and send the calculated differential correlation value to the data shift register submodule; A data shift register submodule (3) is used to shift and register the calculated differential correlation value, and provide the stored result to the correlation value integration submodule; The correlation value integration submodule (4) has two working modes. The first mode is used to calculate the integral value of all data in the data shift register submodule, perform addition and subtraction operations on the integral value and take the modulus, and output the largest modulus value to the sliding window submodule; the second mode is used to calculate the integral value of all data in the data shift register submodule, perform addition and subtraction operations on the integral value and take the modulus, cache the largest modulus value, add the cached value to the new largest modulus value after the cache is full, and output the result to the sliding window submodule; The sliding window submodule (5) is used to store the calculated integral value, calculate the differential correlation peak-to-average ratio, and output it to the peak-to-average ratio judgment submodule; The peak-to-average ratio decision submodule (6) is used to compare the differential correlation peak-to-average ratio with the decision threshold, record the position of the peak-to-average ratio greater than the decision threshold, and send the recorded position to the joint multi-frame decision submodule; A combined multi-frame decision submodule (7) is used to calculate the distance between the positions given by the peak-to-average ratio decision submodule, and to make a decision on the synchronization result based on the calculated distance, and then output the decision result and the position to the output control submodule; The output control submodule (8) is used to control the data of the data storage submodule to be output from the received location.

2. A method for power adaptive frame synchronization in a high dynamic environment using the frame synchronization module of claim 1, characterized in that: These include: 1) Pre-process the data received by the receiving antenna and divide the pre-processed data into two paths. The first path of data enters the data storage submodule and outputs the data after waiting for frame synchronization to succeed; the second path of data enters the differential correlation submodule and performs frame header differential correlation value C Sn and the physical layer signaling differential correlation value C Pk Calculation of 2) The frame header differential correlation value C Sn and the physical layer signaling differential correlation value C Pk Input them into two data shift register submodules respectively. After they are filled with data, the data is integrated to obtain the integral value C. S and C P , then C S and C P Perform addition and subtraction operations, and take the modulus of the results of the addition and subtraction operations, and select the largest modulus value as the total correlation value C A : 3) According to the different working modes of the correlation value integration submodule, C A Perform different processing and calculate the differential correlation peak-to-average ratio P A : When the correlation value integration submodule is in the first mode, C A Enter the sliding window and find the maximum value C m1 When it appears in the center of the sliding window, first calculate the mean μ1 of the data in the sliding window, and then calculate the differential correlation peak-to-average ratio P based on the mean. A1 ; When the correlation value integration submodule is in the second mode, the C A Cache, and when the cache is full, the newly cached C A Compared with the original C A Add up to get the cumulative correlation value C B , and C B Enter the sliding window, at the maximum value C m2 When it appears in the center of the sliding window, first calculate the mean μ2 of the data in the sliding window, and then calculate the differential correlation peak-to-average ratio P based on the mean. A2 ; 4) The differential correlation peak-to-average ratio P A and the preset decision threshold T h For comparison: In this step, the differential correlation peak-to-average ratio P A Including P A1 and P A2 , when the correlation value integration submodule is in the first mode, it is P A =P A1 , when the correlation value integration submodule is in the second mode, it is P A =P A2； If P A ≥T h , then record the position of the differential correlation peak-to-average ratio and execute step 5); If P A <T h , then return to step 1); 5) The joint multi-frame decision submodule first stores the positions sent by the peak-to-average ratio decision submodule, and then checks the number of positions in the joint multi-frame decision submodule: If there is only one position in the joint multi-frame decision submodule, start counting and return to step 1); If there are two positions in the joint multi-frame decision submodule, stop counting and execute step 6); 6) Set the count value C n With a frame length L f For comparison: If C n =L f , then the position when counting starts is considered to be the frame head position P h , proceed to step 7) If C n ≠L f , the position at which counting started is considered invalid and discarded. At this time, only the position at which counting stopped remains in the joint multi-frame decision submodule, and counting starts again from this position, and returns to step 1); 7) Outputting the frame header position to the output control submodule, the output control submodule controls the data storage submodule to output a frame of data starting from the frame header position according to the received frame header position.

3. The method according to claim 2, characterized in that In step 1), the data received by the receiving antenna is preprocessed, and the implementation steps include the following: 1a) Converting the continuously changing analog signal received by the receiving antenna into a discrete digital signal through an analog-to-digital converter; 1b) Multiplying the discrete digital signal by the locally recovered carrier wave to complete demodulation of the discrete digital signal, thereby obtaining the original data sent by the transmitter; 1c) Use a root raised cosine filter with a roll-off factor of 0.35 to perform matched filtering on the original data sent by the transmitter, so that the original data has a maximum signal-to-noise ratio and improves frame synchronization performance.

4. The method according to claim 2, characterized in that Calculate the frame header differential correlation value C in step 1) Sn , the formula is as follows: where R n+i is the n+ith number received, n=1,2,...,25-i, i is the differential distance, R n is the nth number received, Indicates taking R n The complex conjugate of C SOF is a locally pre-stored frame header related sequence, which is expressed as: C SOF =j*(1,1,1,1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,1,-1,-1,-1,1,-1,-1,-1,1), where j represents the imaginary unit, C SOF (n) means C SOF The nth data in .

5. The method according to claim 2, characterized in that Step 1) Calculate the physical layer signaling differential correlation value C Pk , the formula is as follows: where R 2k-1 is the 2k-1th number received, k=14,15,...,45, R 2k is the 2kth number received, Indicates taking R 2k The complex conjugate of C PLS is a locally stored physical layer signaling related sequence, which is expressed as: C PLS =j*(-1, 1, 1, -1, -1, 1, -1, 1, -1, 1, 1, 1, 1, -1, -1, -1, -1, 1, 1, -1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1), where j represents the imaginary unit, C PLS (k-13) represents C PLS The k-13th data in .

6. The method according to claim 2, characterized in that In step 2), the data in the data shift register submodule is integrated to obtain the integral value C S , which is implemented as follows: 2a) Adding the data in the first data shift register submodule in pairs, and storing the added result in a new shift register; 2b) adding the added data two by two adjacently and storing them; 2c) Repeat step 2b) until you get the final sum, which is the integral value C S .

7. The method according to claim 2, characterized in that In step 2), the data in the data shift register submodule is integrated to obtain the integral value C P , which is implemented as follows: 2d) adding the data in the second data shift register submodule in pairs, and storing the added result in a new shift register; 2e) adding the added data again in pairs and storing them; 2f) Repeat step 2e) until you get the final sum, which is the integral value C P .

8. The method according to claim 2, characterized in that In step 2) S and C P Perform addition and subtraction operations, and take the modulus of the results of the addition and subtraction operations, and select the largest modulus value as the total correlation value C A , the formula is as follows: C A =max(|C S +C P |,|C S -C P |) Among them, max means taking the maximum value of two data. |C S +C P | means take C S +C P The modulus value, |C S -C P | means take C S -C P The modulus value of .

9. The method according to claim 2, characterized in that In step 3), the mean μ1 and μ2 of the data in the sliding window and the differential correlation peak-to-average ratio P are calculated. A1 and P A2 , the formula is as follows: Among them C Ad Indicates the d-th data in the sliding window of the first working mode, C Be Represents the e-th data in the sliding window of the second working mode, L represents the length of the sliding window, C m1 is the maximum value of the data in the center of the sliding window in the first working mode, C m2 It is the maximum value of the data in the center of the sliding window in the second working mode.

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