Miniaturized imaging circuit architecture based on CMOS detector

Abstract

The invention discloses a miniaturized imaging circuit architecture based on a CMOS (Complementary Metal Oxide Semiconductor) detector. Sandwich-type architecture design is adopted, according to main realization function division, the upper layer is a focal plane circuit, and detector power supply, detector installation and detector data transmission are realized. And the middle layer is a signal processing circuit, realizes high-speed data storage and processing, realizes instruction receiving, analysis and execution, and realizes on-orbit uploading and refreshing of a program. And the bottom layer is an interface power supply circuit to realize high-efficiency low-noise power supply filtering and power-on time sequence control of a complex circuit. The three layers of circuits are directly connected through the connectors for signal transmission and chip power supply, so that the defects of large size, long signal transmission distance, difficulty in maintenance and the like caused by signal transmission through flexible circuit connection are overcome, noise and interference are reduced, and signal arrangement of connectors between boards is optimized. Miniaturization, integration and multi-interface design in the technical field of high-performance detectors and focal planes are realized, and reliability and stability are improved.

Description

Technical Field

[0001] The invention relates to a miniaturized imaging circuit architecture based on a CMOS detector, and belongs to the technical field of high-performance detectors and focal planes. Background Art

[0002] In recent years, domestic CMOS detectors have developed rapidly. In the field of aerospace remote sensing, small-array CMOS detectors are mainly used for high-resolution imaging of space targets, ground lightning observation, and imaging of space targets and stellar backgrounds. With the rapid development of domestic small-array CMOS detectors, the application demand for small-array CMOS detectors in the field of aerospace remote sensing has gradually increased. Therefore, personalized imaging circuit architectures that meet different needs have emerged in an endless stream, and most of them are flexible circuits for connecting various functional modules. In the face of different application requirements, CMOS imaging circuit designs are of many types, with long design cycles, single application scenarios, single transmission interfaces, low integration, and cannot be reused in the face of different requirements. In the prior art, imaging circuits mostly adopt a split architecture, use flexible boards to transmit signals over long distances, have high requirements for flexible board substrates and conductive media, and transmit signals of many types and in large quantities, resulting in a large volume of circuit boxes. Taking into account different application requirements, different CMOS detector requirements, and different data transmission interfaces and parameter control interface requirements, it is necessary to invent an imaging circuit architecture with a short design cycle, short signal transmission distance, maturity and multi-functional compatibility. It is divided into three circuits according to the main functions, adopts a sandwich architecture, and realizes the development ideas of miniaturization, productization and integration, and is easy to maintain to meet the needs of complex applications. Summary of the invention

[0003] The technical problem solved by the present invention is to overcome the deficiencies of the prior art and provide a miniaturized imaging circuit architecture based on a CMOS detector.

[0004] The technical solution of the present invention is:

[0005] The present invention discloses a miniaturized imaging circuit architecture based on a CMOS detector, comprising: an interface power supply circuit, a signal processing circuit, a focal plane circuit, a first inter-board connector and a second inter-board connector; wherein:

[0006] It adopts a sandwich structure design, with the upper layer being the focal plane circuit, the middle layer being the signal processing circuit, and the bottom layer being the interface power circuit; the interface power circuit provides multiple power signals for the signal processing circuit, and the signal processing circuit provides multiple power signals for the focal plane circuit; the focal plane circuit performs voltage conversion according to the selected CMOS detector power supply type to provide power for the CMOS detector;

[0007] The focal plane circuit and the signal processing circuit are connected through a first inter-board connector, and the CMOS detector data received by the focal plane circuit is transmitted to the signal processing circuit through the first inter-board connector; the signal processing circuit performs image caching and processing, and outputs the processed image data to the outside through the signal processing circuit, or transmits it to the interface power supply circuit through the second inter-board connector; the interface power supply circuit outputs to the outside through different interfaces.

[0008] Furthermore, in the above architecture, the interface power supply circuit includes a power supply filter circuit, a multi-channel DC-DC circuit, a first π-type filter network and an LDO circuit; wherein;

[0009] The external power supply passes through the power filter circuit, and then through the DC-DC circuit, the first π-type filter network and the LDO circuit for low-noise voltage conversion, filtering and power-on timing control, and is provided to the signal processing circuit through the inter-board connector with 7 power signals of different voltages.

[0010] Furthermore, in the above-mentioned architecture, the power supply filter circuit includes diodes D1, D2, resistors R1, R2 and a second π-type filter network; wherein the series-connected diodes D1 and D2 are connected in parallel with the series-connected resistors R1 and R2 to form a parallel circuit; the input power supply of the parallel circuit is connected to the external input power supply, and the input ground is connected to the external input ground; resistors R1 and R2 limit the current of the external input power supply and filter the noise; and the second π-type filter network is connected in parallel with the parallel circuit.

[0011] Furthermore, in the above architecture, the interface power supply circuit further includes a plurality of CAN bus interface chips, a plurality of RS-422 receiving interface chips, a plurality of RS-422 transmitting interface chips and a plurality of LVDS transmitting interface chips; wherein,

[0012] CAN bus interface chip, with 2-way transceiver function of CAN bus communication interface, realizes imaging circuit parameter control reception and telemetry data transmission;

[0013] RS-422 receiving interface chip and RS-422 transmitting interface chip, with RS-422 bus 9-way receiving capability, realize RS-422 second pulse, frame synchronization, parameter control receiving and injection interface receiving communication functions and application demand signal receiving, with RS-422 bus 4-way sending and receiving functions, both sending and receiving functions have redundant backup;

[0014] The LVDS transmission interface chip has two sets of data transmission interfaces, the main and the backup, including clock, gating and data signals.

[0015] Further, in the above architecture, the signal processing circuit includes an FPGA chip, a refresh circuit, a Flash memory, a 2711 interface chip, a CXP interface chip, a DDR3 memory chip, a first differential crystal oscillator, a second differential crystal oscillator, a third differential crystal oscillator, a fourth single-ended crystal oscillator, and a fifth differential crystal oscillator; wherein the FPGA chip realizes data information processing and instruction parsing and execution;

[0016] Refresh circuit, refresh and program the FPGA chip;

[0017] Flash memory, for multiple backup storage of programs;

[0018] 2711 interface chip and CXP interface chip for data transmission;

[0019] DDR3 memory chip, used for caching CMOS detector image data, can expand data width or perform ping-pong operation to cache detector image data;

[0020] The first differential crystal oscillator provides the main clock for the FPGA chip;

[0021] The second differential crystal oscillator and the third differential crystal oscillator are used to provide a clock for the DDR3 memory chip;

[0022] The fourth single-ended crystal oscillator provides a working clock for the refresh circuit;

[0023] The fifth differential crystal oscillator provides clock for the high-speed SerDes interface of the FPGA chip.

[0024] Furthermore, in the above architecture, the focal plane circuit includes a CMOS detector; wherein the CMOS detector receives three power supplies from the signal processing circuit, and completes the power supply of the detector according to the type of the CMOS detector; the CMOS detector receives a register configuration signal from the signal processing circuit through the first inter-board connector, and returns a readout signal, and the output CMOS image data is transmitted to the signal processing circuit through the first inter-board connector.

[0025] The beneficial effects of the present invention and the prior art are:

[0026] (1) The present invention adopts a sandwich architecture design, which is divided according to the main functions. The upper layer is the focal plane circuit, the middle layer is the signal processing circuit, and the bottom layer is the interface power circuit. The three-layer circuit connection adopts a high-speed through-board connector, which has a short signal transmission distance, strong anti-interference ability, high integration, and a small imaging circuit box.

[0027] (2) The imaging circuit architecture of the present invention provides powerful hardware support for software and image processing, realizing miniaturized, commercialized and integrated imaging circuit design.

[0028] (3) The architecture of the present invention is compatible with multi-interface design while meeting the requirements of miniaturization design: including LVDS interface, 2711 interface, CXP interface, CAN interface, RS-422 interface receiving and driving design, meeting the requirements of different data transmission and control interface design.

[0029] (4) The present invention has the ability to process 36 differential signals and 46 single-ended signals of CMOS detectors. This circuit architecture can also be directly put into use by changing the focal plane circuit, signal processing circuit and interface power supply circuit according to the requirements of different types of CMOS detectors, which can meet the design of most small-array CMOS imaging circuits, reduce the design cycle, and improve the maturity of the system. The present invention provides powerful hardware support for software and image processing.

[0030] (5) The circuit architecture of the present invention only needs to change the focal plane circuit according to the requirements of different models and different CMOS detectors. The signal processing circuit and the power supply circuit can be directly put into use, which can meet the design of most small-array CMOS imaging circuits and flexibly use various functional modules. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is a schematic diagram of the connection mode of each functional circuit of the imaging circuit of the present invention;

[0032] Figure 2 This is a schematic diagram of signal transmission of the imaging circuit of the present invention;

[0033] Figure 3 This is a schematic diagram of the power supply network of the imaging circuit of the present invention;

[0034] Figure 4 It is a schematic diagram of the arrangement of the point numbers of the second inter-board connector of the present invention;

[0035] Figure 5 It is a schematic diagram of the arrangement of the point numbers of the first inter-board connector of the present invention;

[0036] Figure 6 The filter circuit diagram of the present invention;

[0037] Figure 7 The figure is a schematic diagram of the structural dimensions of a specific implementation of the imaging focal plane circuit of the present invention. DETAILED DESCRIPTION

[0038] The present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0039] The present invention discloses a miniaturized imaging circuit architecture based on a CMOS detector, comprising: an interface power supply circuit, a signal processing circuit, a focal plane circuit, a first inter-board connector and a second inter-board connector; wherein:

[0040] It adopts a sandwich structure design, with the upper layer being the focal plane circuit, the middle layer being the signal processing circuit, and the bottom layer being the interface power circuit; the interface power circuit provides multiple power signals for the signal processing circuit, and the signal processing circuit provides multiple power signals for the focal plane circuit; the focal plane circuit performs voltage conversion according to the selected CMOS detector power supply type to provide power for the CMOS detector;

[0041] The focal plane circuit and the signal processing circuit are connected through a first inter-board connector, and the CMOS detector data received by the focal plane circuit is transmitted to the signal processing circuit through the first inter-board connector; the signal processing circuit performs image caching and processing, and outputs the processed image data through the 2711 interface and CXP interface of the signal processing circuit, or transmits it to the interface power supply circuit through the second inter-board connector; the interface power supply circuit outputs through different interfaces.

[0042] Preferably, the interface power supply circuit comprises a power supply filter circuit, a multi-channel DC-DC circuit, a first π-type filter network and an LDO circuit; wherein;

[0043] The external power supply passes through the power filter circuit, and then through the DC-DC circuit, the first π-type filter network and the LDO circuit for low-noise voltage conversion, filtering and power-on timing control, and is provided to the signal processing circuit through the inter-board connector with 7 power signals of different voltages.

[0044] Preferably, the power supply filter circuit comprises diodes D1, D2, resistors R1, R2 and a second π-type filter network; wherein the series-connected diodes D1 and D2 are connected in parallel with the series-connected resistors R1 and R2 to form a parallel circuit; the input power supply of the parallel circuit is connected to the external input power supply, and the input ground is connected to the external input ground; the resistors R1 and R2 limit the current of the external input power supply and filter the noise; and the second π-type filter network is connected in parallel with the parallel circuit.

[0045] Preferably, the interface power supply circuit further includes a plurality of CAN bus interface chips, a plurality of RS-422 receiving interface chips, a plurality of RS-422 transmitting interface chips and a plurality of LVDS transmitting interface chips; wherein,

[0046] CAN bus interface chip, with CAN bus communication interface 2-way transceiver function, realizes imaging circuit parameter control reception and telemetry data transmission;

[0047] RS-422 receiving interface chip and RS-422 transmitting interface chip, with RS-422 bus 9-way receiving capability, realize RS-422 second pulse, frame synchronization, parameter control receiving and injection interface receiving communication functions and application demand signal receiving, with RS-422 bus 4-way sending and receiving functions, both sending and receiving functions have redundant backup;

[0048] The LVDS transmission interface chip has two sets of data transmission interfaces, the main and the backup, including clock, gating and data signals.

[0049] Preferably, the signal processing circuit comprises an FPGA chip, a refresh circuit, a Flash memory, a 2711 interface chip, a CXP interface chip, a DDR3 memory chip, a first differential crystal oscillator, a second differential crystal oscillator, a third differential crystal oscillator, a fourth single-ended crystal oscillator and a fifth differential crystal oscillator; wherein,

[0050] FPGA chip, which realizes data information processing, instruction parsing and execution;

[0051] Refresh circuit, refresh and program the FPGA chip;

[0052] Flash memory, for multiple backup storage of programs;

[0053] 2711 interface chip and CXP interface chip for data transmission;

[0054] DDR3 memory chip, used for caching CMOS detector image data, can expand data width or perform ping-pong operation to cache detector image data;

[0055] The first differential crystal oscillator provides the main clock for the FPGA chip;

[0056] The second differential crystal oscillator and the third differential crystal oscillator are used to provide a clock for the DDR3 memory chip;

[0057] The fourth single-ended crystal oscillator provides a working clock for the refresh circuit;

[0058] The fifth differential crystal oscillator provides clock for the high-speed SerDes interface of the FPGA chip.

[0059] Preferably, the focal plane circuit includes a CMOS detector; wherein the CMOS detector receives three power supplies from the signal processing circuit, and completes the power supply of the detector according to the type of the CMOS detector; the CMOS detector receives a register configuration signal from the signal processing circuit through the first inter-board connector, and returns a readout signal, and the output CMOS image data is transmitted to the signal processing circuit through the first inter-board connector.

[0060] Example

[0061] like Figure 1As shown, this embodiment provides a miniaturized imaging circuit architecture based on a CMOS detector, which is divided according to the main functions, including an interface power supply circuit, a signal processing circuit, and a focal plane circuit. A sandwich architecture design is adopted, with the upper layer being the focal plane circuit, the middle layer being the signal processing circuit, and the bottom layer being the interface power supply circuit. The focal plane circuit and the signal processing circuit are connected through a high-reliability inter-board connector to complete the chip power supply and CMOS detector data transmission. The signal processing circuit and the interface power supply circuit are connected through a high-speed inter-board connector to complete the chip power supply and control signal and digital signal data transmission.

[0062] Interface power circuit power supply network such as Figure 3 As shown, an input power supply is received through the input electrical connector and enters the power filter module, such as Figure 6 As shown, diodes D1 and D2 provide overvoltage protection and protection from reverse voltage damage, resistors R1 and R2 limit current and filter noise, and then pass through the π-type filter network to provide clean power to the internal circuit. This clean power is used as the input power of DC-DC_1, DC-DC_2, DC-DC_3, DC-DC_4, LDO_1 and LDO_2, and is efficiently and low-noise voltage converted and output by the filter network through DC-DC and LDO, and is provided to the signal processing circuit through the inter-board connector. A total of 7 high-quality power supplies. DCDC_1 outputs +1V, and when the output voltage of DCDC_1 is higher than 90% of the rated value, the powergood signal output terminal is high, the next level DCDC_2 enable terminal is enabled, and DCDC_2 outputs +1.8V. At the same time, when the output voltage of DCDC_2 is higher than 90% of the rated value, the powergood signal output terminal is high, the next level DCDC_3 enable terminal is enabled, and DCDC_3 outputs +3.3V. DCDC_2 outputs +1.8V as the input power of LDO_3, LDO_5, and LDO_6. LDO_3 outputs +1.5V, and LDO_5 outputs +1V_MGT. At the same time, when the output voltage of LDO_5 is higher than 90% of the rated value, the powergood signal output terminal is high, the next level LDO_6 enable terminal is enabled, and LDO_6 outputs +1.2V_MGT. DCDC_3 outputs +3.3V as the input power of LDO_4, and LDO_4 outputs +2.5V. After that, it is provided to the signal processing circuit through the inter-board connector, with a total of 7 high-quality power supplies. The power supply of the signal processing circuit is as follows Figure 3 As shown in the signal processing circuit section, +1V is the FPGA core power supply, +1V_MGT and +1.2V_MGT are used to power the FPGA high-speed transceiver, +1.5V is generated by the signal processing circuit DDR regulator to +0.75V for DDR3, +3.3V, +2.5V and +1.8V are used to power the FPGA IO power supply and other functional chips. The interface power supply circuit is provided to the focal plane circuit through the middle layer signal processing circuit, a total of 3 high-quality power supplies, such as Figure 3 As shown in the figure, the power supply after the power filter module enters DC-DC_4, LDO_1 and LDO_2 for high-efficiency low-noise voltage conversion and filter network output, LDO_2 outputs +5V, DC-DC_4 outputs -6V. DC-DC_4 outputs -6V as the input power of LDO_1, and LDO_1 outputs -5V. These 3 high-quality power supplies are +5V, -5V and optional +1.8V or +3.3V. Voltage conversion is performed according to the selected CMOS detector power supply type for use by the detector. The above power supplies adopt a multi-point design on the connector to meet the current derating design and improve circuit reliability.

[0063] Interface power circuit such as Figure 2 As shown, it integrates 2 CAN bus interface chips, with 2-way CAN bus communication interface transceiver function, which can realize imaging circuit parameter control reception and telemetry data transmission. It integrates 3 RS-422 receiving interface chips and 3 RS-422 transmitting interface chips, with 9-way RS-422 bus receiving capability, which can realize RS-422 second pulse, frame synchronization, parameter control reception and injection interface receiving communication functions and other control signal receiving application requirements; it has 4-way RS-422 bus transmission capability, which can realize RS-422 telemetry return function, and both transmission and reception can realize master and standby functions. It integrates 2 LVDS transmission interface chips, with two sets of data transmission interfaces, master and standby, which can realize clock, gating and data signal transmission. The data sent or received by the above channels are transmitted to the signal processing circuit through the inter-board connector for data information processing, command parsing and telemetry return.

[0064] Signal processing circuits such as Figure 2 As shown, it integrates a high-speed and high-performance FPGA chip with 203,800 LUTs and 407,600 FFs to realize data information processing and instruction parsing and execution. It integrates an anti-radiation refresh circuit with on-track FPGA refresh and program injection functions. It integrates three 256M-bit parallel NOR Flash memories, which can perform multiple backup storage of programs. It integrates two 2711 interface chips and two CXP interface chips, each with two data channels, for high-speed data transmission. It integrates four 4Gb DDR3 memory chips for high-speed cache processing of CMOS detector image data, which can expand the data bit width or cache detector image data by ping-pong operation. It integrates a 200MHz differential crystal oscillator on the board, two of which provide clocks for DDR3, and one provides a differential clock for FPGA, which is used to drive the phase-locked loop frequency division. The on-board 156.25MHz differential crystal oscillator provides clock for the high-speed serdes interface. The on-board 10MHz single-ended crystal oscillator provides working clock for the refresh circuit. The high-speed connector between the signal processing circuit and the focal plane circuit board has the ability to process 36 differential signals and 46 single-ended signals of the CMOS detector.

[0065] Focal plane circuit Figure 2 As shown, it receives three power supplies from the interface power supply circuit, which are +5V, -5V and optional +1.8V or 3.3V. According to the selected CMOS detector power supply type, LDO or operational amplifier is used for voltage conversion. The focal plane circuit receives the register configuration signal from the signal processing circuit through the inter-board connector and returns the readout signal. The CMOS image data is transmitted to the signal processing circuit through the inter-board high-speed connector for data processing.

[0066] The power and signal layout of the two inter-board connectors is as follows Figure 4 and Figure 5 As shown in the figure, the power and ground of the power supply part adopt a multi-point design to reduce ground loops and ensure that the connector contacts can withstand the expected current load to avoid heating caused by poor contact. The signal line adopts a ground wire surround design to form a shielding effect and reduce interference. The ground wire also provides a low-impedance return path for the signal line to reduce reflection. Differential signals and single-ended signals are laid out separately to reduce crosstalk.

[0067] In the detectors that have been selected for implementation, the maximum data rate of a single channel of image data transmitted through the high-speed board connector of the focal plane circuit and the signal processing circuit is 1200Mbps, and a total of 32 channels are selected. Two DDR3 chips are used to expand the bit width, and then the detector image data is cached through the ping-pong operation for high-speed data caching. The size of the interface power supply circuit and the signal processing circuit is 130mm×130mm, and the size of the circuit box composed of the three circuits is as follows Figure 7 As shown, L1: 138mm, L2: 138mm, L3: 69mm. This imaging circuit architecture provides powerful hardware support for software and image processing, and realizes miniaturization, productization and integration of imaging circuit design.

[0068] The above is only a specific implementation structure of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by any technician familiar with the technical field within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

[0069] Although the content of the present invention has been described in detail through the above preferred embodiments, it should be appreciated that the above description should not be considered as a limitation of the present invention. After reading the above content, it will be apparent to those skilled in the art that various modifications and substitutions of the present invention will occur. Therefore, the protection scope of the present invention should be limited by the appended claims.

[0070] The contents not described in detail in the specification of the present invention belong to the common knowledge of the professionals in this field.

Claims

1. A miniaturized imaging circuit architecture based on a CMOS detector, characterized in that: include: interface power supply circuit, signal processing circuit, focal plane circuit, first inter-board connector and second inter-board connector; wherein, It adopts a sandwich structure design, with the upper layer being the focal plane circuit, the middle layer being the signal processing circuit, and the bottom layer being the interface power circuit; the interface power circuit provides multiple power signals for the signal processing circuit, and the signal processing circuit provides multiple power signals for the focal plane circuit; the focal plane circuit performs voltage conversion according to the selected CMOS detector power supply type to provide power for the CMOS detector; The focal plane circuit and the signal processing circuit are connected through a first inter-board connector, and the CMOS detector data received by the focal plane circuit is transmitted to the signal processing circuit through the first inter-board connector; the signal processing circuit performs image caching and processing, and outputs the processed image data to the outside through the signal processing circuit, or transmits it to the interface power supply circuit through the second inter-board connector; the interface power supply circuit outputs to the outside through different interfaces.

2. The miniaturized imaging circuit architecture based on CMOS detector according to claim 1, characterized in that: The interface power supply circuit includes a power supply filter circuit, a multi-channel DC-DC circuit, a first π-type filter network and an LDO circuit; in; The external power supply passes through the power filter circuit, and then through the DC-DC circuit, the first π-type filter network and the LDO circuit for low-noise voltage conversion, filtering and power-on timing control, and is provided to the signal processing circuit through the inter-board connector with 7 power signals of different voltages.

3. The miniaturized imaging circuit architecture based on CMOS detector according to claim 2, characterized in that: The power supply filter circuit comprises diodes D1, D2, resistors R1, R2 and a second π-type filter network; wherein the diodes D1 and D2 connected in series are connected in parallel with the resistors R1 and R2 connected in series to form a parallel circuit; the input power supply of the parallel circuit is connected to the external input power supply, and the input ground is connected to the external input ground; the resistors R1 and R2 limit the current of the external input power supply and filter the noise; and the second π-type filter network is connected in parallel with the parallel circuit.

4. The miniaturized imaging circuit architecture based on CMOS detector according to claim 1, characterized in that: The interface power supply circuit also includes a plurality of CAN bus interface chips, a plurality of RS-422 receiving interface chips, a plurality of RS-422 transmitting interface chips and a plurality of LVDS transmitting interface chips; wherein, CAN bus interface chip, with 2-way transceiver function of CAN bus communication interface, realizes imaging circuit parameter control reception and telemetry data transmission; RS-422 receiving interface chip and RS-422 transmitting interface chip, with RS-422 bus 9-way receiving capability, realize RS-422 second pulse, frame synchronization, parameter control receiving and injection interface receiving communication functions and application demand signal receiving, with RS-422 bus 4-way sending and receiving functions, both sending and receiving functions have redundant backup; The LVDS transmission interface chip has two sets of data transmission interfaces, the main and the backup, including clock, gating and data signals.

5. The miniaturized imaging circuit architecture based on CMOS detector according to claim 1, characterized in that: The signal processing circuit includes an FPGA chip, a refresh circuit, a Flash memory, a 2711 interface chip, a CXP interface chip, a DDR3 memory chip, a first differential crystal oscillator, a second differential crystal oscillator, a third differential crystal oscillator, a fourth single-ended crystal oscillator and a fifth differential crystal oscillator; wherein, FPGA chip, which realizes data information processing, instruction parsing and execution; Refresh circuit, refresh and program the FPGA chip; Flash memory, for multiple backup storage of programs; 2711 interface chip and CXP interface chip for data transmission; DDR3 memory chip, used for caching CMOS detector image data, can expand data width or perform ping-pong operation to cache detector image data; The first differential crystal oscillator provides the main clock for the FPGA chip; The second differential crystal oscillator and the third differential crystal oscillator are used to provide a clock for the DDR3 memory chip; The fourth single-ended crystal oscillator provides a working clock for the refresh circuit; The fifth differential crystal oscillator provides clock for the high-speed SerDes interface of the FPGA chip.

6. The miniaturized imaging circuit architecture based on CMOS detector according to claim 1, characterized in that: The focal plane circuit includes a CMOS detector; wherein the CMOS detector receives three power supplies from a signal processing circuit, and completes the detector power supply according to the type of the CMOS detector; the CMOS detector receives a register configuration signal from the signal processing circuit through a first inter-board connector, and returns a readout signal, and the output CMOS image data is transmitted to the signal processing circuit through the first inter-board connector.

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