Silicon carbide MOS memory device and preparation method thereof

Abstract

The invention discloses a silicon carbide MOS memory device and a preparation method thereof, and belongs to the field of semiconductor memory devices. Comprising the following steps: a, carrying out organic and inorganic cleaning on a silicon carbide epitaxial wafer; b, depositing a SiO2 film on the SiC epitaxial wafer through chemical reaction, chemical vapor deposition and physical vapor deposition; c, depositing an Al2O3 / AlN / AlON thin film on the SiO2 thin film (or directly on the SiC epitaxial wafer) through atomic layer deposition; d, carrying out argon annealing on the gate medium generated in the above step, and cooling or not annealing; and e, sputtering or evaporating a metal gate electrode and a back electrode on the gate dielectric layer to form an MOS device structure. Positive voltages of different magnitudes are applied to the gate electrode, traps distributed along with energy levels in the gate dielectric layer are filled with electrons, negative voltages are applied to the gate electrode, ultraviolet light is applied at the same time, and electrons in a hole recombination gate dielectric are generated, so that storage and release of charges of a controllable number are achieved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor memory devices, and in particular to a silicon carbide MOS memory device and a preparation method thereof. Background Art

[0002] Traditional charge trapping devices use a silicon-based stacked gate MOS structure, which is a semiconductor-oxide-nitride-metal structure. In this structure, by applying a positive bias to the gate, the electrons emitted from the substrate to the gate are captured by the nitride trap to complete programming, and by applying a negative bias to the gate, the holes tunnel into the nitride and the electrons complete erasure. The above two processes are used to control the amount of charge in the gate dielectric to control the threshold voltage of the transistor, thereby achieving the two states of "0" and "1".

[0003] In the prior art, charge trapping devices are usually silicon-based, but the properties of silicon materials will change seriously at high temperatures. Due to the narrow bandgap of silicon, more electron-hole pairs will be generated at high temperatures, which makes silicon-based storage devices prone to charge leakage at high temperatures, resulting in data loss. As a third-generation semiconductor material, silicon carbide has the characteristics of wide bandgap, high breakdown field strength, high thermal conductivity, high saturated electron drift velocity, etc. It also has stable chemical properties, strong radiation resistance and mechanical strength. These characteristics make silicon carbide have a good application prospect in the field of electronic devices for aerospace applications. Summary of the invention

[0004] The purpose of the present invention is to provide a silicon carbide MOS memory device and a method for preparing the same in view of the above-mentioned problems in the prior art. By introducing electron traps distributed with energy levels into the gate oxide, electrons are filled into the traps when a positive voltage is applied to the gate to complete programming, and negative voltage is applied to the gate, and ultraviolet light is applied at the same time to generate holes that enter the gate oxide and electrons to complete erasure. The more excellent material properties of silicon carbide materials are utilized to prepare a more high-temperature resistant memory device. Effective storage and erasure of charges are achieved, and the excellent properties of silicon carbide materials are utilized to improve the high-temperature resistance and radiation resistance of the memory device.

[0005] In order to achieve the above-mentioned object of the invention, the present invention provides the following technical solutions.

[0006] The present invention provides a silicon carbide MOS storage device comprising an n-type silicon carbide substrate, and a gate dielectric film and a metal gate electrode grown in sequence on the n-type silicon carbide substrate; the gate dielectric film is composed of two or more films, including (1) SiO2 / Al2O3, AlN or AlON; or (2) Al2O3, AlN or AlON, so as to achieve an effective gate control effect and charge storage.

[0007] The n-type silicon carbide substrate is specifically an n-type 4H-SiC substrate; the thickness of the n-type silicon carbide substrate ranges from 100 to 1000 μm, and the doping concentration ranges from 10 17 ~10 19 cm -3 ;

[0008] The thickness of the SiO2 film ranges from 1 to 100 nm.

[0009] The thickness of the Al2O3 / AlN / AlON film ranges from 1 to 100 nm.

[0010] The present invention provides a method for preparing a silicon carbide MOS memory device, comprising the following steps:

[0011] a. Perform organic and inorganic cleaning on silicon carbide epitaxial wafers;

[0012] b. Deposition of Al2O3 / AlN / AlON thin films on SiC epitaxial wafers by atomic layer deposition;

[0013] c. annealing and cooling the gate dielectric generated by the above steps or not annealing;

[0014] d. Sputter or evaporate a metal gate electrode and a back electrode on the gate dielectric layer to form a MOS device structure.

[0015] The present invention provides a second method for preparing a silicon carbide MOS memory device, comprising the following steps:

[0016] a. Perform organic and inorganic cleaning on silicon carbide epitaxial wafers;

[0017] b. Depositing SiO2 thin film on SiC epitaxial wafer by chemical reaction, chemical vapor deposition, and physical vapor deposition;

[0018] c. Deposition of Al2O3 / AlN / AlON thin film on SiO2 thin film by atomic layer deposition;

[0019] d. annealing the gate dielectric generated by the above steps and cooling or not annealing;

[0020] e. Sputtering or evaporating a metal gate electrode and a back electrode on the gate dielectric layer to form a MOS device structure.

[0021] The preferred substrate thickness range is 100~1000 μm, and the doping concentration range is 10 17 ~10 19 cm -3 The thickness of SiC epitaxial wafer ranges from 1 to 100 μm, and the doping concentration ranges from 10 14 ~10 17 cm-3 .

[0022] The thickness of the SiO2 film is preferably in the range of 1 to 100 nm.

[0023] The preferred atomic layer deposition parameters for SiO2 thin films are: pressure of 0.1-0.3 torr, temperature of 100-500°C, carrier gas of Ar or N2, carrier gas flow rate of 50-500 sccm, pulse time of 0.1-5 s, and time interval of 1-180 s.

[0024] The thickness of the Al2O3 / AlN / AlON film is preferably in the range of 1 to 100 nm.

[0025] The preferred parameters for atomic layer deposition of Al2O3 / AlN / AlON thin films are pressure of 0.1~0.3 torr, temperature of 100~500°C, carrier gas of Ar or N2, carrier gas flow of 50~500 sccm, pulse time of 0.1~5 s, and time interval of 1~180 s.

[0026] Preferably, the annealing gas used in the annealing and cooling process is argon gas, and the annealing temperature range is 600-1300°C.

[0027] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0028] 1. By applying the technical solution of the present invention, programming can be completed by filling electrons into the trap when a positive voltage is applied to the gate, and erasing can be completed by applying a negative voltage to the gate and applying ultraviolet light to generate holes that enter the gate oxide and neutralize the electrons, thereby regulating the amount of charge in the gate dielectric.

[0029] 2. By applying the technical solution of the present invention, due to the material properties of silicon carbide such as radiation resistance, high thermal conductivity and wide bandgap, the prepared memory has better temperature stability and better radiation resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 It is a flow chart of the thin film growth and MOS device preparation process of SiO2 and Al2O3 / AlN / AlON stacks and Al2O3 / AlN / AlON two gate dielectric layers.

[0031] Figure 2 Schematic diagram of the preparation process of SiO2 and Al2O3 / AlN / AlON stacks and Al2O3 / AlN / AlON MOS devices.

[0032] Figure 3 CV characteristic hysteresis curve of the device according to the embodiment of the present invention with increasing maximum voltage applied.

[0033] Figure 4 The CV characteristic hysteresis curve after applying reverse bias for 180 s while adding light, and the CV characteristic hysteresis curve after repeatedly applying increasing maximum voltage.

[0034] Figure 5 This is a comparative example of the present invention, and shows CV curves of silicon-based MOS devices at different temperatures.

[0035] Figure 6 This is an embodiment of the present invention, and shows CV curves of a silicon carbide MOS device at different temperatures. DETAILED DESCRIPTION

[0036] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention clearer and more understandable, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments.

[0037] Figure 1 It is a flow chart of the thin film growth and MOS device preparation process of SiO2 and Al2O3 / AlN / AlON stacks and Al2O3 / AlN / AlON two gate dielectric layers. Figure 2 Schematic diagram of the preparation process of SiO2 and Al2O3 / AlN / AlON stacks and Al2O3 / AlN / AlON MOS devices.

[0038] The following reference Figure 1 and Figure 2 In detail, the present invention comprises the following steps:

[0039] (1) Cleaning of silicon carbide epitaxial wafers

[0040] a. Ultrasonic clean with acetone and ethanol at least once, then rinse with deionized water.

[0041] b. Soak the rinsed epitaxial wafer in hydrofluoric acid for at least 1 min.

[0042] c. Place the epitaxial wafer soaked in hydrofluoric acid into liquid No. 3 and boil for at least 20 minutes. Liquid No. 3 is a mixture of concentrated sulfuric acid and hydrogen peroxide, and the volume ratio of concentrated sulfuric acid to hydrogen peroxide is 1:3.

[0043] d. Boil the epitaxial wafers that have been boiled in liquid No. 3 in liquid No. 1 and liquid No. 2 for at least 10 minutes, then rinse with deionized water and blow dry with nitrogen. Liquid No. 1 is a mixture of ammonia, hydrogen peroxide and deionized water, with a volume ratio of 1:2:5. Liquid No. 2 is a mixture of hydrochloric acid, hydrogen peroxide and deionized water, with a volume ratio of 1:2:5.

[0044] (2) A SiO2 film 2 is grown onto the cleaned SiC epitaxial wafer 1 by atomic layer deposition. The thickness of the SiO2 film ranges from 1 to 100 nm, and the process temperature range of the atomic layer deposition SiO2 film is from 100 to 500°C.

[0045] This step may be omitted and the following step (3) may be directly performed, that is, the Al2O3 / AlN / AlON film may be directly deposited on the SiC epitaxial wafer 1 without depositing the SiO2 film.

[0046] (3) Depositing Al2O3 / AlN / AlON thin film on SiO2 thin film 2 (or directly on SiC epitaxial wafer 1) by atomic layer deposition. The thickness of Al2O3 / AlN / AlON thin film ranges from 1 to 100 nm, and the process temperature ranges from 100 to 500°C.

[0047] (4) Annealing the two gate dielectric layers and then cooling them, wherein the annealing gas is Ar and the annealing temperature is 600-1300° C.

[0048] (5) Sputtering or evaporating a metal electrode 4 on the two gate dielectric layers and on the back side of the epitaxial wafer to form a MOS device structure.

[0049] Example 1

[0050] a. Ultrasonic cleaning was performed three times with acetone and ethanol, and then rinsed with deionized water.

[0051] b. Soak the rinsed epitaxial wafer in diluted hydrofluoric acid (volume ratio HF: deionized water = 1:20) for 10 min.

[0052] c. Put the epitaxial wafer soaked in hydrofluoric acid into liquid No. 3 and boil for 20 minutes. Liquid No. 3 is a mixture of concentrated sulfuric acid and hydrogen peroxide, and the volume ratio of concentrated sulfuric acid to hydrogen peroxide is 1:3.

[0053] d. Boil the epitaxial wafers that have been boiled in No. 3 solution in No. 1 solution and No. 2 solution for at least 10 minutes, then rinse with deionized water and blow dry with nitrogen. No. 1 solution is a mixture of ammonia, hydrogen peroxide and deionized water, with a volume ratio of 1:2:5. No. 2 solution is a mixture of hydrochloric acid, hydrogen peroxide and deionized water, with a volume ratio of 1:2:5.

[0054] Then, a SiO2 film was grown on the cleaned SiC epitaxial wafer using the atomic layer deposition method. The thickness of the grown SiO2 film was 5 nm.

[0055] Then, an Al2O3 film is grown on the SiO2 film using the atomic layer deposition method. The thickness of the Al2O3 film is 30 nm.

[0056] Finally, metal electrodes are sputtered or evaporated on the SiO2 / Al2O3 gate dielectric layer and on the back to form a MOS structure.

[0057] Example 2

[0058] a. Ultrasonic cleaning was performed three times with acetone and ethanol, and then rinsed with deionized water.

[0059] b. Soak the rinsed epitaxial wafer in diluted hydrofluoric acid (volume ratio HF: deionized water = 1:20) for 10 min.

[0060] c. Put the epitaxial wafer soaked in hydrofluoric acid into liquid No. 3 and boil for 20 minutes. Liquid No. 3 is a mixture of concentrated sulfuric acid and hydrogen peroxide, and the volume ratio of concentrated sulfuric acid to hydrogen peroxide is 1:3.

[0061] d. Boil the epitaxial wafers that have been boiled in No. 3 solution in No. 1 solution and No. 2 solution in turn for at least 10 minutes, then rinse with deionized water and blow dry with nitrogen. No. 1 solution is a mixture of ammonia water, hydrogen peroxide and deionized water, with a volume ratio of ammonia water, hydrogen peroxide and deionized water of 1:2:5, and No. 2 solution is a mixture of hydrochloric acid, hydrogen peroxide and deionized water, with a volume ratio of hydrochloric acid, hydrogen peroxide and deionized water of 1:2:5.

[0062] Then, an Al2O3 film is grown on the SiO2 film using the atomic layer deposition method. The thickness of the Al2O3 film is 30 nm.

[0063] Finally, metal electrodes are sputtered or evaporated on the SiO2 / Al2O3 gate dielectric layer and on the back to form a MOS structure.

[0064] The present invention performs a capacitance-voltage characteristic test on the silicon carbide MOS memory device of Example 2, the test frequency is 1 MHz, and the AC voltage signal amplitude is 50 mV; the test results are as follows: Figure 3 and 4 As shown; first, the minimum test voltage is fixed at -10 V, and the maximum voltage is increased by 2 V from 8 V to 16 V, and scanned in sequence. Each time the capacitance is measured, it is scanned from the minimum measurement voltage to the maximum voltage, and then from the maximum voltage to the minimum voltage; the results are shown in Figure 3 As shown in the figure, it is observed that the CV hysteresis curve shifts to the right with the maximum test voltage, which indicates that there are electron traps in the gate dielectric. As the maximum test voltage increases, more electrons are trapped and the information is written. Then, a xenon lamp is used to illuminate the device through the optical fiber, and a bias voltage of -10 V is applied and maintained for 180 s. Then a voltage scan from -10 V to 5 V is performed, and then the light source is turned off. The minimum voltage is -10 V and the maximum voltage is increased by 2 V from 8 V to 16 V each time. The measurements are performed in sequence. The results are shown in the figure. Figure 4As shown, it is found that the curve moves back to the initial state after light maintenance, and the previous phenomenon of the hysteresis curve shifting to the right with the increase of the maximum voltage can be repeated; this indicates that the holes enter the gate oxide and neutralize the electrons, completing the erasure of the information.

[0065] Figure 5 For comparison, the CV characteristic curves of silicon-based MOS devices at different temperatures are shown in Figure 2. Figure 6 The CV characteristic curves of silicon carbide substrate at different temperatures are shown in the embodiment; the CV characteristic of silicon is not stable at high temperature, while the present invention uses wide bandgap semiconductor n-type silicon carbide as the substrate. At high temperature, holes are still difficult to be excited, and the CV characteristic remains unchanged, which greatly increases the high temperature stability of the device.

[0066] Example 3

[0067] Similar to Example 1, the difference is that: on the cleaned silicon carbide epitaxial wafer, a layer of SiO2 film with a thickness of 50nm is deposited by atomic layer deposition technology; the deposition temperature is 300°C to ensure the quality and uniformity of the film; on the SiO2 film, a layer of Al2O3 film with a thickness of 20nm is deposited by atomic layer deposition technology; the deposition temperature is 200°C to maintain the density and stability of the film; the deposited SiO2 and Al2O3 gate dielectric layers are annealed, the annealing gas is Ar, and the annealing temperature is 900°C; after annealing, it is naturally cooled to room temperature; metal electrodes are sputtered on the gate dielectric layer and on the back of the silicon carbide epitaxial wafer to form a MOS device structure.

[0068] Example 4

[0069] Similar to Example 2, the difference is: on the cleaned silicon carbide epitaxial wafer, a layer of Al2O3 film with a thickness of 75nm is deposited by atomic layer deposition technology; the deposition temperature is 400°C to obtain good film quality and performance; the deposited Al2O3 gate dielectric layer is annealed, the annealing gas is Ar, and the annealing temperature is 1100°C; after annealing, it is naturally cooled to room temperature; metal electrodes are sputtered on the gate dielectric layer and on the back of the silicon carbide epitaxial wafer to form a MOS device structure.

[0070] Example 5

[0071] The cleaning process is the same as that of Example 1. The difference is that: on the cleaned silicon carbide epitaxial wafer, a layer of SiO2 film with a thickness of 25nm is deposited by atomic layer deposition technology; the deposition temperature is 250°C; on the SiO2 film, a layer of AlN film with a thickness of 50nm is deposited by atomic layer deposition technology; the deposition temperature is 350°C; the deposited SiO2 and AlN gate dielectric layers are annealed, the annealing gas is Ar, and the annealing temperature is 800°C; after annealing, they are naturally cooled to room temperature; metal electrodes are sputtered on the gate dielectric layer and on the back of the silicon carbide epitaxial wafer to form a MOS device structure.

[0072] Example 6

[0073] The cleaning process is the same as that of Example 1. The difference is that: instead of depositing SiO2 film, AlON film is directly deposited; on the cleaned silicon carbide epitaxial wafer, a layer of AlON film with a thickness of 60nm is deposited by atomic layer deposition technology; the deposition temperature is 450°C; the deposited AlON gate dielectric layer is annealed, the annealing gas is Ar, and the annealing temperature is 1000°C; after annealing, it is naturally cooled to room temperature; metal electrodes are sputtered on the gate dielectric layer and on the back of the silicon carbide epitaxial wafer to form a MOS device structure.

[0074] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for preparing a silicon carbide MOS memory device, characterized in that: The following steps are involved: a. Perform organic and inorganic cleaning on silicon carbide epitaxial wafers; b. Deposition of Al2O3 / AlN / AlON thin films on SiC epitaxial wafers by atomic layer deposition; c. annealing and cooling the Al2O3 / AlN / AlON gate dielectric layer generated by step b, or not annealing; d. sputtering or evaporating metal on the Al2O3 / AlN / AlON gate dielectric layer to prepare a gate electrode to form a MOS device structure.

2. A method for preparing a silicon carbide MOS memory device as claimed in claim 1, characterized in that: In step a, the substrate thickness of the silicon carbide epitaxial wafer used is in the range of 100-1000 μm, and the doping concentration is in the range of 10 17 ~10 19 cm -3 The thickness of the silicon carbide epitaxial wafer is 1~100 μm, and the doping concentration ranges from 10 14 ~10 17 cm -3 .

3. A method for preparing a silicon carbide MOS memory device as claimed in claim 1, characterized in that: In step b, the thickness of the generated Al2O3 / AlN / AlON film is 1~100 nm; the parameters of atomic layer deposition are: pressure is 0.1~0.3torr, temperature is 100~500℃, carrier gas is Ar or N2, carrier gas flow rate is 50~500 sccm, pulse time is 0.1~5 s, and time interval is 1~180 s.

4. A method for preparing a silicon carbide MOS memory device as claimed in claim 1, characterized in that: In step c, the annealing gas is argon, and the annealing temperature ranges from 600 to 1300°C.

5. A method for preparing a silicon carbide MOS memory device, characterized in that: The following steps are involved: a. Perform organic and inorganic cleaning on silicon carbide epitaxial wafers; b. Depositing SiO2 thin film on SiC epitaxial wafer by chemical reaction, chemical vapor deposition, and physical vapor deposition; c. depositing an Al2O3 / AlN / AlON film on the SiO2 film by atomic layer deposition; d. annealing and cooling the SiO2 and Al2O3 / AlN / AlON stacked gate dielectric layers generated by step c, or not annealing; e. sputtering or evaporating a metal gate electrode and a back electrode on the Al2O3 / AlN / AlON gate dielectric layer to form a MOS device structure.

6. A method for preparing a silicon carbide MOS memory device as claimed in claim 5, characterized in that: In step a, the substrate thickness of the silicon carbide epitaxial wafer used is in the range of 100-1000 μm, and the doping concentration is in the range of 10 17 ~10 19 cm -3 The thickness of the silicon carbide epitaxial wafer is 1~100 μm, and the doping concentration ranges from 10 14 ~10 17 cm -3 .

7. A method for preparing a silicon carbide MOS memory device as claimed in claim 5, characterized in that: In step b, the thickness of the generated SiO2 film is 1~100 nm; the process temperature range of the vapor-deposited SiO2 film is 100~1000°C.

8. A method for preparing a silicon carbide MOS memory device as claimed in claim 5, characterized in that: In step c, the thickness of the generated Al2O3 / AlN / AlON film is 1~100 nm; the parameters of atomic layer deposition are: pressure is 0.1~0.3 torr, temperature is 100~400℃, carrier gas is Ar or N2, carrier gas flow rate is 50~500 sccm, pulse time is 0.1~5 s, and time interval is 1~180 s.

9. A method for preparing a silicon carbide MOS memory device as claimed in claim 5, characterized in that: In step d, the annealing gas used is argon, and the annealing temperature ranges from 600 to 1300°C.

10. A silicon carbide MOS memory device prepared by the preparation method according to any one of claims 1 to 9.

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