High-voltage isolating ring structure

Abstract

The invention provides a high-voltage isolating ring structure. A high-voltage isolating ring is composed of high-voltage diodes and is isolated between a high-voltage circuit and a low-voltage circuit. A first conductive type doped epitaxial layer is formed on the semiconductor substrate; a doped region of a second conductive type is formed on the epitaxial layer; the first conductive type heavily doped anode is connected with a high level; a heavily doped body contact region of the second conductive type, wherein the body contact region is connected with a low level; at least one pair of first conductive type heavily-doped first active region and second conductive type heavily-doped second active region, the first active region and the second active region are alternately formed in a selected region of the first well region to form a parasitic triode structure, and the first active region and the second active region are both connected to a low level; the gate structure is connected with low level. According to the invention, the triode structure is inserted into the high-voltage diode, so that the electrostatic current discharging capability of the isolating ring can be improved, and the occupied chip area is kept unchanged.

Description

Technical Field

[0001] The invention relates to the field of semiconductor technology, and in particular to a high-voltage isolation ring structure. Background Art

[0002] A typical bilateral high-voltage gate drive circuit (HVIC) consists of a high-side power tube, a low-side power tube, and a control circuit placed in a high-voltage floating basin. The high-voltage floating basin is surrounded by a circle of high-voltage isolation rings to provide high withstand voltage (maximum greater than 200V). Due to the withstand voltage requirements, it usually occupies a very large chip area. Because the operating voltage is too high and the size of the high-voltage isolation ring is large, a self-protection method is generally used to discharge the ESD current. With the development of application scenarios, the demand for ESD performance has gradually increased from HBM (human body model) 2KV to 4KV. This puts higher requirements on the design of the high-voltage isolation ring.

[0003] The plane layout of the prior art high voltage isolation ring is as follows: Figure 1 As shown in FIG. 1 , the high-voltage isolation ring is a closed ring, which is composed of an inner high-voltage floating basin, an outer high-voltage isolation ring, a level-shift (level shift device) area, and a P-type shielding ring that isolates the high-voltage isolation ring and the level-shift. The cross-sectional structure AA' of the traditional high-voltage isolation ring is shown in FIG. Figure 2 As shown, from right to left are the high-voltage floating basin area and the high-voltage isolation ring structure. The high-voltage floating basin area is formed by implanting the NBL area on the substrate Psub, and then growing the N-type epitaxy. The epitaxy surface forms an N+ active area. The high-voltage isolation ring structure is similar to the LDMOS structure. The N-type epitaxy is grown on the Psub substrate. From right to left, the N-type active area, the drift area field oxygen, the polysilicon field plate close to the N-type active area, the gate polysilicon, and the P-type active area are formed. A P-type well and PBL are formed under the P-type active area, which is connected to the substrate Psub. The high-voltage floating basin N-type active area, the high-voltage isolation ring N-type active area and the gate polysilicon field plate are connected together to a high potential, and the gate polysilicon and the P-type active area are connected and grounded to achieve a high withstand voltage function. Two level-shift devices are formed on one side of the high-voltage isolation ring, and the level-shift device and the high-voltage isolation ring are isolated by a P-type shielding ring.

[0004] The existing technical structure uses a diode with a large area to meet the HBM requirement. However, the BV (breakdown voltage) distribution on the isolation ring is uneven, and the junction between the isolation ring and the level-shift area is a weak point of BV, which limits the ability to discharge electrostatic current and can only pass HBM 2KV.

[0005] In order to solve the above problems, it is necessary to propose a new type of high-voltage isolation ring structure. Summary of the invention

[0006] In view of the shortcomings of the prior art mentioned above, the purpose of the present invention is to provide a high-voltage isolation ring structure to solve the problem that in the prior art, a diode with a larger area is used to meet the HBM requirements, but the BV (breakdown voltage) distribution on the isolation ring is uneven, and the junction between the isolation ring and the level shift device area is a weak point of breakdown voltage, which limits the ability to discharge electrostatic current.

[0007] To achieve the above objectives and other related objectives, the present invention provides a high voltage isolation ring structure, comprising:

[0008] The high-voltage isolation ring is composed of a high-voltage diode with a similar LDMOS structure and is isolated between the high-voltage circuit and the low-voltage circuit. The working voltage of the high-voltage circuit is greater than the working voltage of the low-voltage circuit, and the working voltage of the high-voltage diode is also greater than the working voltage of the low-voltage circuit.

[0009] forming an epitaxial layer doped with a first conductivity type on a semiconductor substrate;

[0010] A doped region of the second conductivity type is formed on the epitaxial layer, and the doped region and the epitaxial layer doped with the first conductivity type between the epitaxial layer and the high-voltage circuit constitute a diode part;

[0011] The high voltage diode further comprises:

[0012] A heavily doped anode of the first conductivity type is formed in the surface area of ​​the epitaxial layer, the anode is close to one side of the high voltage circuit, and the anode is connected to a high level;

[0013] A second conductive type heavily doped body contact region formed in a selected area of ​​the doped region, the body contact region being connected to a low level;

[0014] At least one pair of a first active region heavily doped with a first conductivity type and a second active region heavily doped with a second conductivity type, wherein the first and second active regions are alternately formed in selected areas of the first well region to form a parasitic triode structure, and the first and second active regions are both connected to a low level;

[0015] The gate structure covers the surface of the doped region and one side of the gate structure extends onto the epitaxial layer. The gate structure is connected to a low level.

[0016] Preferably, the high voltage circuit is located inside the high voltage isolation ring.

[0017] Preferably, in a top view, the high-voltage isolation ring is in a quadrilateral ring structure.

[0018] Preferably, the high-voltage diodes in a partial area constitute a level shift device.

[0019] Preferably, there are two level shift devices located on the same side.

[0020] Preferably, the high-voltage isolation ring structure is used for the other three sides except the level shift device.

[0021] Preferably, a shielding ring of the second conductivity type is provided around the level shift device to achieve isolation between the level converter and the high-voltage diode and devices of the high-voltage circuit outside the level converter.

[0022] Preferably, the second conductive type doped region includes: a first buried layer, a first doped layer and a first well region doped with the second conductive type stacked in sequence, the first doped layer realizing the connection between the first well region and the first buried layer; the first buried layer is formed in a selected region between the semiconductor substrate and the epitaxial layer; the first doped layer and the first well region are both formed in the epitaxial layer, and the body contact region heavily doped with the second conductive type is formed in a selected region of the first well region.

[0023] Preferably, the drift region similar to the LDMOS structure is composed of the epitaxial layer located between the first well region and the anode; a drift region field oxygen is formed on the surface of the drift region; a gate structure covers the surface of the doped region and one side of the gate structure extends to the drift region field oxygen, and the gate structure is connected to a low level.

[0024] Preferably, the gate structure is formed by stacking a gate dielectric layer and a polysilicon gate.

[0025] Preferably, the gate dielectric layer is a gate oxide layer or a metal silicide.

[0026] Preferably, the top of the first well region is covered with a field oxide layer.

[0027] Preferably, the first conductivity type is N type, and the second conductivity type is P type.

[0028] Preferably, the edges of the first and second active regions are in contact with each other, and the first and second active regions are short-circuited via contact holes and a front metal layer.

[0029] Preferably, there is a non-doped active region between the first and second active regions, and the first and second active regions are short-circuited via contact holes and a front metal layer.

[0030] Preferably, there is a non-doped active region between the first and second active regions, the non-doped active region is covered with a self-aligned silicide barrier layer, and the first and second active regions are short-circuited through contact holes and a front metal layer.

[0031] Preferably, the material of the salicide blocking layer includes at least one of silicon-rich oxide, SiO2, SiON and Si3N4.

[0032] Preferably, there is a non-doped active region between the first and second active regions, the non-doped active region is covered with a polysilicon layer, and the first and second active regions are short-circuited through contact holes and a front metal layer.

[0033] Preferably, the operating voltage of the high-voltage diode is not less than 150V.

[0034] As described above, the high-voltage isolation ring structure of the present invention has the following beneficial effects:

[0035] The present invention can improve the electrostatic current discharge capability of the isolation ring, while the chip area occupied by the isolation ring remains unchanged. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 Shown is a schematic diagram of a high voltage isolation ring structure of the prior art;

[0037] Figure 2 Display as Figure 1 Schematic diagram of the cross-sectional structure at A-A';

[0038] Figure 3 It is a schematic diagram showing the cross-sectional structure of a high-voltage isolation ring according to a first embodiment of the present invention;

[0039] Figure 4 Shown is a schematic diagram of forming a parasitic BJT structure of the present invention;

[0040] Figure 5 It is a schematic diagram of the cross-sectional structure of a high-voltage isolation ring according to a second embodiment of the present invention;

[0041] Figure 6 It is a schematic diagram of the cross-sectional structure of a high-voltage isolation ring according to a third embodiment of the present invention;

[0042] Figure 7 It is a schematic cross-sectional structure diagram of a high-voltage isolation ring according to a fourth embodiment of the present invention. DETAILED DESCRIPTION

[0043] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0044] The present invention provides a high-voltage isolation ring structure, comprising:

[0045] The high-voltage isolation ring is composed of a high-voltage diode and is isolated between the high-voltage circuit and the low-voltage circuit. The working voltage of the high-voltage circuit is greater than the working voltage of the low-voltage circuit, and the working voltage of the high-voltage diode is also greater than the working voltage of the low-voltage circuit. In an embodiment of the present invention, the working voltage of the high-voltage diode is not less than 150V.

[0046] In some embodiments, the high voltage circuit is located inside the high voltage isolation ring.

[0047] In some embodiments, in a top view, the high-voltage isolation ring is in a quadrilateral ring structure.

[0048] An epitaxial layer 102 doped with a first conductivity type is formed on a semiconductor substrate 101;

[0049] A doped region of the second conductivity type is formed on the epitaxial layer 102, and the doped region and the epitaxial layer 102 doped with the first conductivity type between the high-voltage circuit form a diode part;

[0050] For example, the second conductive type doped region includes a first buried layer 103, a first doped layer 104 and a first well region 105 doped with the second conductive type and stacked in sequence, and the first doped layer 104 realizes the connection between the first well region 105 and the first buried layer 103;

[0051] The first buried layer 103 is formed in a selected region between the semiconductor substrate 101 and the epitaxial layer 102;

[0052] The first doped layer 104 and the first well region 105 are both formed in the epitaxial layer 102;

[0053] In some embodiments, high voltage diodes in a portion of the region form a level shift device.

[0054] In some embodiments, the number of the level shifting devices is two and they are located on the same side.

[0055] In some embodiments, a high voltage isolation ring structure is used for the other three sides except the level shift device.

[0056] In some embodiments, a shielding ring of the second conductivity type is provided around the level shift device to achieve isolation between the level converter and the high-voltage diode and devices of the high-voltage circuit outside the level converter.

[0057] High voltage diodes also include:

[0058] A heavily doped anode 112 of the first conductivity type is formed in the surface area of ​​the epitaxial layer 102, the anode 112 is close to one side of the high voltage circuit, and the anode 112 is connected to a high level;

[0059] The drift region similar to the LDMOS structure is composed of an epitaxial layer 102 located between the first well region 105 and the anode 112; a drift region field oxygen is formed on the surface of the drift region; the gate structure covers the surface of the doped region and one side of the gate structure extends to the drift region field oxygen, and the gate structure is connected to a low level.

[0060] A second conductive type heavily doped body contact region 110 is formed in a selected region of the doped region, for example, in a selected region of the first well region 105 , and the body contact region 110 is connected to a low level;

[0061] At least one pair of a first active region 114 heavily doped with a first conductivity type and a second active region 113 heavily doped with a second conductivity type, the first and second active regions are alternately formed in a selected area of ​​the first well region 105 to form a parasitic triode structure, and the first and second active regions are both connected to a low level;

[0062] The drift region is composed of an epitaxial layer 102 located between the first well region 105 and the anode 112;

[0063] A drift region field oxide 106 is formed on the surface of the drift region of the high voltage diode;

[0064] The gate structure covers the surface of the doped region and one side of the gate structure extends onto the epitaxial layer 102 . The gate structure is connected to a low level.

[0065] In some embodiments, the gate structure covers the surface of the first well region 105 and the second side surface of the gate structure extends to the field oxide of the drift region, and the gate structure is connected to a low level.

[0066] In some embodiments, the gate structure is formed by stacking a gate dielectric layer 108 and a polysilicon gate 109 .

[0067] In some embodiments, the gate dielectric layer 108 is a gate oxide layer or a metal silicide.

[0068] In some embodiments, the top of the first well region 105 is covered with a field oxide layer 107 , which is used to isolate the first and second active regions from the body contact region 110 , and to isolate the body contact region 110 from other devices.

[0069] In an embodiment of the present invention, the first conductivity type is N type, and the second conductivity type is P type.

[0070] In some embodiments, see Figure 3 The edges of the first and second active regions are in contact with each other, and the first and second active regions are short-circuited through contact holes and the front metal layer. In the layout, the second active region 113 can be inserted into the first active region 114 of the source end in a flower-insertion manner to achieve short-circuiting. Figure 4The first and second active regions are short-circuited by butting, thus forming a parasitic BJT structure. Since the BJT structure has a higher current amplification factor than the diode, the current capability of the new structure is greatly improved compared with the traditional structure. The HBM capability of the isolation ring is increased from 2KV to 4KV, and the chip area it occupies remains unchanged.

[0071] In some embodiments, see Figure 5 There is a non-doped active region 115 between the first and second active regions, and the first and second active regions are short-circuited through contact holes and a front metal layer.

[0072] In some embodiments, see Figure 6 There is a non-doped active region 115 between the first and second active regions, and a self-aligned silicide barrier layer 116 is covered on the non-doped active region 115. The first and second active regions are short-circuited through contact holes and a front metal layer. Covering the self-aligned silicide barrier layer 116 on the non-doped active region 115 can improve the latch-up effect (Latch up refers to a low impedance path generated between the power supply VDD and the ground line GND (VSS) in the CMOS chip due to the mutual influence of the parasitic PNP and NPN bipolar BJT) immunity.

[0073] In some embodiments, the material of the salicide blocking layer 116 includes at least one of silicon-rich oxide, SiO 2 , SiON, and Si 3 N 4 .

[0074] In some embodiments, see Figure 7 There is a non-doped active region 115 between the first and second active regions, and the non-doped active region 115 is covered with a polysilicon layer 117. The first and second active regions are short-circuited through contact holes and a front metal layer. Covering the non-doped active region 115 with a polysilicon layer 117 can improve the latch-up immunity.

[0075] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0076] In summary, the present invention can improve the electrostatic current discharge capability of the isolation ring, and the chip area occupied by the isolation ring remains unchanged. Therefore, the present invention effectively overcomes various shortcomings of the prior art and has high industrial utilization value.

[0077] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A high voltage isolation ring structure, characterized in that: include: The high-voltage isolation ring is composed of a high-voltage diode with a similar LDMOS structure and is isolated between the high-voltage circuit and the low-voltage circuit. The working voltage of the high-voltage circuit is greater than the working voltage of the low-voltage circuit, and the working voltage of the high-voltage diode is also greater than the working voltage of the low-voltage circuit. forming an epitaxial layer doped with a first conductivity type on a semiconductor substrate; A doped region of the second conductivity type is formed on the epitaxial layer, and the doped region and the epitaxial layer doped with the first conductivity type between the epitaxial layer and the high-voltage circuit constitute a diode part; The high voltage diode further comprises: A heavily doped anode of the first conductivity type is formed in the surface area of ​​the epitaxial layer, the anode is close to one side of the high voltage circuit, and the anode is connected to a high level; A second conductive type heavily doped body contact region formed in a selected area of ​​the doped region, the body contact region being connected to a low level; At least one pair of a first active region heavily doped with a first conductivity type and a second active region heavily doped with a second conductivity type, wherein the first and second active regions are alternately formed in selected areas of the first well region to form a parasitic triode structure, and the first and second active regions are both connected to a low level; The gate structure covers the surface of the doped region and one side of the gate structure extends onto the epitaxial layer. The gate structure is connected to a low level.

2. The high voltage isolation ring structure according to claim 1, characterized in that: The high voltage circuit is located inside the high voltage isolation ring.

3. The high voltage isolation ring structure according to claim 1, characterized in that: In a top view, the high-voltage isolation ring is in a quadrilateral ring structure.

4. The high voltage isolation ring structure according to claim 1, characterized in that: The high voltage diodes in some areas constitute level shift devices.

5. The high voltage isolation ring structure according to claim 4, characterized in that: The number of the level shifting devices is two and they are located on the same side.

6. The high voltage isolation ring structure according to claim 5, characterized in that: The high-voltage isolation ring structure is used for the other three sides except the level shift device.

7. The high voltage isolation ring structure according to claim 4, characterized in that: A shielding ring of the second conductivity type is arranged on the peripheral side of the level shift device to achieve isolation between the level converter and the high-voltage diode and the components of the high-voltage circuit outside the level converter.

8. The high voltage isolation ring structure according to claim 1, characterized in that: The second conductive type doped region includes: a first buried layer, a first doped layer and a first well region doped with the second conductive type stacked in sequence, the first doped layer realizing the connection between the first well region and the first buried layer; the first buried layer is formed in a selected region between the semiconductor substrate and the epitaxial layer; the first doped layer and the first well region are both formed in the epitaxial layer; and the body contact region heavily doped with the second conductive type is formed in a selected region of the first well region.

9. The high voltage isolation ring structure according to claim 1, characterized in that: The drift region similar to the LDMOS structure is composed of the epitaxial layer located between the first well region and the anode; a drift region field oxygen is formed on the surface of the drift region; The gate structure covers the surface of the doped region and one side of the gate structure extends to the field oxygen of the drift region, and the gate structure is connected to a low level.

10. The high voltage isolation ring structure according to claim 1, characterized in that: The gate structure is formed by stacking a gate dielectric layer and a polysilicon gate.

11. The high voltage isolation ring structure according to claim 1, characterized in that: The gate dielectric layer is a gate oxide layer or a metal silicide.

12. The high voltage isolation ring structure according to claim 8, characterized in that: The top of the first well region is covered with a field oxide layer.

13. The high voltage isolation ring structure according to claim 1, characterized in that: The first conductivity type is N type, and the second conductivity type is P type.

14. The high voltage isolation ring structure according to claim 1, characterized in that: The edges of the first and second active regions are in contact with each other, and the first and second active regions are short-circuited through contact holes and a front metal layer.

15. The high voltage isolation ring structure according to claim 1, characterized in that: There is a non-doped active region between the first and second active regions, and the first and second active regions are short-circuited through contact holes and a front metal layer.

16. The high voltage isolation ring structure according to claim 1, characterized in that: There is a non-doped active region between the first and second active regions, the non-doped active region is covered with a self-aligned silicide barrier layer, and the first and second active regions are short-circuited through contact holes and a front metal layer.

17. The high voltage isolation ring structure according to claim 16, characterized in that: The material of the salicide blocking layer includes at least one of silicon-rich oxide, SiO2, SiON and Si3N4.

18. The high voltage isolation ring structure according to claim 1, characterized in that: There is a non-doped active region between the first and second active regions. The non-doped active region is covered with a polysilicon layer. The first and second active regions are short-circuited through contact holes and a front metal layer.

19. The high voltage isolation ring structure according to claim 1, characterized in that: The operating voltage of the high voltage diode is not less than 150V.

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