Method for providing wafer

Abstract

A method comprising: providing an electrically insulating wafer comprising a first surface and a second surface for treatment; and providing a layer on the first surface. The layer is non-metallic, electrically conductive, and is configured to electrostatically clamp to an electrostatic chuck.

Description

Background Art

[0001] An electrostatic chuck is used to support a wafer during the fabrication of a circuit on the wafer. It would be desirable to improve this technique for fabricating photonic integrated circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Figure 1 is a flow chart of a method according to an example;

[0003] Figure 2A , Figure 2C , Figure 2E , Figure 2G , Figure 2H and Fig.2I schematically illustrates a side cross section of a structure during a method according to an example;

[0004] Figure 2B Schematically show Figure 2A A top plan view of the structure;

[0005] Figure 2D and Figure 2F Schematically show Figure 2E and Figure 2G a bottom plan view of the structure;

[0006] Figures 3 to 4B schematically illustrating a side cross-section of various structures during a method of a further example;

[0007] Figure 5 A bottom plan view of a structure during a method of a further example is schematically shown. DETAILED DESCRIPTION

[0008] In an example to be described, a method includes providing an electrically insulating wafer. A layer is provided on a first surface (e.g., a lower side) of the wafer. The layer is non-metallic, electrically conductive, and is used for electrostatic clamping to an electrostatic chuck. A second surface (e.g., an upper side) of the wafer is used for processing, such as for manufacturing a circuit such as a photonic integrated circuit (PIC). Examples herein also relate to methods of manufacturing a device, a structure obtained by a method described herein, and a device obtained by a method described herein.

[0009] Electrostatically clamping a wafer to an electrostatic chuck is used to reduce or prevent displacement (e.g., rotation) of the wafer during processing of a surface of the wafer (e.g., for fabricating a circuit). This electrostatic clamping may cause less damage to the wafer than other clamping methods. However, electrostatic clamping may still damage the wafer and / or a circuit being fabricated. It has been found that this damage may be due to the interaction between the electric field applied for electrostatic clamping and the processing of the wafer (e.g., dry etching or plasma etching for fabricating a circuit). This damage may be referred to as electrostatic damage. For example, it has been found that electrostatic clamping combined with plasma etching electrostatically damages and / or deforms the wafer.

[0010] It has been recognized that the use of a non-metallic conductive layer on the first surface of the wafer reduces or even prevents electrostatic damage, as will be described in more detail in the examples below. By reducing this electrostatic damage, the performance, reliability and / or reproducibility of a circuit manufactured on the wafer can be improved. It has also been recognized that the use of a non-metallic layer on the first surface of the wafer reduces or even prevents contamination of a manufactured circuit and / or wafer, for example, during etching during circuit manufacturing. This is in contrast to the use of a metallic layer that is susceptible to etching during processing of the second surface. In addition, depending on a particular etchant used during processing of the second surface, the material of this layer can reduce or avoid the need to replace the layer on the first surface, which would otherwise require unclamping and re-clamping the wafer and interrupting manufacturing. Reducing or avoiding the need to replace the layer can reduce the time required for circuit manufacturing, thereby reducing the cost of circuit manufacturing.

[0011] Before describing the examples in more detail, it is useful to detail the meaning of several terms used herein. Further details of various terms used herein are explained at the end of the description.

[0012] Electrostatic clamping of a wafer is achieved by applying an electric field to an electrostatic chuck and bonding the wafer and the electrostatic chuck together to clamp the wafer to the electrostatic chuck. The electric field causes a portion of the wafer and a portion of the electrostatic chuck to become oppositely charged and electrostatically attracted, thereby clamping the wafer to the electrostatic chuck. A clamping force between the wafer and the chuck increases as the voltage between the chuck and the wafer increases.

[0013] A metal layer referred to herein is a layer comprising a metal material. A metal layer as a layer on the first surface of the wafer is beyond the scope of the examples described herein. A metal material is considered to be a material formed by metallic bonds between particles of the material. A metallic bond is an electrostatic attraction between delocalized conduction electrons and positively charged ions of a metal element. In contrast, a non-metallic material is any material that is not a metal material. Therefore, a non-metallic layer has the properties of the non-metallic material from which it is formed. More specifically, a non-metallic material of the layer on the first surface is a non-metallic conductive material, such as a non-metallic conductive material comprising at least one metal element. For example, the layer comprises iron-doped indium phosphide (Fe-InP).

[0014] Reference Figures 1 to 2I A general description of the examples herein is given. Figure 1 is a flow chart of a method 100 according to an example. Figure 2A , Figure 2C , Figure 2E , Figure 2G , Figure 2H and Fig.2I A schematic cross section through a structure during a method according to an example is shown. Figure 2B exhibit Figure 2A A top plan view of the structure. Figure 2D and Figure 2F Display separately Figure 2E and Figure 2G The method 100 includes providing 101 an electrically insulating wafer 202 having a first surface 204 and a second surface 206. The second surface 206 is used for processing, for example, for manufacturing a circuit. The method 100 then includes providing 103 a layer 208 on the first surface 204, see Figure 2C Layer 208 is non-metallic and conductive, and is used for electrostatic clamping to an electrostatic chuck. Figure 2C Also shown is a structure 250 obtained by providing 103 a layer 208 on the first surface 204 .

[0015] The method 100 then includes electrostatically clamping 105 the layer 208 to an electrostatic chuck 210, see Figure 2D and Figure 2E A surface 212 of layer 208 is in contact with electrostatic chuck 210 and is electrostatically clamped to electrostatic chuck 210. In other examples not shown, when the layer is electrostatically clamped to the electrostatic chuck, the layer and / or a surface of the layer is not in contact with the electrostatic chuck. Figure 2D and Figure 2E2, layer 208 is interposed between surface 212 of layer 208 and electrically insulating wafer 202. Electrostatic chuck 210 is electrostatically clamped to layer 208 by applying a voltage to at least one of electrostatic chuck 210 or layer 208 and bonding layer 208 and electrostatic chuck 210 together. Several different electrical configurations for electrostatic clamping are contemplated, as will be described subsequently. Before and after electrostatically clamping layer 208 to electrostatic chuck 210, first surface 204 and second surface 206 are flat. In other examples not shown, before electrostatically clamping the layer to the electrostatic chuck, the first surface and the second surface are flat, and after electrostatically clamping the layer to the electrostatic chuck, at least one of the first surface or the second surface is not flat. The first surface 204 and the second surface 206 being flat can increase the performance of a circuit fabricated on second surface 206, the repeatability of fabricating a circuit on second surface 206, and / or the reliability of a circuit on second surface 206. Figure 2D and Figure 2E Also shown is a structure 252 obtained by electrostatically clamping layer 208 105 to electrostatic chuck 210 .

[0016] The method 100 then includes fabricating 107 a circuit 214 on the second surface 206 of the electrically insulating wafer 202, see Figure 2F and Figure 2G When fabricating circuit 214, layer 208 is electrostatically clamped to electrostatic chuck 210. In other examples not shown, the layer is removed from the electrostatic chuck for at least partial fabrication of the circuit. Fabrication of the circuit will be described in detail later. Figure 2F and 2G Also shown is a structure 254 obtained by manufacturing 107 a circuit 214 on the second surface 206 .

[0017] Method 100 then includes removing 109 electrostatic chuck 210 from layer 208, see Figure 2H The layer 208 is located on the first surface 204 of the wafer 202. In other examples not shown, removing the electrostatic chuck from the layer also includes at least partially removing the layer from the wafer. Further details of removing the electrostatic chuck will be provided later. Figure 2H Also shown is a structure 256 obtained by removing 109 the electrostatic chuck 210 from the layer 208 .

[0018] The method 100 then includes removing the layer 111 208 (from the electrically insulating wafer 202) Figure 2H or Figure 2F and Figure 2G Transition to Fig.2I In various examples, the method includes at least partially removing the layer 208 from the electrically insulating wafer 202 . Fig.2IA layer 208 is shown separated from the first surface 204 of the electrically insulating wafer 202. In examples not shown, the layer is damaged, physically altered, or chemically altered such that the layer is at least partially removed. Removing the layer from the wafer and / or at least partially removing the layer from the wafer may include at least one of etching, polishing, or grinding of the layer. Other techniques for removing or at least partially removing the layer are contemplated. Fig.2I Also shown is an example structure 258 obtained by removing the 111 layer 208 from the wafer 202 .

[0019] Reference Figure 3 A description of further examples is given. Figure 3 Schematically illustrates a side cross-section of a structure during a method of a further example. Layer 308 is located on first surface 304 of electrically insulating wafer 302. Figure 3 A related feature corresponds to the use of FIG. 2A to FIG. 2I In the case of describing a feature, the use of FIG. 2A to FIG. 2I The corresponding element symbol is 100 larger than the element symbol (for example, Figure 2C 202 in the Figure 3 302 in ); corresponding descriptions of such features also apply herein. Layer 308 includes a portion 326 (e.g., a sublayer on a lower side of the layer) that is a resist and is therefore resistant to a given etchant (e.g., used in circuit fabrication). In examples not shown, the layer includes a plurality of portions (e.g., sublayers), each serving as a resist. Other configurations or arrangements of the plurality of portions are contemplated. Figure 3 Also shown is a structure 360 ​​in which layer 308 includes a portion 326 as a resist. A dashed line is used to indicate a boundary between portions of the layer.

[0020] Reference Figure 4A and Figure 4B A description of further examples is given. Figure 4A and Figure 4B A side cross-section of a structure during a method of a further example is schematically shown. Figure 4A and Figure 4B A related feature corresponds to the use of FIG. 2A to FIG. 2I In the case of describing a feature, the use of FIG. 2A to FIG. 2I The corresponding component symbol is 200 larger than the component symbol (for example, Figure 2C 202 in the Figure 4B 402); the corresponding descriptions of these features also apply in this article. Figure 4AA precursor 420 is shown being provided to the layer 408 and the wafer 402. The precursor includes a first portion 416 and a second portion 418. The method then includes doping at least one of the first portion 416 or the second portion 418 to form the layer 408 from the first portion 416 of the precursor 420 and to form the wafer 402 from the second portion 418 of the precursor 420 ( Figure 4B 408 and wafer 402 shown in FIG. 4 ). Doping may include implanting ions into at least one of first portion 416 or second portion 418, or diffusing ions into at least one of first portion 416 or second portion 418. Those skilled in the art will be familiar with such doping techniques. Figure 4B A layer 408 formed from a first portion 416 and a wafer 402 formed from a second portion 418 are shown. Figure 4B Also shown is a structure 462 obtained by doping at least one of the first portion 416 or the second portion 418 to form the layer 408 from the first portion 416 and the wafer 402 from the second portion 418 .

[0021] Reference Figure 5 A description of further examples is given. Figure 5 A bottom plan view of a structure during a method of a further example is schematically shown. Figure 5 A related feature corresponds to the use of FIG. 2A to FIG. 2I In the case of describing a feature, the use of FIG. 2A to FIG. 2I The corresponding component symbol is 300 larger than the component symbol (for example, Figure 2C 202 in the Figure 5 502 in FIG); corresponding descriptions of these features also apply herein. Layer 508 includes a first portion 522 and a second portion 524. The first portion 522 and the second portion 524 can be configured to reduce electrostatic damage to the electrically insulating wafer 502, for example by reducing an electric field gradient on the first surface or the second surface. The first portion 522 and the second portion 524 can be configured to reduce warping of the wafer 502 due to electrostatic damage. Other configurations or arrangements of the first portion 522 and the second portion 524 different from the configuration shown are contemplated, such as an array or a grid. Figure 5 Also shown is a structure 564 obtained by providing the layer 508 on the first surface. A dotted line is used to indicate a boundary between different parts of the layer.

[0022] A description of the various examples herein will now be given without reference to the drawings.

[0023] In various examples, a layer on a first surface of a wafer improves the performance of a circuit fabricated on a second surface of the wafer. For example, the layer may increase the repeatability of fabricating a circuit on the second surface of the wafer. A stiffness of the layer may be greater than a stiffness of the wafer. A heat capacity of the layer may be greater than a heat capacity of the wafer. The greater stiffness and / or heat capacity of the layer compared to the wafer may reduce the effects of mechanical forces or temperature changes on a circuit on the second surface of the wafer, respectively, which in turn may increase the performance of the circuit. A portion of the layer may be anti-reflective. For a PIC, anti-reflectivity may be desirable, for example, to reduce losses due to light escaping the PIC. The material of the layer may also be selected to be compatible with the wafer. For example: the thermal conductivity of the wafer is the same as the thermal conductivity of the layer; and / or a thermal expansion coefficient of the wafer is the same as a thermal expansion coefficient of the layer. A dry etch resistance rate of the wafer may be the same as a dry etch resistance rate of the layer. A plasma etch resistance rate of the wafer may be the same as a plasma etch resistance rate of the layer. An etch resistance herein is measured as, for example, a volume of material etched per unit time and depends on the etching technique. When a comparison is made herein between thermal conductivity, coefficient of thermal expansion, and etch resistance, identical conditions, such as pressure or etchant, are assumed. Identical herein means no more than or less than at least one of 1%, 2%, 5%, 10%, 20%, or 50%. Identical thermal conductivity, coefficient of thermal expansion, dry etch resistance, wet etch resistance, and / or plasma etch resistance of layers and wafers can simplify processing of the wafer, simplify fabrication of a circuit on the second surface of the wafer, and / or increase the performance of a circuit on the second surface of the wafer.

[0024] In various examples, providing the layer and / or providing the electrically insulating wafer comprises at least one of: surface passivation, photolithography, ion implantation, etching, dry etching, ion etching, wet etching, buffered oxide etching, plasma ashing, thermal treatment, annealing, thermal oxidation, chemical vapor deposition, atomic layer deposition, laser lift-off, electrochemical deposition, electroplating, physical vapor deposition, or chemical mechanical polishing. As will be appreciated by those skilled in the art, etching may be used to remove at least a portion of the layer but not all of the layer.

[0025] In various embodiments, the method includes epitaxially forming at least a portion of the layer on the first surface. Metal organic vapor phase epitaxy (MOVPE) or molecular beam epitaxy (MBE) can be used to epitaxially form the layer. Other epitaxial techniques are contemplated. The method may include bonding at least a portion of the layer to the first surface. For example, bonding includes forming a chemical bond, forming a mechanical bond, melt bonding, gold hot pressing, anodic bonding, heat treatment, photocuring, exposure to a catalyst and / or application of pressure. Other bonding techniques are contemplated.

[0026] Processing of the second surface may include various techniques, such as bonding a layer to the second surface, etching, and / or other techniques, for example, for fabricating a circuit. Fabricating a circuit on the second surface may include at least one of etching, epitaxy, dry etching, plasma etching, or photolithography. For example, fabricating the circuit includes at least one of: etching at least a portion of the second surface to at least partially form the circuit; etching at least a portion of an etch precursor for the circuit to at least partially form the circuit, the etch precursor being located on the second surface; photolithography of at least a portion of the second surface to at least partially form the circuit; photolithography of at least a portion of a lithography precursor for the circuit to at least partially form the circuit, the lithography precursor being located on the second surface; epitaxially forming at least a portion of the circuit on the second surface; or epitaxially forming a precursor for the circuit on the second surface. A precursor is a precursor for the circuit. An etching precursor is, for example, a resist. A photolithography precursor is, for example, a resist.

[0027] The circuit may be at least one of: a PIC or an integrated circuit (IC). Other circuits are contemplated. The circuit may include at least one of: silicon, gallium, germanium, lithium niobate, graphene, indium, or an alloy, oxide, nitride, or phosphide of at least one of these. Those skilled in the art will readily understand how to form a circuit on the second surface, for example, using techniques such as: metal organic vapor phase epitaxy, surface passivation, optical lithography, ion implantation, etching, dry ion etching, wet etching, buffered oxide etching, plasma ashing, heat treatment, annealing, thermal oxidation, chemical vapor deposition, atomic layer deposition, physical vapor deposition, molecular beam epitaxy, laser lift-off, electrochemical deposition, electroplating, or chemical mechanical polishing.

[0028] The circuit may be a PIC or be used in a PIC. The circuit may be formed using a universal photonic platform. A universal photonic platform uses standardized procedures to manufacture photonic components and / or standardized photonic components. Forming circuits using a universal photonic platform may be simpler, cheaper, faster, and have a wide range of applications. A commercial material platform for PICs is indium phosphide. Optical active and passive functions may be integrated on the same chip by manufacturing a PIC using the indium phosphide (InP) universal platform. Other material platforms such as silicon, gallium arsenide, or lithium niobate may be used as a platform for PICs. A PIC may include hundreds of components integrated into a single chip.

[0029] Examples herein are directed to a method of making a device, the method comprising any of the methods described herein. Further examples are directed to a device obtained by a method described herein. The device may be an electronic device and / or a photonic device. The first surface and the second surface of a wafer obtained by a method described herein may be flatter than a wafer obtained by another method not described herein. A device obtained by a method described herein may have improved performance compared to a device obtained by a known technique not described herein.

[0030] Some of the terms, techniques, and features used in this article are now described in detail.

[0031] The electrostatic chuck herein may be a Coulombic electrostatic chuck or a Johnson-Rahbek electrostatic chuck. A Coulomb electrostatic chuck includes an electrode and an electrical insulator. When the electrostatic chuck is clamped to the wafer, the electrical insulator is configured to be between the electrode and the wafer. A Johnson-Rahbek electrostatic chuck includes an electrode and a dielectric. When the electrostatic chuck is clamped to the wafer, the dielectric is configured to be between the electrode and the wafer. An electrostatic chuck may include a monopole, a dipole, or a bipole for applying an electric field, and such electrostatic chucks may be referred to as a monopole electrostatic chuck, a dipole electrostatic chuck, or a bipole electrostatic chuck, respectively. Electrostatic clamping and / or fabricating a circuit on an electrostatically clamped wafer may include flowing a fluid over the wafer. The fluid may be an inert gas, such as helium. Electrostatic clamping by applying an electric field to the electrostatic chuck may include applying an electromotive force to one or more electrodes of the electrostatic chuck. When a fluid is not flowing on the wafer, the electromotive force for electrostatic clamping is, for example, greater than at least one of 400 volts, 500 volts, 700 volts, 1000 volts, 1500 volts, 5000 volts, or 10,000 volts. When a fluid is flowing on the wafer, the electromotive force for electrostatic clamping applied to one or more electrodes of the electrostatic chuck is, for example, greater than at least one of 700 volts, 800 volts, 1000 volts, 1500 volts, 5000 volts, or 10,000 volts. One volt (V) is one kilogram-meter 2 ·Second -3 ·ampere -1 (kg·m 2 ·s -3 ·A -1 The electrostatic chuck can be removed from the layer (or the electrostatic clamping can be released) by reducing the electric field applied to at least one of the electrostatic chuck or the layer (e.g., by reducing the electromotive force applied to one or more electrodes of the electrostatic chuck). The electrostatic chuck can be removed from the layer using a mechanical force.

[0032] A wafer herein may also be considered a slice, a substrate, or a chip. The term wafer is used herein to refer to a relatively thin (e.g., flat) portion of a material, and may be crystalline. A wafer may be a crystalline semiconductor or dielectric disk used in a semiconductor fab, such as a 300 mm silicon disk. A wafer may be a crystalline InP disk used in a semiconductor fab. A wafer may be a 25 mm, 51 mm, 76 mm, 100 mm, 200 mm, or 300 mm diameter disk.

[0033] A wafer herein is, for example, a single layer of the same homogeneous material, but for other examples, it is contemplated that a wafer instead includes one or more sub-layers or portions, each of which is deposited or formed independently of one another (e.g., a stack of layers is formed one after another during a manufacturing process, and the layers may be collectively considered a wafer). A wafer may include portions of different materials, for example, for manufacturing.

[0034] The wafer herein may be a semiconductor, a III-V semiconductor, a polymer and / or a dielectric. The wafer may include at least one of: silicon, gallium, germanium, lithium niobate, graphene, indium or an alloy, oxide, nitride or phosphide of at least one of these. The wafer includes an electrical insulator, which may be an electrically insulating material and / or an electrically insulating structure. The wafer may reduce or prevent electrical crosstalk and / or conduction of ions and / or electrons between a first surface and a second surface. The wafer may have an electrical conductivity at 20 degrees Celsius (293 degrees Kelvin) of less than at least one of 0.00001 Siemens / meter, 0.0001 Siemens / meter, 0.001 Siemens / meter, 0.01 Siemens / meter, 0.1 Siemens / meter, 1 Siemens / meter or 10 Siemens / meter. One Siemens / meter (S / m) is one ampere. 2 ·Second 3 ·kilogram -1 ·rice -3 (kg -1 ·m -3 ·s 3 ·A 2 The resistivity of the wafer at 20 degrees Celsius (293 degrees Kelvin) may be greater than at least one of 0.1 ohm-meter, 1 ohm-meter, 10 ohm-meter, 100 ohm-meter, 1000 ohm-meter, 10,000 ohm-meter, or 100,000 ohm-meter. One ohm-meter (Ω·m) is one kilogram-meter. 3 ·ampere -2 ·Second -3 (kg·m 3 ·s -3 ·A -2 ).

[0035] A layer herein may be a single layer of the same homogeneous material, but for other examples, it is also contemplated that a layer instead includes one or more sub-layers or portions, each of which is deposited or formed independently of one another (e.g., a stack of sub-layers is formed one after another during a manufacturing process, which sub-layers may be collectively considered a layer). A layer may have sub-portions of different materials, such as used in manufacturing. Sub-portions of a layer may have different dopant concentrations.

[0036] A metallic element herein is an element that is not hydrogen, helium, boron, carbon, nitrogen, oxygen, fluorine, neon, silicon, phosphorus, sulfur, chlorine, argon, germanium, arsenic, selenium, bromine, krypton, antimony, tellurium, iodine, xenon, or radon. A metallic element may be considered an element that is a metallic material when isolated at 293 degrees Kelvin. A metallic element is, for example, indium, gallium, tin, lithium, niobium, zinc, or iron. Metalloid elements are not considered metallic elements.

[0037] The non-metallic conductive material includes, for example, at least one of a semiconductor, a dielectric, an n-type semiconductor, a metalloid, a III-V semiconductor, silicon, gallium, germanium, lithium niobate, graphene, indium, or an alloy, oxide, nitride, or phosphide of at least one of these. The wafer may include indium phosphide, and the layer may include n-type doped indium phosphide. The metalloids herein are boron, silicon, germanium, arsenic, antimony, and tellurium. The non-metallic conductive material may be a conductive material and / or a conductive structure. In some examples, the conductivity of the layer does not reduce or prevent electrical crosstalk and / or significant conduction of ions and / or electrons across the layer. The electrical conductivity of the layer at 20 degrees Celsius (293 degrees Kelvin) may be greater than at least one of 0.1 Siemens / meter, 1 Siemens / meter, 10 Siemens / meter, 100 Siemens / meter, 1000 Siemens / meter, 10,000 Siemens / meter, or 100,000 Siemens / meter. One Siemens / meter (S / m) is equal to one ampere. 2 ·Second 3 ·kilogram -1 ·rice -3 (kg -1 ·m -3 ·s 3 ·A 2 The resistivity of the layer at 20 degrees Celsius (293 degrees Kelvin) may be less than at least one of 0.00001 ohm-meter, 0.0001 ohm-meter, 0.001 ohm-meter, 0.01 ohm-meter, 0.1 ohm-meter, 1 ohm-meter, or 10 ohm-meter. One ohm-meter (Ω·m) is equal to one kilogram·meter 3 ·ampere -2 ·Second -3 (kg·m 3 ·s -3 ·A -2 ).

[0038] It should be understood that any feature described in relation to any one example may be used alone or in combination with other features described, and may also be used in combination with one or more features of any other example or any combination of any other example. In addition, equivalents and modifications not described above may also be adopted without departing from the scope of the attached invention claims.

Claims

1. A method, comprising: Providing an electrically insulating wafer including a first surface and a second surface for processing; and A layer is provided on the first surface, wherein the layer is non-metallic, electrically conductive, and is adapted for electrostatic clamping to an electrostatic chuck.

2. The method of claim 1, comprising epitaxially forming at least part of the layer on the first surface.

3. A method as claimed in claim 1 or claim 2, comprising bonding at least part of the layer to the first surface.

4. A method as claimed in any preceding claim, wherein: The layer includes a non-metallic conductive material including at least one metallic element.

5. A method as claimed in any preceding claim, wherein: The layer includes at least one of the following: a semiconductor, a III-V semiconductor, an n-type doped semiconductor, or a dielectric.

6. A method as claimed in any preceding claim, comprising electrostatically clamping the layer to the electrostatic chuck.

7. The method of claim 6, wherein: After electrostatically clamping the layer to the electrostatic chuck, the first surface and the second surface are planar.

8. A method as claimed in claim 6 or claim 7, comprising removing the electrostatic chuck from the layer.

9. A method as claimed in any preceding claim, comprising fabricating a circuit on the second surface.

10. The method of claim 9, comprising at least one of the following: etching at least a portion of the second surface to at least partially form the circuit; etching at least a portion of an etch precursor of the circuit to at least partially form the circuit, the etch precursor being located on the second surface; performing photolithography on at least a portion of the second surface to at least partially form the circuit; performing photolithography on at least a portion of a photolithographic precursor of the circuit to at least partially form the circuit, the photolithographic precursor being located on the second surface; epitaxially forming at least part of the circuit on the second surface; or A precursor of the circuit is epitaxially formed on the second surface.

11. The method of claim 9 or claim 10, wherein: The circuit is at least one of an integrated circuit or a photonic integrated circuit.

12. A method as claimed in any preceding claim, wherein: The method includes etching, and the layer includes a resist.

13. A method as claimed in any preceding claim, wherein: A thermal conductivity of the electrically insulating wafer is the same as a thermal conductivity of the layer.

14. A method as claimed in any preceding claim, wherein: A thermal expansion coefficient of the electrically insulating wafer is the same as a thermal expansion coefficient of the layer.

15. A method as claimed in any preceding claim, wherein: At least one of the following: The first resist dry etching rate of the wafer may be the same as the first resist dry etching rate of the layer; or The resist plasma etching rate of the electrically insulating wafer is the same as the resist plasma etching rate of the layer.

16. A method as claimed in any preceding claim, comprising: providing a precursor to the layer and the electrically insulating wafer, the precursor comprising a first portion and a second portion; and At least one of the first portion or the second portion is doped to form the layer from the first portion of the precursor and to form the electrically insulating wafer from the second portion of the precursor.

17. A method as claimed in any preceding claim, wherein: A stiffness of the layer is greater than a stiffness of the electrically insulating wafer.

18. A method as claimed in any preceding claim, wherein: A heat capacity of the layer is greater than a heat capacity of the electrically insulating wafer.

19. A method as claimed in any preceding claim, comprising at least partially removing the layer from the electrically insulating wafer or removing the layer from the electrically insulating wafer.

20. A method as claimed in any preceding claim, wherein: Part of this layer is anti-reflective.

21. A method as claimed in any preceding claim, wherein: The electrically insulating wafer includes at least one of a dielectric, a semiconductor, a III-V semiconductor, silicon or indium phosphide.

22. A method as claimed in any preceding claim, wherein: The electrically insulating wafer includes indium phosphide, and the layer includes n-type doped indium phosphide.

23. A structure obtainable by a method as claimed in any preceding claim.

24. A method of manufacturing a device, the method comprising the method of any one of claims 1 to 22.

25. A device obtained by the method according to claim 24.

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