Multi-row programming operations in artificial neural network arrays

Abstract

Numerous examples of programming a plurality of rows in an array in an artificial neural network as part of a single programming operation are disclosed. In one example, a method includes ramping up an output of a high voltage generator to a first voltage level; programming a plurality of words of K rows of memory cells in an array of memory cells using the output of the high voltage generator while maintaining the output of the high voltage generator at the first voltage level, where K > 1; and after the programming, ramping down the output of the high voltage generator to a second voltage level.

Description

[0001] Priority declaration

[0002] This application claims priority to U.S. patent application No. 18 / 076,129, filed on December 6, 2022, and entitled “Multiple Row Programming Operation in Artificial Neural Network Array,” and U.S. Provisional Patent Application No. 63 / 409,177, filed on September 22, 2022, and entitled “Multiple Row Programming Operation in Artificial Neural Network Array.” Technical Field

[0003] Many examples of programming multiple rows in an array in an artificial neural network in a single programming operation are disclosed. Background Art

[0004] Artificial neural networks simulate biological neural networks (the central nervous system of animals, especially the brain), and are used to estimate or approximate functions that may depend on a large number of inputs and are usually unknown. Artificial neural networks typically consist of layers of interconnected "neurons" that exchange messages with each other.

[0005] FIG1 illustrates an artificial neural network, where circles represent inputs or layers of neurons. Connections (called synapses) are represented by arrows and have numerical weights that can be tuned based on experience. This allows the neural network to adapt to the input and be able to learn. Typically, a neural network includes multiple layers of inputs. There are typically one or more intermediate layers of neurons, and an output layer of neurons that provide the output of the neural network. Neurons at each level make decisions based on data received from the synapses, either individually or collectively.

[0006] One of the main challenges in developing artificial neural networks for high-performance information processing is the lack of adequate hardware technology. In fact, practical neural networks rely on a large number of synapses to achieve high connectivity between neurons, i.e. very high computational parallelism. In principle, this complexity can be achieved by digital supercomputers or clusters of dedicated graphics processing units. However, these approaches, in addition to their high cost, are also mediocre in energy efficiency compared to biological networks, which consume much less energy mainly due to the low-precision analog calculations they perform. CMOS analog circuits have been used for artificial neural networks, but given the large number of neurons and synapses, the synapses of most CMOS implementations are too large.

[0007] Applicant previously disclosed an artificial (simulated) neural network using one or more non-volatile memory arrays as synapses in U.S. Patent Application Publication 2017 / 0337466A1, which is incorporated herein by reference. The non-volatile memory array operates as an analog neural memory and includes non-volatile memory cells arranged in rows and columns. The neural network includes a first plurality of synapses configured to receive a first plurality of inputs and generate a first plurality of outputs therefrom, and a first plurality of neurons configured to receive a first plurality of outputs. The first plurality of synapses includes a plurality of memory cells, wherein each of the memory cells includes: a source region and a drain region spaced apart formed in a semiconductor substrate, wherein a channel region extends between the source region and the drain region; a floating gate disposed above a first portion of the channel region and insulated from the first portion; and a non-floating gate disposed above a second portion of the channel region and insulated from the second portion. Each of the plurality of memory cells stores a weight value corresponding to a plurality of electrons on the floating gate. The plurality of memory cells multiply the first plurality of inputs by the stored weight values ​​to generate a first plurality of outputs.

[0008] Non-volatile memory cell

[0009] Nonvolatile memory is well known. For example, U.S. Pat. No. 5,029,130 ​​(“the '130 patent”), which is incorporated herein by reference, discloses an array of split-gate nonvolatile memory cells, which is a type of flash memory cell. Such a memory cell 210 is shown in FIG. 2 . Each memory cell 210 includes a source region 14 and a drain region 16 formed in a semiconductor substrate 12 with a channel region 18 therebetween. A floating gate 20 is formed over and insulated from (and controls the conductivity of) a first portion of the channel region 18, and is formed over a portion of the source region 14. A word line terminal 22 (which is typically coupled to a word line) has a first portion disposed over and insulated from (and controls the conductivity of) a second portion of the channel region 18, and a second portion extending upward and located over the floating gate 20. The floating gate 20 and the word line terminal 22 are insulated from the substrate 12 by a gate oxide. A bit line 24 is coupled to the drain region 16.

[0010] Memory cell 210 is erased (where electrons are removed from the floating gate) by placing a high positive voltage on word line terminal 22, which causes the electrons on floating gate 20 to tunnel through the intervening insulator via Fowler-Nordheim (FN) tunneling from floating gate 20 to word line terminal 22.

[0011] The memory cell 210 is programmed by source side injection (SSI) with hot electrons (where electrons are placed on the floating gate) by placing a positive voltage on the word line terminal 22 and a positive voltage on the source region 14. The electron flow will flow from the drain region 16 to the source region 14. When the electrons reach the gap between the word line terminal 22 and the floating gate 20, the electrons will accelerate and become hot. Due to the electrostatic attraction from the floating gate 20, some of the heated electrons will be injected through the gate oxide onto the floating gate 20.

[0012] The memory cell 210 is read by placing a positive read voltage on the drain region 16 and the word line terminal 22 (which turns on the portion of the channel region 18 below the word line terminal). If the floating gate 20 is positively charged (i.e., the electrons are erased), the portion of the channel region 18 below the floating gate 20 is also turned on, and current will flow through the channel region 18, which is sensed as an erased state or a "1" state. If the floating gate 20 is negatively charged (i.e., programmed by electrons), the portion of the channel region below the floating gate 20 is mostly or completely turned off, and current will not (or very little) flow through the channel region 18, which is sensed as a programmed state or a "0" state.

[0013] Table 1 depicts typical voltage and current ranges that may be applied to the terminals of the memory cell 210 for performing read operations, erase operations, and program operations:

[0014] Table 1: Operation of the flash memory unit 210 of FIG. 2

[0015] WL BL SL Read 2V-3V 0.6V-2V 0V Erase About 11V-13V 0V 0V programming 1V-2V 10.5μA-3μA 9V-10V

[0016] Other split gate memory cell configurations are known as other types of flash memory cells. For example, FIG. 3 depicts a four-gate memory cell 310, which includes a source region 14, a drain region 16, a floating gate 20 above a first portion of a channel region 18, a select gate 22 (typically coupled to a word line WL) above a second portion of the channel region 18, a control gate 28 above the floating gate 20, and an erase gate 30 above the source region 14. This configuration is described in U.S. Pat. No. 6,747,310, which is incorporated herein by reference for all purposes. Here, except for the floating gate 20, all gates are non-floating gates, meaning that they are electrically connected or capable of being electrically connected to a voltage source. Programming is performed by heated electrons from the channel region 18 that inject themselves into the floating gate 20. Erasing is performed by electrons tunneling from the floating gate 20 to the erase gate 30.

[0017] Table 2 depicts typical voltage and current ranges that may be applied to the terminals of the memory cell 310 for performing read operations, erase operations, and program operations:

[0018] Table 2: Operation of the flash memory unit 310 of FIG. 3

[0019] WL / SG BL CG EG SL Read 1.0V-2V 0.6V-2V 0V-2.6V 0V-2.6V 0V Erase -0.5V / 0V 0V 0V / -8V 8V-12V 0V programming 1V 0.1μA-1μA 8V-11V 4.5V-9V 4.5V-5V

[0020] FIG4 depicts a tri-gate memory cell 410, which is another type of flash memory cell. Memory cell 410 is the same as memory cell 310 of FIG3, except that memory cell 410 does not have a separate control gate. Erase operations (thus erasing by using an erase gate) and read operations are similar to the operations of FIG3, except that no control gate bias is applied. Program operations are also completed without a control gate bias, and therefore, a higher voltage is applied on the source line during a programming operation to compensate for the lack of a control gate bias.

[0021] Table 3 depicts typical voltage and current ranges that may be applied to the terminals of the memory cell 410 for performing read operations, erase operations, and program operations:

[0022] Table 3: Operation of the flash memory unit 410 of FIG. 4

[0023] WL / SG BL EG SL Read 0.7V-2.2V 0.6V-2V 0V-2.6V 0V Erase -0.5V / 0V 0V 11.5V 0V programming 1V 0.2μA-3μA 4.5V 7V-9V

[0024] FIG5 depicts a stacked gate memory cell 510, which is another type of flash memory cell. Memory cell 510 is similar to memory cell 210 of FIG2, except that floating gate 20 extends over the entire channel region 18, and control gate 22 (which here will be coupled to the word line) extends over floating gate 20, separated by an insulating layer (not shown). Erasing is performed by FN tunneling of electrons from the FG to the substrate, programming is performed by channel hot electron (CHE) injection at the region between channel 18 and drain region 16, by electron flow from source region 14 toward drain region 16, and a read operation similar to memory cell 210 with a higher control gate voltage.

[0025] Table 4 depicts typical voltage ranges that may be applied to the terminals of the memory cell 510 and the substrate 12 for performing read operations, erase operations, and program operations:

[0026] Table 4: Operation of the flash memory unit 510 of FIG. 5

[0027] CG BL SL Substrate Read 2V-5V 0.6V-2V 0V 0V Erase -8V to -10V / 0V FLT FLT 8V-10V / 15V-20V programming 8V-12V 3V-5V 0V 0V

[0028] The methods and devices described herein can be applied to other non-volatile memory technologies, such as but not limited to FINFET split-gate flash memory or stacked-gate flash memory, NAND flash memory, SONOS (silicon-oxide-nitride-oxide-silicon, charge trapped in nitride), MONOS (metal-oxide-nitride-oxide-silicon, metal charge trapped in nitride), ReRAM (resistive RAM), PCM (phase change memory), MRAM (magnetic RAM), FeRAM (ferroelectric RAM), CT (charge trapping) memory, CN (carbon tube) memory, OTP (two-level or multi-level one-time programmable) and CeRAM (correlated electron RAM), etc.

[0029] In order to utilize a memory array comprising one of the above-described types of non-volatile memory cells in an artificial neural network, two modifications are made. First, the circuitry is configured so that each memory cell can be individually programmed, erased, and read without adversely affecting the memory states of other memory cells in the array, as further explained below. Second, continuous (analog) programming of the memory cells is provided.

[0030] Specifically, the memory state (i.e., the charge on the floating gate) of each memory cell in the array can be changed from a fully erased state to a fully programmed state, and vice versa, independently and continuously with minimal disturbance to other memory cells. This means that the cell storage device is actually analog, or at least can store one of many discrete values ​​(such as 16 or 64 different values), which allows very precise and individual tuning of all the memory cells in the memory array, and makes the memory array ideal for storing and fine tuning the synaptic weights of a neural network.

[0031] Neural Network Using Non-Volatile Memory Cell Array

[0032] Figure 6 The present example conceptually illustrates a non-limiting example of a neural network utilizing a non-volatile memory array. This example uses a non-volatile memory array neural network for a facial recognition application, but any other suitable application may also be implemented using a neural network based on a non-volatile memory array.

[0033] For this example, S0 is the input layer, which is a 32x32 pixel RGB image with 5 bits of precision (i.e., three 32x32 pixel arrays, one for each color R, G, and B, with 5 bits of precision per pixel). Synapse CB1 from input layer S0 to layer C1 applies different sets of weights in some cases and shared weights in other cases, and scans the input image with a 3x3 pixel overlapping filter (kernel), shifting the filter by 1 pixel (or more than 1 pixel as the model dictates). Specifically, the values ​​of 9 pixels in the 3x3 portion of the image (i.e., called the filter or kernel) are provided to synapse CB1, where these 9 input values ​​are multiplied by the appropriate weights, and after summing the outputs of the multiplications, a single output value is determined and provided by the first synapse of CB1 for generating a pixel of one of the feature maps of layer C1. The 3x3 filter is then shifted right by one pixel within the input layer S0 (i.e., a column of three pixels on the right is added, and a column of three pixels on the left is released), whereby the 9 pixel values ​​in this newly positioned filter are provided to the synapse CB1, where they are multiplied by the same weights and a second single output value is determined by the associated synapse. This process continues until the 3x3 filter has scanned all three colors and all bits (precision values) over the entire 32x32 pixel image of the input layer S0. The process is then repeated using different sets of weights to generate different feature maps for layer C1 until all feature maps for layer C1 are calculated.

[0034] At layer C1, in this example, there are 16 feature maps, each with 30x30 pixels. Each pixel is a new feature pixel extracted from the product of the input and the kernel, so each feature map is a two-dimensional array, so in this example, layer C1 consists of a two-dimensional array of 16 layers (remember that the layers and arrays referred to in this article are logical relationships, not necessarily physical relationships, that is, arrays do not have to be oriented to physical two-dimensional arrays). Each of the 16 feature maps in layer C1 is generated by one of sixteen different sets of synaptic weights applied to the filter scan. The C1 feature maps can all relate to different aspects of the same image features, such as boundary identification. For example, a first map (generated using a first set of weights, shared for all scans used to generate the first map) can identify circular edges, a second map (generated using a second set of weights different from the first set of weights) can identify rectangular edges, or the aspect ratio of certain features, and so on.

[0035] Before passing from layer C1 to layer S1, an activation function P1 (pooling) is applied, which pools the values ​​from consecutive non-overlapping 2x2 regions in each feature map. The purpose of the pooling function P1 is to average neighboring positions (or a max function can also be used) to, for example, reduce the dependency of edge positions and reduce the data size before entering the next stage. At layer S1, there are 16 15x15 feature maps (i.e., sixteen different arrays, each with 15x15 pixels). The synapse CB2 from layer S1 to layer C2 scans the map in layer S1 using a 4x4 filter, where the filter is shifted by 1 pixel. At layer C2, there are 22 12x12 feature maps. Before passing from layer C2 to layer S2, an activation function P2 (pooling) is applied, which pools the values ​​from consecutive non-overlapping 2x2 regions in each feature map. At layer S2, there are 22 6x6 feature maps. An activation function (pooling) is applied to the synapse CB3 from layer S2 to layer C3, where each neuron in layer C3 is connected to each map in layer S2 via a corresponding synapse of CB3. At layer C3, there are 64 neurons. Synapse CB4 from layer C3 to output layer S3 completely connects C3 to S3, i.e., each neuron in layer C3 is connected to each neuron in layer S3. The output at S3 includes 10 neurons, where the highest output neuron determines the class. For example, the output may indicate recognition or classification of the content of the original image.

[0036] The synapses at each layer are implemented using an array or a portion of an array of non-volatile memory cells.

[0037] Figure 7 A block diagram of an array that can be used for this purpose is shown in FIG. 3. The vector-matrix multiplication (VMM) array 32 includes non-volatile memory cells and serves as a synapse between one layer and the next (such as Figure 6 CB1, CB2, CB3 and CB4 in FIG. 3 ). Specifically, the VMM array 32 includes a nonvolatile memory cell array 33, an erase gate and word line gate decoder 34, a control gate decoder 35, a bit line decoder 36 and a source line decoder 37, which decode the corresponding inputs of the nonvolatile memory cell array 33. The input to the VMM array 32 may come from the erase gate and word line gate decoder 34 or from the control gate decoder 35. In this example, the source line decoder 37 also decodes the output of the nonvolatile memory cell array 33. Alternatively, the bit line decoder 36 may decode the output of the nonvolatile memory cell array 33.

[0038] The non-volatile memory cell array 33 serves two purposes. First, it stores weights to be used by the VMM array 32. Second, the non-volatile memory cell array 33 effectively multiplies the input with the weights stored in the non-volatile memory cell array 33 and each output line (source line or bit line) adds them to produce an output, which will serve as the input of the next layer or the input of the final layer. By performing multiplication and addition functions, the non-volatile memory cell array 33 eliminates the need for separate multiplication and addition logic circuits, and is also power efficient due to its in-situ memory calculations.

[0039] The output of the non-volatile memory cell array 33 is provided to a differential summer (such as a summing operational amplifier or a summing current mirror) 38, which sums the output of the non-volatile memory cell array 33 to create a single value for the convolution. The differential summer 38 is arranged to perform the summing of positive and negative weights.

[0040] The summed output value of the difference summer 38 is then provided to the activation function block 39, which modifies the output. The activation function block 39 may provide a sigmoid, tanh, or ReLU function. The modified output value of the activation function block 39 becomes the next layer (e.g., Figure 6 The elements of the feature map of layer C1 in the image are then applied to the next synapse to produce the next feature map layer or the final layer. Thus, in this example, the non-volatile memory cell array 33 constitutes a plurality of synapses (which receive their inputs from an existing neuron layer or from an input layer such as an image database), and the summing operational amplifier 38 and the activation function block 39 constitute a plurality of neurons.

[0041] Figure 7 The inputs to the VMM array 32 (WLx, EGx, CGx, and optionally BLx and SLx) may be analog levels, binary levels, or digital bits (in which case a DAC is provided to convert the digital bits to the appropriate input analog levels), and the outputs may be analog levels, binary levels, or digital bits (in which case an output ADC is provided to convert the output analog levels to digital bits).

[0042] Figure 8 1 is a block diagram depicting the use of multiple layers of VMM arrays 32, labeled here as VMM arrays 32a, 32b, 32c, 32d, and 32e. Figure 8As shown, the input (denoted as Inputx) is converted from digital to analog by a digital-to-analog converter 31 and provided to an input VMM array 32a. The converted analog input may be a voltage or a current. The first level of input D / A conversion may be accomplished by using a function or LUT (lookup table) that maps the input Inputx to the appropriate analog level of the matrix multiplier of the input VMM array 32a. The input conversion may also be accomplished by an analog-to-analog (A / A) converter to convert an external analog input into a mapped analog input to the input VMM array 32a.

[0043] The output generated by the input VMM array 32a is provided as input to the next VMM array (hidden level 1) 32b, which in turn generates outputs provided as input to the next VMM array (hidden level 2) 32c, and so on. The layers of the VMM array 32 serve as different layers of synapses and neurons of a convolutional neural network (CNN). Each VMM array 32a, 32b, 32c, 32d, and 32e can be an independent physical non-volatile memory array, or multiple VMM arrays can utilize different portions of the same non-volatile memory array, or multiple VMM arrays can utilize overlapping portions of the same physical non-volatile memory array. Figure 8 The example shown includes five layers (32a, 32b, 32c, 32d, 32e): one input layer (32a), two hidden layers (32b, 32c) and two fully connected layers (32d, 32e). One of ordinary skill in the art will appreciate that this is merely an example and that, on the contrary, the system may include more than two hidden layers and more than two fully connected layers.

[0044] Vector-Matrix Multiplication (VMM) Array

[0045] Fig. 9 Depicted is a neuron VMM array 900 that is particularly suitable for use with the memory cells 310 shown in FIG. 3 and serves as a synapse and component of neurons between an input layer and the next layer. The VMM array 900 includes a memory array 901 of nonvolatile memory cells and a reference array 902 of nonvolatile reference memory cells (at the top of the array). Alternatively, another reference array may be placed at the bottom.

[0046] In the VMM array 900, control gate lines (such as control gate line 903) extend in the vertical direction (so reference array 902 is orthogonal to control gate line 903 in the row direction), and erase gate lines (such as erase gate line 904) extend in the horizontal direction. Here, the input to the VMM array 900 is set on the control gate lines (CG0, CG1, CG2, CG3), and the output of the VMM array 900 appears on the source lines (SL0, SL1). In one example, only even rows are used, and in another example, only odd rows are used. The current placed on each source line (SL0, SL1, respectively) performs a summing function of all currents from the memory cells connected to that particular source line.

[0047] As described herein for neural networks, non-volatile memory cells of VMM array 900 (ie, memory cells 310 of VMM array 900 ) may be configured to operate in a sub-threshold region.

[0048] The nonvolatile reference memory cell and the nonvolatile memory cell described herein are biased in weak inversion (subthreshold region):

[0049] Ids=Io*e (Vg-Vth) / nVt =w*Io*e (Vg) / nVt ,

[0050] where w = e (-Vth) / nVt

[0051] Where Ids is the drain to source current; Vg is the gate voltage on the memory cell; Vth is the threshold voltage of the memory cell; Vt is the thermal voltage = k*T / q, where k is the Boltzmann constant, T is the temperature in Kelvin, and q is the electron charge; n is the slope factor = 1+(Cdep / Cox), where Cdep = the capacitance of the depletion layer, and Cox is the capacitance of the gate oxide layer; Io is the memory cell current at a gate voltage equal to the threshold voltage, and Io is related to (Wt / L)*u*Cox*(n-1)*Vt 2 is proportional to , where u is the carrier mobility, and Wt and L are the width and length of the memory cell, respectively.

[0052] For an I to V logarithmic converter that uses a memory cell (such as a reference memory cell or a peripheral memory cell) or a transistor to convert the input current into an input voltage:

[0053] Vg=n*Vt*log[Ids / wp*Io]

[0054] Wherein, wp is w of a reference memory cell or a peripheral memory cell.

[0055] For a memory array used as a vector matrix multiplier VMM array with current input, the output current is:

[0056] Iout=wa*Io*e (Vg) / nVt ,Right now

[0057] Iout=(wa / wp)*Iin=W*Iin

[0058] W=e (Vthp-Vtha) / nVt

[0059] Here, wa = w for each memory cell in the memory array.

[0060] Vthp is the effective threshold voltage of the peripheral memory cells, and Vtha is the effective threshold voltage of the main (data) memory cells. Note that the threshold voltage of the transistor is a function of the substrate bulk bias voltage, and the substrate bulk bias voltage, denoted as Vsb, can be modulated to compensate for various conditions at this temperature. The threshold voltage Vth can be expressed as:

[0061] Vth=Vth0+γ(SQRT|Vsb-2*φF)-SQRT|2*φF|)

[0062] where Vth0 is the threshold voltage with zero substrate bias, φF is the surface potential, and γ is the bulk effect parameter.

[0063] The word line or control gate may be used as the input of the memory cell for the input voltage.

[0064] Alternatively, the flash memory cells of the VMM array described herein may be configured to operate in the linear region:

[0065] Ids=β*(Vgs-Vth)*Vds;β=u*Cox*Wt / L

[0066] W=α(Vgs-Vth)

[0067] This means that the weight W in the linear region is proportional to (Vgs-Vth)

[0068] The word line or control gate or bit line or source line can be used as the input of the memory cell operating in the linear region. The bit line or source line can be used as the output of the memory cell.

[0069] For an IV linear converter, a memory cell (such as a reference memory cell or a peripheral memory cell) or a transistor operating in a linear region may be used to linearly convert an input / output current into an input / output voltage.

[0070] Alternatively, the memory cells of the VMM array described herein may be configured to operate in the saturation region:

[0071] Ids=1 / 2*β*(Vgs-Vth) 2 ; β=u*Cox*Wt / L

[0072] Wα(Vgs-Vth) 2 , which means weight W and (Vgs-Vth) 2 Proportional

[0073] The word line, control gate, or erase gate can be used as the input of the memory cell operating in the saturation region. The bit line or source line can be used as the output of the output neuron.

[0074] Alternatively, the memory cells of the VMM array described herein may be used for all regions or combinations thereof (subthreshold, linear or saturation regions) of each layer or multiple layers of a neural network.

[0075] U.S. Patent No. 10,748,630 describes Figure 7 Other examples of VMM arrays 32 of , which are incorporated herein by reference. As described herein, source lines or bit lines can be used as neuron outputs (current summing outputs).

[0076] Fig.10 A neuron VMM array 1000 is depicted, which is particularly suitable for the memory cell 210 shown in FIG. 2 and serves as a synapse between an input layer and a next layer. The VMM array 1000 includes a memory array 1003 of nonvolatile memory cells, a reference array 1001 of a first nonvolatile reference memory cell, and a reference array 1002 of a second nonvolatile reference memory cell. The reference arrays 1001 and 1002 arranged in the column direction of the array are used to convert the current input flowing into the terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs WL0, WL1, WL2, and WL3. In practice, the first nonvolatile reference memory cell and the second nonvolatile reference memory cell are diode-connected through a multiplexer 1014 (only partially depicted), in which the current input flows. The reference cells are tuned (e.g., programmed) to a target reference level. The target reference level is provided by a reference microarray matrix (not shown).

[0077] The memory array 1003 serves two purposes. First, it stores the weights that the VMM array 1000 will use on its corresponding memory cells. Second, the memory array 1003 effectively multiplies the inputs (i.e., the current inputs provided in the terminals BLR0, BLR1, BLR2, and BLR3, which are converted into input voltages by the reference arrays 1001 and 1002 to be supplied to the word lines WL0, WL1, WL2, and WL3) by the weights stored in the memory array 1003, and then adds all the results (memory cell currents) to produce an output on the corresponding bit lines (BL0-BLN), which will be the input of the next layer or the input of the final layer. By performing multiplication and addition functions, the memory array 1003 eliminates the need for separate multiplication logic circuits and addition logic circuits, and is also highly power-efficient. Here, the voltage inputs are provided on the word lines WL0, WL1, WL2, and WL3, and the outputs appear on the corresponding bit lines BL0-BLN during the read (inference) operation. The current placed on each of the bit lines BL0-BLN performs a summing function of the currents from all of the nonvolatile memory cells connected to that particular bit line.

[0078] Table 5 depicts operating voltages and currents for the VMM array 1000. The columns in the table indicate the voltages placed on the word line for a selected cell, the word line for an unselected cell, the bit line for a selected cell, the bit line for an unselected cell, the source line for a selected cell, and the source line for an unselected cell. The rows indicate read, erase, and program operations.

[0079] Table 5: Fig.10 Operation of VMM Array 1000 :

[0080] WL WL-Not selected BL BL-Not selected SL SL-Not selected Read 1V-3.5V -0.5V / 0V 0.6V-2V(Ineuron) 0.6V-2V / 0V 0V 0V Erase About 5V-13V 0V 0V 0V 0V 0V programming 1V-2V -0.5V / 0V 0.1uA-3uA Vinh - 2.5V 4V-10V 0V-1V / FLT

[0081] Fig.11 A neuron VMM array 1100 is depicted, which is particularly suitable for the memory cell 210 shown in FIG. 2 and serves as a synapse and component of a neuron between an input layer and a next layer. The VMM array 1100 includes a memory array 1103 of nonvolatile memory cells, a reference array 1101 of a first nonvolatile reference memory cell, and a reference array 1102 of a second nonvolatile reference memory cell. The reference arrays 1101 and 1102 extend in the row direction of the VMM array 1100. The VMM array is similar to the VMM 1000, except that in the VMM array 1100, the word lines extend in the vertical direction. Here, the inputs are set on the word lines (WLA0, WLB0, WLA1, WLB2, WLA2, WLB2, WLA3, WLB3), and the outputs appear on the source lines (SL0, SL1) during a read operation. The current placed on each source line performs a summing function of all currents from the memory cells connected to that particular source line.

[0082] Table 6 depicts operating voltages and currents for the VMM array 1100. The columns in the table indicate the voltages placed on the word line for a selected cell, the word line for an unselected cell, the bit line for a selected cell, the bit line for an unselected cell, the source line for a selected cell, and the source line for an unselected cell. The rows indicate read, erase, and program operations.

[0083] Table 6: Fig.11 Operation of the VMM array 1100

[0084]

[0085] Fig.12 A neuron VMM array 1200 is depicted, which is particularly suitable for the memory cell 310 shown in FIG. 3 and is used as a synapse and component of a neuron between an input layer and a next layer. The VMM array 1200 includes a memory array 1203 of nonvolatile memory cells, a reference array 1201 of a first nonvolatile reference memory cell, and a reference array 1202 of a second nonvolatile reference memory cell. The reference arrays 1201 and 1202 are used to convert the current input flowing into the terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs CG0, CG1, CG2, and CG3. In practice, the first nonvolatile reference memory cell and the second nonvolatile reference memory cell are diode-connected through a multiplexer 1212 (only partially shown), wherein the current input flows into them through BLR0, BLR1, BLR2, and BLR3. Multiplexers 1212 each include a respective multiplexer 1205 and cascode transistor 1204 to ensure a constant voltage on a bit line (such as BLR0) of each of the first and second nonvolatile reference memory cells during a read operation. The reference cells are tuned to a target reference level.

[0086] The memory array 1203 serves two purposes. First, it stores weights to be used by the VMM array 1200. Second, the memory array 1203 effectively multiplies the inputs (current inputs provided to terminals BLR0, BLR1, BLR2, and BLR3, which are converted by reference arrays 1201 and 1202 into input voltages to be provided to the control gates (CG0, CG1, CG2, and CG3)) by the weights stored in the memory array, and then adds all the results (cell currents) to produce an output, which appears in BL0-BLN and will be the input to the next layer or the input to the final layer. By performing multiplication and addition functions, the memory array eliminates the need for separate multiplication and addition logic circuits and is also highly power efficient. Here, the inputs are provided on the control gate lines (CG0, CG1, CG2, and CG3), and the outputs appear on the bit lines (BL0-BLN) during a read operation. The current placed on each bit line performs a summing function of all currents from the memory cells connected to that particular bit line.

[0087] The VMM array 1200 implements unidirectional tuning of the non-volatile memory cells in the memory array 1203. That is, each non-volatile memory cell is erased and then partially programmed until the desired charge on the floating gate is reached. If too much charge is placed on the floating gate (causing an erroneous value to be stored in the cell), the cell is erased and the sequence of partial programming operations restarts. As shown, two rows sharing the same erase gate (such as EG0 or EG1) are erased together (which is called a page erase), and thereafter, each cell is partially programmed until the desired charge on the floating gate is reached.

[0088] Table 7 depicts operating voltages and currents for the VMM array 1200. The columns in the table indicate the voltages placed on the word line for a selected cell, the word line for an unselected cell, the bit line for a selected cell, the bit line for an unselected cell, the control gate for a selected cell, the control gate for an unselected cell in the same sector as the selected cell, the control gate for an unselected cell in a different sector than the selected cell, the erase gate for a selected cell, the erase gate for an unselected cell, the source line for a selected cell, and the source line for an unselected cell. The rows indicate read, erase, and program operations.

[0089] Table 7: Fig.12 Operation of the VMM array 1200

[0090]

[0091] Fig.13A neuron VMM array 1300 is depicted that is particularly suitable for use with the memory cell 310 shown in FIG. 3 and serves as a synapse and component of a neuron between an input layer and a next layer. The VMM array 1300 includes a memory array 1303 of nonvolatile memory cells, a reference array 1301 of a first nonvolatile reference memory cell, and a reference array 1302 of a second nonvolatile reference memory cell. The EG lines EGR0, EG0, EG1, and EGR1 extend vertically, while the CG lines CG0, CG1, CG2, and CG3 and the SL lines WL0, WL1, WL2, and WL3 extend horizontally. The VMM array 1300 is similar to the VMM array 1400, except that the VMM array 1300 implements bidirectional tuning, where each individual cell can be fully erased, partially programmed, and partially erased as needed to achieve a desired amount of charge on the floating gate due to the use of separate EG lines. As shown, reference arrays 1301 and 1302 convert input currents in terminals BLR0, BLR1, BLR2, and BLR3 into control gate voltages CG0, CG1, CG2, and CG3 to be applied to the memory cells in the row direction (through the action of diode-connected reference cells via multiplexer 1314). The current outputs (neurons) are in bit lines BL0-BLN, where each bit line sums all currents from the non-volatile memory cells connected to that particular bit line.

[0092] Table 8 depicts operating voltages and currents for the VMM array 1300. The columns in the table indicate the voltages placed on the word line for a selected cell, the word line for an unselected cell, the bit line for a selected cell, the bit line for an unselected cell, the control gate for a selected cell, the control gate for an unselected cell in the same sector as the selected cell, the control gate for an unselected cell in a different sector than the selected cell, the erase gate for a selected cell, the erase gate for an unselected cell, the source line for a selected cell, and the source line for an unselected cell. The rows indicate read, erase, and program operations.

[0093] Table 8: Fig.13 Operation of the VMM array 1300

[0094]

[0095] Fig. 22 A neuron VMM array 2200 is depicted, which is particularly suitable for the memory unit 210 shown in FIG. 2 and is used as a synapse and component of neurons between an input layer and the next layer. In the VMM array 2200, inputs INPUT0, ..., INPUT N On bit lines BL0, BL NThe signals are received on the source lines SL0, SL1, SL2 and SL3, and outputs OUTPUT1, OUTPUT2, OUTPUT3 and OUTPUT4 are generated on the source lines SL0, SL1, SL2 and SL3, respectively.

[0096] Fig.23 A neuron VMM array 2300 is depicted that is particularly suitable for use with the memory cell 210 shown in FIG. 2 and serves as a synapse and component of neurons between an input layer and the next layer. In this example, inputs INPUT0, INPUT1, INPUT2, and INPUT3 are received on source lines SL0, SL1, SL2, and SL3, respectively, and outputs OUTPUT0, ..., OUTPUT N On the bit lines BL0, BL N Generate on.

[0097] Fig.24 A neuron VMM array 2400 is depicted, which is particularly suitable for the memory unit 210 shown in Figure 2 and is used as a synapse and component of neurons between the input layer and the next layer. In this example, input INPUT0, ..., INPUT M On word lines WL0, ......, WL M is received and output OUTPUT0, ..., OUTPUT N On the bit lines BL0, BL N Generate on.

[0098] Fig.25 Depicted is a neuron VMM array 2500 that is particularly suitable for use with the memory cell 310 shown in FIG. 3 and serves as a synapse and component of neurons between an input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M On word lines WL0, ..., WL M is received and output OUTPUT0, ..., OUTPUT N On the bit lines BL0, BL N Generate on.

[0099] Fig.26 Depicted is a neuron VMM array 2600 that is particularly suitable for use with the memory cell 410 shown in FIG. 4 and serves as a synapse and component of neurons between an input layer and the next layer. In this example, inputs INPUT0, ..., INPUT n On the vertical control gate lines CG0, CG N The signals are received on the source lines SL0 and SL1, and outputs OUTPUT1 and OUTPUT2 are generated on the source lines SL0 and SL1.

[0100] Fig. 27 Depicted is a neuron VMM array 2700 that is particularly suitable for use with the memory cell 410 shown in FIG. 4 and serves as a synapse and component of neurons between an input layer and the next layer. In this example, inputs INPUT0, ..., INPUT N are received at the gates of bit line control gates 2701-1, 2701-2, ..., 2701-(N-1), and 2701-N, which are respectively coupled to bit lines BL0, ..., BL N Example outputs OUTPUT1 and OUTPUT2 are generated on source lines SL0 and SL1.

[0101] Fig.28 Depicted is a neuron VMM array 2800 that is particularly suitable for use with memory cells 310 shown in FIG. 3 , memory cells 510 shown in FIG. 5 , and Figure 7 The memory unit 710 shown is used as a synapse and component of the neurons between the input layer and the next layer. In this example, the inputs INPUT0, ..., INPUT M On word lines WL0, ..., WL M is received and output OUTPUT0, ..., OUTPUT N On bit lines BL0, BL N Generate on.

[0102] Fig.29 Depicted is a neuron VMM array 2900 that is particularly suitable for use with memory cells 310 shown in FIG. 3 , memory cells 510 shown in FIG. 5 , and Figure 7 The memory unit 710 shown is used as a synapse and component of the neurons between the input layer and the next layer. In this example, the inputs INPUT0, ..., INPUT M On the control gate lines CG0, CG M OUTPUT0, OUTPUT1, OUTPUT2, OUTPUT3, OUTPUT4 N On the vertical source lines SL0, . . . , SL N Each source line SL i The source line coupled to all memory cells in column i.

[0103] Fig.30 Depicted is a neuron VMM array 3000, which is particularly suitable for use with memory cells 310 shown in FIG. 3, memory cells 510 shown in FIG. 5, and Figure 7The memory unit 710 shown is used as a synapse and component of the neurons between the input layer and the next layer. In this example, the inputs INPUT0, ..., INPUT M On the control gate lines CG0, CG M OUTPUT0, OUTPUT1, OUTPUT2, OUTPUT3, OUTPUT4 N On the vertical bit lines BL0, BL N On the generation, each bit line BL i The bit line coupled to all memory cells in column i.

[0104] Long Short-Term Memory

[0105] Prior art includes a concept called long short-term memory (LSTM). LSTM cells are commonly used in neural networks. LSTM allows a neural network to remember information for a predetermined arbitrary time interval and use the information in subsequent operations. A conventional LSTM cell includes a cell, an input gate, an output gate, and a forget gate. The three gates regulate the flow of information into and out of the cell and the time interval at which information is remembered in the LSTM. VMMs are particularly useful in LSTM cells.

[0106] FIG. 14 depicts an example LSTM 1400. The LSTM 1400 in this example includes units 1401, 1402, 1403, and 1404. Unit 1401 receives an input vector x0 and generates an output vector h0 and a unit state vector c0. Unit 1402 receives an input vector x1, an output vector (hidden state) h0 from unit 1401, and a unit state c0 from unit 1401, and generates an output vector h1 and a unit state vector c1. Unit 1403 receives an input vector x2, an output vector (hidden state) h1 from unit 1402, and a unit state c1 from unit 1402, and generates an output vector h2 and a unit state vector c2. Unit 1404 receives an input vector x3, an output vector (hidden state) h2 from unit 1403, and a unit state c2 from unit 1403, and generates an output vector h3. Additional units may be used, and an LSTM with four units is merely an example.

[0107] Figure 15 depicts an example implementation of an LSTM cell 1500 that may be used for cells 1401, 1402, 1403, and 1404 in Figure 14. LSTM cell 1500 receives an input vector x(t), a cell state vector c(t-1) from a previous cell, and an output vector h(t-1) from a previous cell, and generates a cell state vector c(t) and an output vector h(t).

[0108] LSTM cell 1500 includes sigmoid function devices 1501, 1502, and 1503, each of which applies a number between 0 and 1 to control how much of each component in the input vector is allowed to pass through to the output vector. LSTM cell 1500 also includes tanh devices 1504 and 1505 for applying a hyperbolic tangent function to the input vector, multiplier devices 1506, 1507, and 1508 for multiplying two vectors together, and an addition device 1509 for adding two vectors together. The output vector h(t) can be provided to the next LSTM cell in the system, or it can be accessed for other purposes.

[0109] Fig.16 LSTM cell 1600 is depicted, which is an example of a specific implementation of LSTM cell 1500. For the convenience of the reader, the same numbering as LSTM cell 1500 is used in LSTM cell 1600. Sigmoid function devices 1501, 1502 and 1503 and tanh device 1504 each include multiple VMM arrays 1601 and activation function blocks 1602. Therefore, it can be seen that VMM arrays are particularly useful in LSTM cells used in certain neural network systems. Multiplier devices 1506, 1507 and 1508 and addition device 1509 are implemented digitally or in analog. Activation function block 1602 can be implemented digitally or in analog.

[0110] An alternative form of LSTM cell 1600 (and another example of a specific implementation of LSTM cell 1500) is Fig.17 In Fig.17 , the sigmoid function devices 1501, 1502 and 1503 and the tanh device 1504 share the same physical hardware (VMM array 1701 and activation function block 1702) in a time-division multiplexing manner. The LSTM unit 1700 also includes a multiplier device 1703 for multiplying two vectors together, an addition device 1708 for adding two vectors together, a tanh device 1505 (which includes an activation function block 1702), a register 1707 for storing the value i(t) when the value i(t) is output from the sigmoid function block 1702, a register 1704 for storing the value f(t)*c(t-1) when the value is output from the multiplier device 1703 through the multiplexer 1710, a register 1705 for storing the value i(t)*u(t) when the value is output from the multiplier device 1703 through the multiplexer 1710, and a register 1706 for storing the value o(t)*c~(t) when the value is output from the multiplier device 1703 through the multiplexer 1710, and a multiplexer 1709.

[0111] LSTM cell 1600 includes multiple sets of VMM arrays 1601 and corresponding activation function blocks 1602, while LSTM cell 1700 includes only one set of VMM arrays 1701 and activation function blocks 1702, which are used to represent multiple layers in the example of LSTM cell 1700. LSTM cell 1700 will require less space than LSTM 1600 because LSTM cell 1700 only requires 1 / 4 of its space for VMM and activation function blocks compared to LSTM cell 1600.

[0112] It is also understood that the LSTM cell will typically include multiple VMM arrays, each of which requires functionality provided by certain circuit blocks outside the VMM array (such as summers and activation function blocks and high voltage generation blocks). Providing a separate circuit block for each VMM array would require a large amount of space within the semiconductor device and would be inefficient to a certain extent. Therefore, the examples described below reduce the circuitry required outside the VMM array itself.

[0113] Gate Controlled Recursive Unit

[0114] The simulated VMM implementation can be used for a Gated Recurrent Unit (GRU) system. GRU is a gate mechanism in a recurrent neural network. GRU is similar to LSTM, except that a GRU cell generally contains fewer components than an LSTM cell.

[0115] FIG. 18 depicts an example GRU 1800. The GRU 1800 in this example includes units 1801, 1802, 1803, and 1804. Unit 1801 receives an input vector x0 and generates an output vector h0. Unit 1802 receives an input vector x1, an output vector h0 from unit 1801, and generates an output vector h1. Unit 1803 receives an input vector x2 and an output vector (hidden state) h1 from unit 1802 and generates an output vector h2. Unit 1804 receives an input vector x3 and an output vector (hidden state) h2 from unit 1803 and generates an output vector h3. Additional units may be used, and a GRU with four units is merely an example.

[0116] FIG. 19 depicts an example implementation of a GRU cell 1900 that may be used for cells 1801, 1802, 1803, and 1804 of FIG. 18. GRU cell 1900 receives an input vector x(t) and an output vector h(t-1) from a previous GRU cell, and generates an output vector h(t). GRU cell 1900 includes sigmoid function devices 1901 and 1902, each of which applies a number between 0 and 1 to components from the output vector h(t-1) and the input vector x(t). GRU cell 1900 also includes a tanh device 1903 for applying a hyperbolic tangent function to the input vector, a plurality of multiplier devices 1904, 1905, and 1906 for multiplying two vectors together, an addition device 1907 for adding two vectors together, and a complement device 1908 for subtracting the input from 1 to generate an output.

[0117] Fig. 20 A GRU unit 2000 is depicted, which is an example of a specific implementation of the GRU unit 1900. For the convenience of the reader, the same numbering is used in the GRU unit 2000 as in the GRU unit 1900. Fig. 20 As can be seen in FIG. 1 , sigmoid function devices 1901 and 1902 and tanh device 1903 each include multiple VMM arrays 2001 and activation function blocks 2002. Therefore, it can be seen that the VMM array is particularly useful in the GRU unit used in some neural network systems. Multiplier devices 1904, 1905 and 1906, addition device 1907 and complementary device 1908 are implemented in digital or analog form. Activation function block 2002 can be implemented in digital or analog form.

[0118] An alternative form of GRU unit 2000 (and another example of a specific implementation of GRU unit 1900) is Fig.21 In Fig.21 In , the GRU unit 2100 utilizes a VMM array 2101 and an activation function block 2102 which, when configured as a sigmoid function, applies a number between 0 and 1 to control how much of each component in the input vector is allowed to pass through to the output vector. Fig.21, the sigmoid function devices 1901 and 1902 and the tanh device 1903 share the same physical hardware (VMM array 2101 and activation function block 2102) in a time-division multiplexing manner. The GRU unit 2100 also includes a multiplier device 2103 for multiplying two vectors together, an addition device 2105 for adding two vectors together, a complementary device 2109 for subtracting an input from 1 to generate an output, a multiplexer 2104, a register 2106 for holding the value h(t-1)*r(t) when it is output from the multiplier device 2103 through the multiplexer 2104, a register 2107 for holding the value h(t-1)*z(t) when it is output from the multiplier device 2103 through the multiplexer 2104, and a register 2108 for holding the value h^(t)*(1-z(t)) when it is output from the multiplier device 2103 through the multiplexer 2104.

[0119] The GRU unit 2000 includes multiple sets of VMM arrays 2001 and activation function blocks 2002, while the GRU unit 2100 includes only one set of VMM arrays 2101 and activation function blocks 2102, which are used to represent multiple layers in the example of the GRU unit 2100. The GRU unit 2100 will require less space than the GRU unit 2000 because the GRU unit 2100 only requires 1 / 3 of its space for the VMM and activation function blocks compared to the GRU unit 2000.

[0120] It will also be appreciated that a GRU system will typically include multiple VMM arrays, each of which requires functionality provided by certain circuit blocks outside the VMM array (such as summers and activation function blocks and high voltage generation blocks). Providing a separate circuit block for each VMM array would require a significant amount of space within the semiconductor device and would be somewhat inefficient. Therefore, the examples described below reduce the circuitry required outside the VMM array itself.

[0121] The inputs to the VMM array can be analog levels, binary levels, pulses, time-modulated pulses, or digital bits (in which case a DAC is required to convert the digital bits to the appropriate input analog levels), and the outputs can be analog levels, binary levels, timed pulses, pulses, or digital bits (in which case an output ADC is required to convert the output analog levels to digital bits).

[0122] In general, for each memory cell in the VMM array, each weight W can be implemented by a single memory cell or by a differential cell or by two hybrid memory cells (average of 2 cells). In the case of a differential cell, two memory cells are required to implement the weight W as a differential weight (W=W+-W-). In two hybrid memory cells, two memory cells are required to implement the weight W as the average of the two cells.

[0123] Fig.31 A VMM system 3100 is depicted. In some examples, the weights W stored in the VMM array are stored as a differential pair W+ (positive weight) and W- (negative weight), where W=(W+)-(W-). In the VMM system 3100, half of the bit lines are designated as W+ lines, i.e., bit lines connected to memory cells that will store positive weights W+, and the other half of the bit lines are designated as W- lines, i.e., bit lines connected to memory cells that implement negative weights W-. The W- lines are interspersed between the W+ lines in an alternating manner. The subtraction operation is performed by a summing circuit (such as summing circuits 3101 and 3102), which receives current from the W+ line and the W- line. The output of the W+ line and the output of the W- are combined together to effectively give W=W+-W- for each (W+, W-) cell pair of all (W+, W-) line pairs. Although described above with respect to W- lines interspersed between W+ lines in an alternating manner, in other examples, the W+ lines and W- lines may be arbitrarily located anywhere in the array.

[0124] Fig.32 Another example is depicted. In VMM system 3210 , positive weights W+ are implemented in a first array 3211 , and negative weights W− are implemented in a second array 3212 , which is separate from the first array, and the resulting weights are appropriately combined together by summing circuit 3213 .

[0125] Fig.33A VMM system 3300 is depicted, in which the weights W stored in the VMM array are stored as a differential pair W+ (positive weight) and W- (negative weight), where W=(W+)-(W-). The VMM system 3300 includes an array 3301 and an array 3302. Half of the bit lines in each of the arrays 3301 and 3302 are designated as W+ lines, i.e., bit lines connected to memory cells that will store positive weights W+, and the other half of the bit lines in each of the arrays 3301 and 3302 are designated as W- lines, i.e., bit lines connected to memory cells that implement negative weights W-. The W- lines are interspersed between the W+ lines in an alternating manner. The subtraction operation is performed by a summing circuit (such as summing circuits 3303, 3304, 3305, and 3306), which receives current from the W+ lines and the W- lines. The outputs of the W+ lines and the outputs of the W- lines from each array 3301, 3302 are combined together to effectively give W=W+-W- for each (W+, W-) cell pair for all (W+, W-) line pairs. In addition, the W values ​​from each array 3301 and 3302 can be further combined by summing circuits 3307 and 3308 so that each W value is the result of subtracting the W value from array 3301 from the W value from array 3302, which means that the final result from summing circuits 3307 and 3308 is a difference of two difference values.

[0126] Each nonvolatile memory cell used in an analog neural memory system is erased and programmed to hold a very specific and precise amount of charge (i.e., number of electrons) in the floating gate. For example, each floating gate should hold one of N different values, where N is the number of different weights that can be indicated by each cell. Examples of N include 16, 32, 64, 128, and 256.

[0127] It is desirable to reduce the waiting time in programming operations to increase the overall operating speed of artificial neural networks. Summary of the invention

[0128] A number of examples are disclosed for programming multiple rows in an array in an artificial neural network as part of a single programming operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0129] FIG. 1 is a diagram illustrating an example of an artificial neural network.

[0130] FIG. 2 depicts a prior art split-gate flash memory cell.

[0131] FIG. 3 depicts another prior art split gate flash memory cell.

[0132] FIG. 4 depicts another prior art split gate flash memory cell.

[0133] FIG. 5 depicts another prior art split gate flash memory cell.

[0134] Figure 6 Schematic diagram illustrating different levels of an exemplary artificial neural network utilizing one or more non-volatile memory arrays.

[0135] Figure 7 FIG. 1 is a block diagram illustrating a VMM system.

[0136] Figure 8 is a block diagram illustrating an example artificial neural network utilizing one or more VMM systems.

[0137] Fig. 9 Another example of a VMM system is depicted.

[0138] Fig.10 Another example of a VMM system is depicted.

[0139] Fig.11 Another example of a VMM system is depicted.

[0140] Fig.12 Another example of a VMM system is depicted.

[0141] Fig.13 Another example of a VMM system is depicted.

[0142] FIG. 14 depicts a prior art long short term memory system.

[0143] FIG. 15 depicts an example cell for use in a long short term memory system.

[0144] Fig.16 An example implementation of the unit of FIG. 15 is depicted.

[0145] Fig.17 Another example implementation of the unit of FIG. 15 is depicted.

[0146] FIG. 18 depicts a prior art gate-controlled recursive cell system.

[0147] FIG. 19 depicts an example cell for use in a gate-controlled recursive cell system.

[0148] Fig. 20 An example implementation of the unit of FIG. 19 is depicted.

[0149] Fig.21 Another example implementation of the unit of FIG. 19 is depicted.

[0150] Fig. 22 Another example of a VMM system is depicted.

[0151] Fig.23Another example of a VMM system is depicted.

[0152] Fig.24 Another example of a VMM system is depicted.

[0153] Fig.25 Another example of a VMM system is depicted.

[0154] Fig.26 Another example of a VMM system is depicted.

[0155] Fig. 27 Another example of a VMM system is depicted.

[0156] Fig.28 Another example of a VMM system is depicted.

[0157] Fig.29 Another example of a VMM system is depicted.

[0158] Fig.30 Another example of a VMM system is depicted.

[0159] Fig.31 Another example of a VMM system is depicted.

[0160] Fig.32 Another example of a VMM system is depicted.

[0161] Fig.33 Another example of a VMM system is depicted.

[0162] Fig.34 Another example of a VMM system is depicted.

[0163] FIG. 35 depicts an example of a prior art programming waveform.

[0164] Fig.36A , Fig.36B , Fig.36C and Fig.36D Example programming waveforms for consecutive rows are depicted.

[0165] Fig.37 A block diagram of a VMM system for sequential row programming is depicted.

[0166] Fig.38 Depicted is the diagonal line control circuit.

[0167] Fig.39 Depicted is the diagonal line control circuit.

[0168] Fig.40 Depicted is the diagonal line control circuit.

[0169] Fig.41 Depicted is the diagonal line control circuit.

[0170] Fig.42 A high voltage level shifter and inverter are depicted.

[0171] Fig.43 A ramp control circuit and its exemplary waveforms are depicted.

[0172] Fig.44 A ramp-down control circuit and its exemplary waveforms are depicted. DETAILED DESCRIPTION

[0173] VMM system architecture

[0174] Fig.34 Depicted is a block diagram of a VMM system 3400. The VMM system 3400 includes a VMM array 3401, a row decoder 3402, a high voltage decoder 3403, a column decoder 3404, a bit line driver 3405, an input circuit 3406, an output circuit 3407, a control logic component 3408, and a bias generator 3409. The VMM system 3400 also includes a high voltage generation block 3410, which includes a charge pump 3411, a charge pump regulator 3412, and a high voltage level generator 3413. The VMM system 3400 also includes a (program / erase or weight tuning) algorithm controller 3414, an analog circuit 3415, a control engine 3416 (which may include special functions such as arithmetic functions, activation functions, embedded microcontroller logic, but is not limited to such), a test control logic component 3417, and a static random access memory (SRAM) block 3418 to store intermediate data such as for input circuits (e.g., activation data) or output circuits (neuron output data) or data for programming (such as input data for an entire row or multiple rows).

[0175] The input circuit 3406 may include various circuits such as a DAC (digital-to-analog converter), a DPC (digital-to-pulse converter, digital-to-time modulated pulse converter), an AAC (analog-to-analog converter, such as a current-to-voltage converter, a logarithmic converter), a PAC (pulse-to-analog level converter), or any other type of converter. The input circuit 3406 may implement one or more of normalization, linear or nonlinear up / down scaling functions, or arithmetic functions. The input circuit 3406 may implement a temperature compensation function for the input level. The input circuit 3406 may implement an activation function such as a ReLU or a sigmoid.

[0176] Output circuit 3407 may include circuits such as an ADC (analog-to-digital converter for converting neuron analog outputs into digital bits), an AAC (analog-to-analog converter, such as a current-to-voltage converter, a logarithmic converter), an APC (analog-to-pulse converter, analog-to-time modulated pulse converter), or any other type of converter. Output circuit 3407 may implement an activation function, such as a rectified linear activation function (ReLU) or a sigmoid. Output circuit 3407 may implement one or more of statistical normalization, regularization, up / down scaling / gain functions, statistical rounding, or arithmetic functions (e.g., addition, subtraction, division, multiplication, shift, logarithm) for the neuron output. Output circuit 3407 may implement a temperature compensation function for the neuron output or array output (such as a bit line output) to keep the power consumption of the array approximately constant, or to improve the accuracy of the array (neuron) output, such as by keeping the IV slope approximately the same.

[0177] FIG35 depicts a timing waveform for a prior art programming operation 3500. Shown here is a timing waveform for HVSUP (by Fig.34 3410 (the high voltage generation block includes a charge pump 3411) in the high voltage supply generated, and the HVSUP is particularly generated by the high voltage level generator 3413 and provided to the control gate line, source line and / or bit line of the selected cell during the programming operation. Specifically, Figure 35 depicts CG (the voltage applied to the control gate line coupled to the selected cell during the programming operation), SL (the voltage applied to the source line coupled to the selected cell during the programming operation), EG (the voltage applied to the erase gate line coupled to the selected cell during the programming operation) and IPROG (generated by the bias generator 3409 or the analog circuit 3415 and applied to the bit line coupled to the selected cell during the programming operation). For example, these voltages are selected according to Tables 1 to 8 previously described for the programming operation, but are not limited thereto. It can be seen that due to the high voltage of its peak value and the actions involved in generating the voltage (such as capacitance), there are significant ramp rise times t1 and ramp fall times t2 for HVSUP. For example, the ramp up time is affected by the charge pumping action of the charge pump 3411 which takes time. For example, the ramp down time is affected by the time required to discharge the high voltage for all devices coupled to the high voltage, including large capacitive loads which results in slow ramp down times. There is a shorter ramp up time t3 for the CG and a shorter ramp down time t4 for the CG.

[0178] Typical values ​​for t1, t2, t3, t4, and t5 (described below) are 20μs-60μs, 5μs-20μs, 0.1μs-1μs, 0.1μs-1μs, and 0.1μs, respectively. In contrast, once the relevant voltage is in place, the time required to program a single cell is only 1μs. Therefore, it is common in the prior art to program an entire row of cells in a single high voltage cycle of HVSUP, so that programming for the entire row only calls a single ramp-up cycle and a single ramp-down cycle of HVSUP. For example, a row can contain 2048 cells, and each word can contain 128 bits, which means that each row contains 16 words. Therefore, in the example of Figure 35, Word0, ..., Word15 (a total of 16 words) are programmed during a single HVSUP cycle, so that programming for each group of 16 words causes a single ramp-up of t1 and a ramp-down of t2. An additional delay of t5 is caused between different rows of programming cells.

[0179] Fig.36A A timing waveform is depicted for a programming operation 3600. Again, waveforms for HVSUP, CG, SL, EG, and IPROG are shown. Here, K consecutive rows of cells are programmed for each HVSUP cycle, where K>1. For example, K=2, K=3, or K=4.

[0180] First, a ramp-up period of t1 is caused, such as due to the charge pumping action of the charge pump 3411 and due to charging all capacitive loads of all devices coupled to the high voltage generation block 3410. After the high voltage (HVSUP) is stabilized, HVSUP is then switched to one or more lines coupled to the array terminals (CG, WL, SL, EG and / or BL). For example, HVSUP may be applied to the CG, SL or EG lines, and other voltages (lower than HVSUP) may be applied to the remaining lines according to Tables 1 to 8 above. The high voltage applied to CG, SL, EG and BL may optionally be four different voltages. The low voltage applied to CG, SL, EG and BL may optionally be four different voltages, the same voltage (such as ground) or any variation therebetween. Second, taking 16 words of a row as an example, a programming current (IPROG) for tPROG (e.g., 0.5μs-1μs) is enabled for each word. Instead of ramping HVSUP down after each row of programming, HVSUP remains high for the next row of programming, and instead, the circuit disconnects and then turns on CG, SL, and EG. Disconnecting and then turning on CG, SL, and EG requires a time period equal to t4+t3+t5, where t4 is the slowest required ramp-down time of CG, SL, and EG, t3 is the slowest ramp-up period of CG, SL, and EG, and t5 provides a gap to ensure that the ramp-up circuit does not mistakenly start ramping up CG, SL, and EG before it has completed its ramp-down. It is worth noting that t3 is much smaller than t1 and t4 is much smaller than t2. Third, the second row of cells is programmed without ramping down HVSUP. Fourth, the ramp-down period of t2 is caused. For example, typical quantities are t1~10μs-60μs, t3~0.1μs-1μs, t4~0.1μs-1μs, t5<0.1μs, t2~2=10μs. Using this same sequence, K rows are programmed for each constant high period of HVSUP, where K > 1. In the example shown, the ramp up and ramp down slopes of CG, SL, and EG are steeper than the ramp up and ramp down of HVSUP, respectively.

[0181] Fig.36B Depicts a timing waveform for a programming operation 3620, which is similar to Fig.36A The programming operation 3600 in FIG. 1 is different in that there is no t5, which means there is no delay between the end of the ramp down period of t4 and the end of the ramp up period of t3 and the CG signal is switched from the first CG line for the first row to the second CG line for the second row without delay. This reduces the programming time compared to the programming operation 3600.

[0182] Fig.36C Depicts a timing waveform for a programming operation 3640, which is similar to Fig.36A 3600, except that t4 overlaps with t3, which means that the CG signal is switched from the first CG line for the first row to the second CG line for the second row at the same time that the ramp-down cycle of t4 occurs. This reduces programming time compared to programming operation 3620, although there is an increased risk that the ramp-down of CG does not progress to the point where it will be considered "low" before it ramps up again.

[0183] Fig.36D Depicted is a timing waveform for a programming operation 3660, which is similar to Fig.36A Programming operation 3600 is similar to programming operation 3600, except that t3 starts before t4 ends, which means that the CG signal applied to the second CG line of the second row ramps up before or at the same time as the CG signal applied to the first CG line of the first row ramps down. This reduces programming time compared to programming operation 3640, at the expense of not having the option of using a change in CG state to trigger any action.

[0184] Thus, programming operation 3600, programming operation 3620, programming operation 3640, and programming operation 3660 are faster than programming operation 3500 for programming two or more consecutive rows. The amount can be significant, on the order of a 3x to 10x improvement in programming time.

[0185] Figures 37 to 41 Circuits for implementing programming operation 3600 , programming operation 3620 , programming operation 3640 , and programming operation 3660 are depicted.

[0186] Fig.37 A VMM system 3700 is depicted, which includes Fig.34 36 , and the high voltage pre-decoder receives HVSUP as a voltage input.

[0187] like FIG. 36A to FIG. 36D The ramp up and ramp down functions shown for HVSUP may be implemented in the HV generation block 3410 , the HV pre-decoder 3701 , or the row decoder 3402 . Figures 38 to 41 Depicted is a circuit that can be used to implement the ramp up and ramp down functions.

[0188] Fig.38Ramp control circuit 3800-i, bias circuit 3810, bias circuit 3820, and decoder 3830 are depicted, where i ranges from 0 to N, where there are N+1 rows of cells in array 3401. Ramp control circuit 3800-i includes PMOS transistor 3801 and NMOS transistor 3802, and can cause signal Vout (e.g., CG, EG, SL array terminals, pre-decoded high voltage signal) to ramp up or ramp down from ground toward HVSUP. A first terminal of PMOS transistor 3801 receives HVSUP, a gate of PMOS transistor 3801 receives a first control signal PBIAS[N:0] (which is optionally a current control signal), and a second terminal of PMOS transistor 3801 is a Vout node. A first terminal of the NMOS transistor 3802 is coupled to the Vout node, a gate of the NMOS transistor 3802 receives a second control signal NBIAS[N:0] (which is optionally a current control signal), and a second terminal of the NMOS transistor 3802 is coupled to ground.

[0189] An instantiation of ramp control circuit 3800-i is coupled to each control gate line, source line, and erase gate line to perform on and off operations of programming operation 3600, programming operation 3620, programming operation 3640, and programming operation 3660. In the example shown, the suffix [N:0] indicates that there are N+1 different instantiations. The instantiations of ramp control circuit 3800 are coupled together in a decoded current mirror configuration.

[0190] Decoder 3830 receives a row address and generates an enable signal EN[N:0], a complement of an enable signal ENB[N:0], such that N+1 EN signals and N+1 ENB signals are generated, one for each of the instantiations of the ramp control circuit 3800 .

[0191] Bias circuit 3810 includes primary circuit 3815 and N+1 instantiations of subcircuit 3816-i, where i ranges from 0 to N. Primary circuit 3815 includes current source 3811 and NMOS transistor 3812 and generates current i to be mirrored to generate NBIAS[N:0]. N Each sub-circuit 3816 - i includes a switch 3813 controlled by EN[N:0] from the decoder 3830 and a switch 3814 controlled by ENB[N:0] from the decoder 3830 .

[0192] Bias circuit 3820 includes primary circuit 3825 and N+1 instantiations of sub-circuit 3826-i, where i ranges from 0 to N. Primary circuit 3825 includes current source 3821 and PMOS transistor 3822 and generates current i to be mirrored to generate PBIAS[N:0].P Each sub-circuit 3826 - i includes a switch 3823 controlled by EN[N:0] from a decoder 3830 and a switch 3824 controlled by ENB[N:0] from a decoder 3830 .

[0193] In the ramp control circuit 3800-i, a high voltage on NBIAS[N:0] causes the ramp to fall, and a low voltage on PBIAS[N:0] causes the ramp to rise. When PBIAS is asserted to turn on PMOS transistor 3801 and NBIAS is deasserted, Vout is pulled up to HVSUP, thus performing an on function. When NBIAS is asserted to turn on NMOS transistor 3802 and PBIAS is deasserted, Vout is pulled down to ground, thus performing an off function. The ramp control circuit 3800 is shown here for Vout, which can be used to provide FIG. 36A to FIG. 36D Because current mirrors are used in bias circuit 3810 and bias circuit 3820, all N+1 instantiations receive the same current on PBIAS[N:0] and the same current on NBIAS[N:0] when the row address provided to decoder 3830 enables the corresponding row.

[0194] Fig.39 Ramp control circuit 3900-i is depicted, where i ranges from 0 to N, where there are N+1 rows of cells in array 3401. Ramp control circuit 3900-i includes PMOS transistor 3901 and PMOS transistor 3902 and NMOS transistor 3903 and NMOS transistor 3904. An instantiation of ramp control circuit 3900-i is coupled to each control gate line, source line, and erase gate line to perform on and off operations of programming operation 3600. In the example shown, the suffix [N:0] indicates that there are N+1 different instantiations. A high voltage on NBIAS[N:0] and NCASCODE causes the ramp to drop, and a low voltage on PBIAS[N:0] and PCASCODE causes the ramp to rise.

[0195] The first terminal of the PMOS transistor 3901 receives HVSUP and the gate of the PMOS transistor 3901 receives the first control signal PBIAS[N:0] (which is optionally a current control signal). The first terminal of the PMOS transistor 3902 is coupled to the second terminal of the PMOS transistor 3901, the gate of the PMOS transistor 3902 receives the second control signal PCASCODE, and the second terminal of the PMOS transistor 3902 is coupled to the Vout node (e.g., CG, EG, SL array terminals, pre-decoding high voltage signal). The first terminal of the NMOS transistor 3903 is coupled to the Vout node and the gate of the NMOS transistor 3903 receives the third control signal NCASCODE. The first terminal of the NMOS transistor 3904 is coupled to the second terminal of the NMOS transistor 3903, the gate of the NMOS transistor 3904 receives the fourth control signal NBIAS[N:0] (which is optionally a current control signal), and the second terminal of the NMOS transistor 3904 is coupled to ground.

[0196] PMOS transistor 3902 and NMOS transistor 3903 perform a cascade function to isolate PMOS transistor 3901 and NMOS transistor 3904 from Vout. When PCASCODE and PBIAS for row N are asserted, PMOS transistor 3901 and PMOS transistor 3902 are turned on, and in the case where NCASCODE and NBIAS for row N are deasserted, Vout is pulled up to HVSUP, thereby performing a turn-on function. When NCASCODE and NBIAS for row N are asserted, NMOS transistor 3903 and NMOS transistor 3904 are turned on, and in the case where PCASCODE and PBIAS for row N are deasserted, Vout is pulled down to ground, thereby performing a turn-off function. A ramp control circuit 3900 is shown here for Vout, which can be used to provide FIG. 36A to FIG. 36D Optionally, the PBIAS[N:0] signal for the N+1 instantiations of ramp control circuit 3900-I can be Fig.38 The bias circuit 3820 in FIG. 1 is provided so that all N+1 instantiations receive the same current on PBIAS[N:0], and the NBIAS[N:0] signal for the N+1 instantiations of the ramp control circuit can be provided by Fig.38 The bias circuit 3810 in is provided so that all N+1 instantiations receive the same current on NBIAS[N:0]. Optionally, in these configurations also use Fig.38 Decoder 3830 in provides EN[N:0] and EN[N:B].

[0197] Fig.40Ramp control circuit 4000-i is depicted, where i ranges from 0 to N. Ramp control circuit 4000-i includes PMOS transistors 4001 and 4002, NMOS transistors 4003, and current bias sources 4004 and 4005. Current bias source 4005 includes a first terminal coupled to a high voltage generation block. PMOS transistor 4001 includes a first terminal coupled to a second terminal of current bias source 4005, a second terminal, and a gate for receiving a first control signal PBIAS[N:0] (which is optionally a current control signal). PMOS transistor 4002 includes a first terminal coupled to the second terminal of PMOS transistor 4001, a second terminal coupled to a Vout node (e.g., CG, EG, SL array terminal, pre-decoded high voltage signal), and a gate for receiving a second control signal GP[N:0]. NMOS transistor 4003 includes a first terminal coupled to the Vout node, a second terminal, and a gate for receiving a third control signal NBIAS[N:0] (which is optionally a current control signal). A current bias source 4004 is coupled between the second terminal of NMOS transistor 4004 and ground.

[0198] The instantiation of the ramp control circuit 4000 is coupled to each control gate line, source line and erase gate line to perform the on and off operations of programming operation 3600, programming operation 3620, programming operation 3640 and programming operation 3660. In the example shown, the suffix [N:0] indicates that there are N+1 different instantiations. The high voltage on NBIAS [N:0] causes the ramp to fall, and the low voltage on PBIAS [N:0] and GP [N:0] causes the ramp to rise. When PBIAS and GP for row N are asserted, PMOS transistor 4001 and PMOS transistor 4002 are turned on, and in the case where NBIAS for row N is deasserted, Vout is pulled up to HVSUP, where the slope of the ramp can be controlled by the amount of current provided by the current bias source 4005, thus performing the on function. When NBIAS is asserted, NMOS transistor 4003 turns on, and with PBIAS and GP for row N deasserted, Vout is pulled down to ground, where the slope of the ramp down can be controlled by the amount of current provided by current bias source 4004, thus performing a cutoff function. A ramp control circuit 4000 is shown here for Vout, and Vout can be used FIG. 36A to FIG. 36D CG, SL or EG in.

[0199] Optionally, the PBIAS[N:0] signals for the N+1 instantiations of ramp control circuit 3900-I may be Fig.38The bias circuit 3820 in FIG. 1 is provided so that all N+1 instantiations receive the same current on PBIAS[N:0], and the NBIAS[N:0] signal for the N+1 instantiations of the ramp control circuit can be provided by Fig.38 The bias circuit 3810 in is provided so that all N+1 instantiations receive the same current on NBIAS[N:0]. Optionally, in these configurations also use Fig.38 Decoder 3830 in provides EN[N:0] and EN[N:B].

[0200] Fig.41 Ramp control circuit 4100-i is depicted, where i ranges from 0 to N. Ramp control circuit 4100-I includes PMOS transistor 4101, PMOS transistor 4102, and PMOS transistor 4103; NMOS transistor 4104 and NMOS transistor 4105; and current bias source 4106 and current bias source 4107. An instantiation of ramp control circuit 4100-i is coupled to each control gate line, source line, and erase gate line to perform on and off operations of programming operation 3600.

[0201] The current bias source 4107 includes a first terminal coupled to HVSUP. The PMOS transistor 4101 includes a first terminal coupled to a second terminal of the current bias source 4107, a second terminal, and a gate for receiving a first control signal GPIAS[N:0] (which is optionally a current control signal). The PMOS transistor 4102 includes a first terminal coupled to a second terminal of the PMOS transistor 4101, a second terminal, and a gate for receiving a second control signal GP[N:0]. The PMOS transistor 4103 includes a first terminal coupled to a second terminal of the PMOS transistor 4103, a second terminal coupled to a Vout node, and a gate for receiving a third control signal PCASCODE. The NMOS transistor 4104 includes a first terminal coupled to a Vout node, a second terminal, and a gate for receiving a fourth control signal NCASCODE. The NMOS transistor 4105 includes a first terminal coupled to a second terminal of the NMOS transistor 4104, a second terminal, and a gate for receiving a fifth control signal NBIAS[N:0] (which is optionally a current control signal). The current bias source 4106 is coupled between the second terminal of the NMOS transistor 4105 and ground.

[0202] In the example shown, the suffix [N:0] indicates that there are N+1 different instantiations. A high voltage on NBIAS[N:0] causes the ramp to drop, and a low voltage on PBIAS[N:0] and GP[N:0] causes the ramp to rise. PMOS transistor 4103 and NMOS transistor 4104 perform a CA encoding function. GP[N:0] performs another pre-decoding signal function. When GPIAS, GP, and PCASCODE for row N are turned on, PMOS transistor 4101, PMOS transistor 4102, and PMOS transistor 4103 are turned on, and when NBIAS and NCASCODE for row N are deasserted, Vout is pulled up to CGSUP, where the slope of the ramp can be controlled by the amount of current provided by the current bias source 4107, thereby performing a turn-on function. When NBIAS and NCASCODE are asserted, NMOS transistor 4104 and NMOS transistor 4105 are turned on, and with PBIAS, GP and PCASCODE for row N deasserted, Vout is pulled down to ground where it is accelerated by current bias source 4107, where the slope of the ramp down can be controlled by the amount of current provided by current bias source 4106, thus performing a turn-off function. A ramp control circuit 4100 is shown here for Vout, which can be used to FIG. 36A to FIG. 36D CG, SL or EG in.

[0203] Optionally, the PBIAS[N:0] signals for the N+1 instantiations of ramp control circuit 3900-I may be Fig.38 The bias circuit 3820 in FIG. 1 is provided so that all N+1 instantiations receive the same current on PBIAS[N:0], and the NBIAS[N:0] signal for the N+1 instantiations of the ramp control circuit can be provided by Fig.38 The bias circuit 3810 in is provided so that all N+1 instantiations receive the same current on NBIAS[N:0]. Optionally, in these configurations also use Fig.38 Decoder 3830 in provides EN[N:0] and EN[N:B].

[0204] Fig.42A high voltage level shifter and inverter 4200 is depicted, which includes a current bias source 4201; PMOS transistors 4202 and 4204; NMOS transistors 4203, 4205, 4207, and 4208; and a current bias source 4206. Inputs IN and INB (logic voltage levels, where INB is the inversion of IN) are received, and an output (high voltage level) OUT is generated at the drain of NMOS transistor 4208. A low value for IN results in a high value for OUT, and a high value for IN results in a low value for OUT, where the high values ​​of IN and OUT are different voltage levels.

[0205] In some details, when IN is high, NMOS transistor 4208 turns on, pulling OUT to ground, and PMOS transistor 4204 turns off and NMOS transistor 4205 turns on, so that OUT is pulled low by NMOS transistor 4205, which in turn turns on PMOS transistor 4202 and turns off NMOS transistor 4203, latching the high voltage level shifter.

[0206] When IN is low, INB is high, PMOS transistor 4204 is turned on, NMOS transistor 4205 is turned off, and OUT is pulled high to HVSUP, which in turn turns off PMOS transistor 4202 and turns on NMOS transistor 4203. Current bias source 4201 and current bias source 4206 respectively control the slope of the ramp of the output voltage.

[0207] Fig.43A ramp control circuit 4300 is depicted, which includes an NMOS transistor 4301, an NMOS transistor 4302, and an NMOS transistor 4305; a capacitor 4303 having a capacitance Cap; and a current bias 4304, which draws a current Ibias. The ramp control circuit 4300 provides ramp control of VHV (e.g., HVSUP, CG, EG, SL array terminals, pre-decoded high voltage signals). The ramp control circuit 4300 can be applied at the HV generation block 3410, the HV pre-decoder 3701, or the row decoder 3402. VHV is a high voltage node for ramp control. The NMOS transistor 4301 is always turned on based on the VDD applied to its gate. VNCTRLU is a control bias signal that turns on transistor 4302, which will absorb current from HVSUP to control the ramp rate of VHV. When it is desired that VNCTRLU is low, ENB is high because NMOS transistor 4305 pulls VNCTRLU down to ground. When VNCTRLU is low, NMOS transistor 4302 will be turned off. When it is desired that VHV ramp up to the final voltage, ENB goes low. When ENB goes low, NMOS transistor 4305 turns off. Charge will begin to accumulate on the lower plate of capacitor 4303 to produce a voltage at VCNTRLU to control the ramp rate of VHV. The ramp rate is equal to Cap*VHV / Ibias. Figure 4310 shows the waveforms for the ramp control circuit 4300. The voltage at node VHV initially remains at a low voltage level before the ramp (circuitry not shown).

[0208] Fig.44A ramp-down control circuit 4400 is depicted, which includes an NMOS transistor 4403, an NMOS transistor 4404, an NMOS transistor 4405, an NMOS transistor 4406, and an NMOS transistor 4407; a current bias source 4402 that draws a current Ibias; and a capacitor 4408 having a capacitance Cap. The ramp-down control circuit 4400 is switchably coupled to the CG, SL, or EG line of a selected row during a programming operation (where it switches from a first selected row to a second selected row during operation). The ramp-down control circuit 4400 can be implemented in an HV generation block 3410, an HV predecoder 3701, or a row decoder 3402. VHV is a controlled ramp-down high voltage node (e.g., HVSUP, CG, EG, SL array terminal, pre-decoding high voltage signal). NMOS transistor 4403 and NMOS transistor 4407 are always turned on based on VDD applied to their respective gates. When EN is high, ENB is low, and NMOS transistor 4404 will be turned on, and transistor 4405 will be turned off. In this state, VCNTRLD will be at a bias voltage to control the ramp rate of VHV. When EN goes low, ENB will go high, and transistor 4405 will be turned on and VCNTRLD will be pulled to ground. The ramp rate is equal to Cap*VHV / Ibias. Figure 4410 shows the waveforms for the ramp control circuit 4400.

[0209] It should be noted that, as used herein, the terms "above" and "on" both inclusively include "directly on" (no intervening materials, elements, or spaces are provided in between) and "indirectly on" (intervening materials, elements, or spaces are provided in between). Similarly, the term "adjacent" includes "directly adjacent" (no intervening materials, elements, or spaces are provided in between) and "indirectly adjacent" (intervening materials, elements, or spaces are provided in between), "mounted to" includes "directly mounted to" (no intervening materials, elements, or spaces are provided in between) and "indirectly mounted to" (intervening materials, elements, or spaces are provided in between), and "electrically coupled to" includes "directly electrically coupled to" (no intervening materials or elements electrically connecting the elements together) and "indirectly electrically coupled to" (intervening materials or elements electrically connecting the elements together). For example, forming an element "above" a substrate may include directly forming the element on the substrate without intervening materials / elements in between, and indirectly forming the element on the substrate with one or more intervening materials / elements in between.

Claims

1. A method, comprising: ramping the output of the high voltage generator to a first voltage level; programming a plurality of words of K rows of memory cells in an array of memory cells using the output of the high voltage generator while maintaining the output of the high voltage generator at the first voltage level, where K>1; as well as After the programming, the output of the high voltage generator is ramped down to a second voltage level.

2. The method according to claim 1, comprising: For one or more of the K rows, a control gate line voltage is ramped up to a third voltage level before programming the row and is ramped down to a fourth voltage level after programming the row. The method of claim 2 , wherein the fourth voltage level is equal to the second voltage level.

4. The method according to claim 2, comprising: For one or more of the K rows, a source line voltage is ramped up to a fifth voltage level before programming the row and is ramped down to a sixth voltage level after programming the row.

5. The method according to claim 4, comprising: For one or more of the K rows, the erase gate line voltage is ramped up to a seventh voltage level before programming the row and the source line voltage is ramped down to an eighth voltage level after programming the row.

6. The method according to claim 2, comprising: For one or more of the K rows, a control gate line voltage is ramped up to a third voltage level before programming the row and is ramped down to a fifth voltage level between the fourth voltage level and the third voltage level after programming the row. The method of claim 6 , wherein the fourth voltage level is equal to the second voltage level.

8. The method of claim 2, wherein the ramping up of the control gate voltage is ramp rate controlled.

9. The method of claim 8, wherein the ramp rate of the ramp up of the control gate voltage is faster than the ramp rate of the output of the high voltage generator.

10. A system, comprising: an array of memory cells arranged in rows and columns; a high voltage generation block for: (i) generating a first ramp-up voltage before performing a programming operation on a plurality of words in K rows of memory cells in the array, where K>1, (ii) generating a high voltage during performing the programming operation on K rows of memory cells in the array, and (iii) generating a first ramp-down voltage after performing the programming operation on K rows of memory cells in the array; and A ramp control circuit is configured to: (i) generate a second ramp-up voltage steeper than the first ramp-up voltage before programming one of the K rows of memory cells, (ii) apply the high voltage to a control gate line of a row of the array of memory cells to program one of the K rows of memory cells, and (iii) generate a second ramp-down voltage steeper than the first ramp-down voltage after programming the one of the K rows of memory cells.

11. The system of claim 10, wherein the ramp control circuit comprises: a PMOS transistor including a first terminal coupled to the high voltage generating block, a second terminal coupled to the control gate line, and a gate for receiving a first control signal; and An NMOS transistor includes a first terminal coupled to the control gate line, a second terminal coupled to a ground terminal, and a gate for receiving a second control signal.

12. The system of claim 11, wherein the PMOS transistor is current controlled by the gate of the PMOS transistor and the NMOS transistor is current controlled by the gate of the NMOS transistor.

13. The system of claim 10, wherein the ramp control circuit comprises: a first PMOS transistor including a first terminal coupled to the high voltage generating block, a second terminal, and a gate for receiving a first control signal; a second PMOS transistor including a first terminal coupled to the second terminal of the first PMOS transistor, a second terminal coupled to the control gate line, and a gate for receiving a second control signal; a first NMOS transistor, the first NMOS transistor comprising a first terminal coupled to the control gate line, a second terminal, and a gate for receiving a third control signal; and A second NMOS transistor includes a first terminal coupled to the second terminal of the first NMOS transistor, a second terminal coupled to a ground terminal, and a gate for receiving a fourth control signal.

14. The system of claim 13, wherein the second PMOS transistor is current controlled by the gate of the second PMOS transistor and the second NMOS transistor is current controlled by the gate of the second NMOS transistor.

15. The system of claim 10, wherein the ramp control circuit comprises: a first current bias source including a first terminal coupled to the high voltage generation block; a first PMOS transistor, the first PMOS transistor comprising a first terminal coupled to the second terminal of the first current source, a second terminal, and a gate for receiving a first control signal; a second PMOS transistor including a first terminal coupled to the second terminal of the first PMOS transistor, a second terminal coupled to the control gate line, and a gate for receiving a second control signal; an NMOS transistor, the NMOS transistor comprising a first terminal coupled to the control gate line, a second terminal, and a gate for receiving a third control signal; and A second current bias source is coupled between the second terminal of the NMOS transistor and ground.

16. The system of claim 10, wherein the ramp control circuit comprises: a first current bias source including a first terminal coupled to the high voltage generation block; a first PMOS transistor, the first PMOS transistor comprising a first terminal coupled to the second terminal of the first current source, a second terminal, and a gate for receiving a first control signal; a second PMOS transistor including a first terminal coupled to the second terminal of the first PMOS transistor, a second terminal, and a gate for receiving a second control signal; a third PMOS transistor, the third PMOS transistor comprising a first terminal coupled to the second terminal of the second PMOS transistor, a second terminal coupled to the control gate line, and a gate for receiving a third control signal; a first NMOS transistor, the first NMOS transistor comprising a first terminal coupled to the control gate line, a second terminal, and a gate for receiving a fourth control signal; a second NMOS transistor comprising a first terminal coupled to the second terminal of the first NMOS transistor, a second terminal, and a gate for receiving a fifth control signal; and A second current bias source is coupled between the second terminal of the second NMOS transistor and ground.

17. A system, comprising: an array of memory cells arranged in rows and columns; a high voltage generation block for: (i) generating a first ramp-up voltage before a programming operation is performed on a plurality of words in K rows of memory cells in the array, where K>1, (ii) generating a high voltage during the programming operation, and (iii) generating a first ramp-down voltage after the programming operation; a ramp control circuit for generating a second ramp voltage steeper than the first ramp voltage before programming one of the K rows of memory cells and applying the high voltage to a control gate line to program the one of the K rows of memory cells; and A ramp-down control circuit is provided for generating a second ramp-down voltage steeper than the first ramp-down voltage after programming said one of said K rows of memory cells.

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