An epitaxial structure and a method for preparing the same
During the growth of the epitaxial structure of GaAs-based HBT, the environment in the reaction chamber is controlled to avoid unnecessary mixed layer formation, and the interface quality problems caused by the residue of five-group element materials are solved, and the reliability and stability of the device are improved.
Patent Information
- Application Number
- CN202411842552.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-13
- Publication Date
- 2025-04-04
AI Technical Summary
During the growth of the epitaxial structure of GaAs-based HBT, the five-group elemental materials containing high saturated vapor pressure cannot be completely eliminated, resulting in the impact of the interface quality, which in turn affects the reliability and stability of the device.
By interrupting the access of the first reaction source and the second reaction source in the reaction chamber, performing a preset purge treatment, and then gradually entering the third reaction source to control the gradual closure of the second reaction source and the gradual entry of the third reaction source, ensuring the purity of the environment in the reaction chamber and avoiding unnecessary mixed layers.
It effectively reduces the residue of the second reaction source in the reaction chamber, reduces interface defects, improves the reliability and long-term stability of semiconductor devices, and improves the fineness and controllability of the process.
Smart Images
Figure CN119753827A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to an epitaxial structure and a method for preparing the same. Background Art
[0002] In the field of semiconductor technology, especially in the manufacture of high-performance electronic devices, GaAs-based heterojunction bipolar transistors (HBTs) have attracted much attention due to their excellent high-frequency and high-speed characteristics.
[0003] The GaAs-based HBT structure is usually formed on a semi-insulating GaAs substrate by epitaxial growth technology, in which the electrode preparation of the collector region and the base region depends on the high selectivity corrosion characteristics between the formed etching barrier layer including the group V element phosphorus (P) and the collector region layer including the group V element arsenic (As). During the wet etching process, the etching solution of the collector region layer has almost no corrosion effect on the etching barrier layer. This characteristic is used to accurately control the etching process to ensure that the corrosion stays accurately in the base region and the collector region. However, in the prior art, the growth windows of the etching barrier layer and the collector region layer are inconsistent, the optimal growth temperature of the etching barrier layer is lower than that of the collector region layer, and the saturated vapor pressure of P in the etching barrier layer is higher than that of As. This results in the formation of an alloy containing both As and P on the surface of the etching barrier layer when the material is converted from the etching barrier layer to the collector region layer during the growth process. The alloy is easily corroded by the etching solution of the collector region layer, thereby weakening the corrosion resistance of the etching barrier layer, so that the corrosion depth quickly reaches the vicinity of the semi-insulating substrate. Since the dislocation density of the semi-insulating substrate is as high as 5000 cm^-2, a large number of defects will be formed when the etching solution of the collector layer reaches here, resulting in a decrease in the reliability of the HBT device. In addition, during the switching process from the emitter region including the P element to the emitter region electrode layer including the As element during the growth process, it is also found that in the subsequent etching process, alloys containing both As and P will appear, thus affecting the material quality of the emitter region, and further affecting the reliability and stability of the HBT device.
[0004] Based on the above, during the growth process of the existing HBT epitaxial structure, if a large amount of gas source containing group V elements with high saturated vapor pressure remains in the reaction chamber, then during the switching process from the growth of materials containing group V elements with high saturated vapor pressure to the growth of materials containing group V elements with low saturated vapor pressure, it is easy to affect the quality of the material containing group V elements with high saturated vapor pressure, thereby affecting the device performance. Summary of the invention
[0005] Based on this, it is necessary to provide an epitaxial structure and a preparation method thereof to address the problem that during the growth process of the epitaxial structure of the HBT device in the prior art, the material containing the group V elements with high saturated vapor pressure cannot be completely eliminated during the conversion from the growth of the material containing the group V elements with high saturated vapor pressure to the growth of the material containing the group V elements with low saturated vapor pressure, thereby affecting the interface quality of the material containing the group V elements with high saturated vapor pressure, and thus affecting the reliability and stability of the HBT device.
[0006] In order to achieve the above object, on the one hand, the present invention provides a method for preparing an epitaxial structure, comprising the following steps:
[0007] Providing a substrate, and placing the substrate into a reaction chamber;
[0008] At least a first reaction source and a second reaction source are introduced into the reaction chamber to form a first semiconductor layer above the substrate;
[0009] interrupting the flow of the first reaction source and the second reaction source into the reaction chamber;
[0010] After the first reaction source and the second reaction source are interrupted, a purge process is performed in the reaction chamber for a preset purge time;
[0011] At least the first reaction source and the third reaction source are introduced into the reaction chamber to form a second semiconductor layer on the first semiconductor layer. The third reaction source and the second reaction source include the same main group element.
[0012] In one embodiment, the saturated vapor pressure of the second reaction source is greater than the saturated vapor pressure of the third reaction source.
[0013] In one embodiment, interrupting the flow of the first reaction source and the second reaction source into the reaction chamber comprises the following steps:
[0014] Closing the inlet valve of the first reaction source;
[0015] reducing the gas flow rate of the second reaction source introduced into the reaction chamber when forming the first semiconductor layer to a first preset value, wherein the first preset value is at least half of the gas flow rate of the second reaction source when forming the first semiconductor layer;
[0016] Then close the inlet valve of the second reaction source.
[0017] In one embodiment, the gas used for purging the reaction chamber includes hydrogen.
[0018] In one embodiment, the gas used for the purge process in the reaction chamber includes hydrogen.
[0019] In one embodiment, the preset purge time ranges from 2s to 5s.
[0020] In one embodiment, introducing the first reaction source and the third reaction source into the reaction chamber comprises the following steps:
[0021] Opening the inlet valve of the third reaction source within a first preset time, introducing the third reaction source into the reaction chamber, and the gas flow rate of the third reaction source introduced into the reaction chamber has a second preset value;
[0022] Increasing the gas flow rate of the third reaction source introduced into the reaction chamber to a third preset value within a second preset time, wherein the third preset value is at least twice the second preset value;
[0023] The first reaction source is introduced into the reaction chamber.
[0024] In one embodiment, the first preset time range is 0.05s~0.2s; the second preset time range is 0.05s~0.2s.
[0025] In one embodiment, when forming the first semiconductor layer, the reaction chamber is at a first reaction temperature; when forming the second semiconductor layer, the reaction chamber is at a second reaction temperature, and the first reaction temperature is lower than the second reaction temperature.
[0026] In a second aspect, the present invention provides an epitaxial structure, which is prepared by any of the above-mentioned methods for preparing an epitaxial structure.
[0027] The above-mentioned epitaxial structure of the present invention and its preparation method have the following beneficial effects: after forming the first semiconductor layer and before forming the second semiconductor layer, the first reaction source and the second reaction source in the reaction chamber are interrupted and the reaction chamber is purged for a preset purging time. In some embodiments, the gas flow rate of the second reaction source introduced into the reaction chamber when forming the first semiconductor layer is reduced to a first preset value, and then the introduction valve of the second reaction source is closed, and the introduction valve of the third reaction source is opened within the first preset time, and then the gas flow rate of the third reaction source introduced into the reaction chamber is increased to a third preset value within the second preset time. That is, in the transition process from the formation of the first semiconductor layer to the formation of the second semiconductor layer, the second reaction source is controlled to be gradually closed and the third reaction source is gradually introduced. Therefore, the residue of the second reaction source in the reaction chamber is effectively reduced, ensuring that the environment in the reaction chamber is purer before the second semiconductor layer is formed, avoiding the formation of an unnecessary mixed layer between the second reaction source and the third reaction source on the surface of the first semiconductor layer, reducing the interface defects of the first semiconductor layer, and improving the reliability and long-term stability of the semiconductor device; in addition, by precisely controlling the introduction and purging process of the reaction source, a more sophisticated and controllable means is provided for the semiconductor device manufacturing process, which not only improves the performance of the semiconductor device, but also lays the foundation for further process improvements and technological innovations. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0029] Figure 1 is a SEM image of the first semiconductor layer provided in the prior art;
[0030] Figure 2 is a flow chart of a method for preparing an epitaxial structure provided in an embodiment;
[0031] Figure 3 is a SEM image of a first semiconductor layer provided in an embodiment;
[0032] Figure 4 It is a schematic diagram of the cross-sectional structure of an epitaxial structure provided in one embodiment.
[0033] Description of reference numerals:
[0034] 1-substrate, 2-first semiconductor layer, 3-second semiconductor layer, 4-contact electrode layer, 5-base layer. DETAILED DESCRIPTION
[0035] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.
[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.
[0037] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. On the contrary, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
[0038] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.
[0039] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.
[0040] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic diagrams of ideal embodiments (and intermediate structures) of the invention, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Thus, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the invention.
[0041] See also Figure 2 , is a flow chart of a method for preparing an epitaxial structure, the present invention provides a method for preparing an epitaxial structure, comprising the following steps:
[0042] S1: providing a substrate 1 and placing the substrate 1 into a reaction chamber;
[0043] S2: introducing at least a first reaction source and a second reaction source into the reaction chamber to form a first semiconductor layer 2 on the substrate 1;
[0044] S3: interrupting the flow of the first reaction source and the second reaction source into the reaction chamber;
[0045] S4: performing a purge process for a preset purge time in the reaction chamber after the first reaction source and the second reaction source are interrupted;
[0046] S5: introducing at least a first reaction source and a third reaction source into the reaction chamber to form a second semiconductor layer 3 on the first semiconductor layer 2, wherein the third reaction source and the second reaction source include an element of the same main group.
[0047] The preparation method of the above-mentioned epitaxial structure interrupts the introduction of the first reaction source and the second reaction source into the reaction chamber and performs a purging treatment for a preset purging time in the reaction chamber after forming the first semiconductor layer 2 and before forming the second semiconductor layer 3. In some embodiments, the gas flow rate of the second reaction source introduced into the reaction chamber when forming the first semiconductor layer 2 is reduced to a first preset value, and then the introduction valve of the second reaction source is closed; when forming the second semiconductor layer 3, the introduction valve of the third reaction source is opened within the first preset time, and then the gas flow rate of the third reaction source introduced into the reaction chamber is increased to a third preset value within the second preset time. That is, in the process from the formation of the first semiconductor layer 2 to the formation of the second semiconductor layer 3, the second reaction source is controlled to be gradually closed and the third reaction source is gradually introduced. Therefore, the residue of the second reaction source in the reaction chamber is effectively reduced, ensuring that the environment in the reaction chamber is purer before the second semiconductor layer 3 is formed, thereby avoiding the second reaction source and the third reaction source from forming an unnecessary mixed layer on the surface of the first semiconductor layer 2, reducing the interface defects of the first semiconductor layer 2, and thereby improving the reliability and long-term stability of the semiconductor device; in addition, the preparation method of the epitaxial structure of the present invention provides a more sophisticated and controllable means for the semiconductor device manufacturing process by precisely controlling the introduction and purging process of the reaction source, which not only improves the performance of the semiconductor device, but also lays the foundation for further process improvements and technological innovations.
[0048] Step S1 is executed to provide a substrate 1 (not shown), and place the substrate 1 in a reaction chamber.
[0049] Specifically, the epitaxial structure of the semiconductor device is mainly formed by epitaxial growth using a chemical vapor deposition process. Therefore, a reaction chamber is provided, and different reaction sources are introduced into the reaction chamber to perform chemical reactions to complete the growth of the epitaxial structure.
[0050] Substrate 1 is used to provide physical support for the epitaxial structure. Exemplarily, substrate 1 is a semi-insulating substrate with high resistivity, which ensures the stability of the semiconductor device while realizing the preparation of high-performance semiconductor devices. In this embodiment, substrate 1 is a GaAs substrate, and its high resistivity characteristic can be achieved by doping the GaAs substrate with specific impurities to obtain a semi-insulating GaAs substrate, such as carbon. The doped impurity carbon can form an acceptor energy level in GaAs, thereby compensating the donor, reducing the carrier concentration, and increasing the resistivity of the material.
[0051] Specifically, the first reaction source includes group III elements; the second reaction source includes group V elements; and the third reaction source includes group V elements. Therefore, the first reaction source can react with both the second reaction source and the third reaction source. In this embodiment, the first reaction source is a Ga source, the second reaction source is a P source, such as PH3; and the third reaction source is an As source, such as AsH3.
[0052] In addition, the saturated vapor pressure of the second reaction source is greater than the saturated vapor pressure of the third reaction source. Therefore, after participating in the reaction, the second reaction source is not easy to be completely discharged from the reaction chamber. In the process of switching from forming the first semiconductor layer 2 to forming the second semiconductor layer 3, if the second reaction source is not completely eliminated, it will mix with the newly introduced third reaction source in the reaction chamber. Due to the similarity in chemical properties between the second reaction source and the third reaction source, both reaction sources will try to adsorb on the interface surface and participate in chemical reactions with the first reaction source. They can replace each other's sites to a certain extent, thereby forming a mixed layer on the surface of the first semiconductor layer 2 that has been formed, thereby affecting the interface characteristics and the performance of the semiconductor device. Therefore, in the process of switching from forming the first semiconductor layer 2 to forming the second semiconductor layer 3, it is necessary to effectively remove the second reaction source in the reaction chamber and avoid the second reaction source and the third reaction source from forming a mixed layer to ensure the yield and performance of the semiconductor device.
[0053] Specifically, see Figure 3 , execute steps S2 to S5, introduce at least a first reaction source and a second reaction source into the reaction chamber to form a first semiconductor layer 2 above the substrate 1; interrupt the introduction of the first reaction source and the second reaction source into the reaction chamber; perform a purge treatment for a preset purge time in the reaction chamber after the introduction of the first reaction source and the second reaction source is interrupted; introduce at least a first reaction source and a third reaction source into the reaction chamber to form a second semiconductor layer 3 on the first semiconductor layer 2, the third reaction source and the second reaction source include the same main group element.
[0054] In some embodiments, the first semiconductor layer 2 includes an etching barrier layer, which can serve as an etching stop layer for the base region and the collector region in the subsequent semiconductor device, so that the etching can accurately stop in the base region and the collector region, thereby achieving precise preparation of the semiconductor device; the second semiconductor layer 3 includes a collector region layer, which is the region for collecting carriers in the semiconductor device, and is usually composed of heavily doped materials to improve the collection efficiency and reduce the resistance of the collector.
[0055] In addition, when the first semiconductor layer 2 is an etching stop layer, before forming the first semiconductor layer 2, a step of forming a contact electrode layer 4 is also included, and the contact electrode layer 4 is located between the substrate 1 and the first semiconductor layer 2. The contact electrode layer 4 is used for contacting the collector region in the semiconductor device, and is a metal layer that connects the collector region and the external circuit and is used to collect current. The contact electrode layer 4 is formed by introducing a first reaction source and a third reaction source into the reaction chamber, and the first reaction source and the third reaction source react on the surface of the substrate 1. Under the condition of ensuring the performance of the epitaxial structure, the gas flow rate of the first reaction source and the third reaction source introduced when forming the contact electrode layer 4 and the thickness of the contact electrode layer 4 formed can be selected according to actual conditions, and are not limited here. In this embodiment, the contact electrode layer 4 is a GaAs layer.
[0056] When the first semiconductor layer 2 formed is an etching stop layer, a fourth reaction source is also introduced into the reaction chamber, and the fourth reaction source and the first reaction source include the same main group element, and the fourth reaction source can react chemically with the second reaction source. In the present embodiment, the fourth reaction source is an In source. Therefore, the first semiconductor layer 2 is formed by introducing the first reaction source, the second reaction source and the fourth reaction source into the reaction chamber, and the first reaction source, the second reaction source and the fourth reaction source react chemically from the surface of the contact electrode layer 4. Under the condition of ensuring the performance of the epitaxial structure, the gas flow rate of the first reaction source, the second reaction source and the fourth reaction source introduced when forming the first semiconductor layer 2 and the thickness of the formed first semiconductor layer 2 can be selected according to actual conditions, and no limitation is made here. In the present embodiment, when the first semiconductor layer 2 is used as an etching stop layer, the first semiconductor layer 2 is an InGaP layer.
[0057] When the second semiconductor layer 3 formed is a collector layer, the second semiconductor layer 3 is formed by introducing a first reaction source and a third reaction source into the reaction chamber, and the first reaction source and the third reaction source undergo a chemical reaction on the surface of the first semiconductor layer 2. When the performance of the epitaxial structure is guaranteed, the gas flow rate of the first reaction source and the third reaction source introduced when forming the second semiconductor layer 3 and the thickness of the formed second semiconductor layer 3 can be selected according to actual conditions, and are not limited here. In this embodiment, the second semiconductor layer 3 is a GaAs layer.
[0058] In some embodiments, the first semiconductor layer 2 includes an emitter region layer, which is a region in the semiconductor device where carriers are injected and is usually composed of highly doped materials to ensure efficient carrier injection; the second semiconductor layer includes an emitter electrode layer, which is a metal layer in the semiconductor device that connects the emitter region and an external circuit and is used to inject current.
[0059] When the first semiconductor layer 2 formed is the emission zone layer, a fourth reaction source is also introduced into the reaction chamber, and the fourth reaction source and the first reaction source include the same main group element, and the fourth reaction source can chemically react with the third reaction source. In the present embodiment, the fourth reaction source is an In source. The first semiconductor layer 2 is formed by introducing the first reaction source, the second reaction source and the fourth reaction source into the reaction chamber, and the first reaction source, the second reaction source and the fourth reaction source chemically react. Under the condition of ensuring the performance of the epitaxial structure, the gas flow rate of the first reaction source, the second reaction source and the fourth reaction source introduced when the first semiconductor layer 2 is formed and the thickness of the first semiconductor layer 2 formed can be selected according to actual conditions, and are not limited here. In the present embodiment, the first semiconductor layer 2 is an InGaP layer.
[0060] When the second semiconductor layer 3 formed is an emission electrode layer, a fourth reaction source is also introduced into the reaction chamber, and the fourth reaction source and the first reaction source include the same main group element, and the fourth reaction source can react chemically with the third reaction source. In the present embodiment, the fourth reaction source is an In source. The second semiconductor layer 3 is formed by introducing the first reaction source, the third reaction source and the fourth reaction source into the reaction chamber, and the first reaction source, the third reaction source and the fourth reaction source react chemically from the surface of the first semiconductor layer 2. Under the condition of ensuring the performance of the epitaxial structure, the gas flow rate of the first reaction source, the third reaction source and the fourth reaction source introduced when forming the second semiconductor layer 3 and the thickness of the formed second semiconductor layer 3 can be selected according to actual conditions, and are not limited here. In the present embodiment, the second semiconductor layer 3 is an InGaAs layer.
[0061] In this embodiment, when forming the epitaxial structure, the first semiconductor layer 2 and the second semiconductor layer 3 are formed in two cases where the first semiconductor layer 2 includes an etch stop layer, the second semiconductor layer 3 includes a collector region layer, the first semiconductor layer 2 includes an emitter region layer, and the second semiconductor layer 3 includes an emitter electrode layer. The first semiconductor layer 2 and the second semiconductor layer 3 in the case where the first semiconductor layer 2 includes an etch stop layer and the second semiconductor layer 3 includes a collector region layer are formed before the first semiconductor layer 2 and the second semiconductor layer 3 in the case where the first semiconductor layer 2 includes an emitter region layer and the second semiconductor layer 3 includes an emitter electrode layer.
[0062] Then, after forming the second semiconductor layer 3 which is the collector layer and before forming the first semiconductor layer 2 which is the emitter layer, the step of forming the base layer 5 is also included.
[0063] The base layer 5 is formed by introducing a first reaction source and a third reaction source into the reaction chamber, and the first reaction source and the third reaction source react chemically on the surface of the second semiconductor layer 3 which is the collector layer. The base layer 5 is used to control the flow of current between the emitter region and the collector region, and is usually composed of low-doped materials to reduce the resistance of the base layer 5 and improve the switching speed of the semiconductor device. While ensuring the performance of the epitaxial structure, the gas flow rates of the first reaction source and the third reaction source introduced when forming the base layer 5 and the thickness of the formed base layer 5 can be selected according to actual conditions, and are not limited here. In this embodiment, the base layer 5 is a GaAs layer.
[0064] In some embodiments, step S3 further includes steps S31 to S33, and interrupting the flow of the first reaction source and the second reaction source into the reaction chamber includes the following steps:
[0065] S31: Close the inlet valve of the first reaction source. In addition, when the first semiconductor layer 2 formed is an etching stop layer, the fourth reaction source participating in the reaction when the first semiconductor layer 2 is formed needs to be closed; when the first semiconductor layer 2 formed is an emitter layer, the fourth reaction source participating in the reaction when the first semiconductor layer 2 is formed needs to be closed. By closing the reaction source when the first semiconductor layer 2 is formed, the subsequent process is avoided from being affected.
[0066] S32: reducing the gas flow rate of the second reaction source introduced into the reaction chamber when forming the first semiconductor layer 2 to a first preset value, wherein the first preset value is at least half of the gas flow rate of the second reaction source when forming the first semiconductor layer 2.
[0067] S33: Then close the inlet valve of the second reaction source. By gradually closing the second reaction source and accurately controlling the gas flow of the second reaction source during the closing process, it can be ensured that the second reaction source in the reaction chamber is gradually cleared rather than suddenly interrupted, which helps to more thoroughly remove the second reaction source residue and avoid incomplete chemical reaction or residue accumulation caused by sudden closing.
[0068] In some embodiments, the time range used to reduce the gas flow rate of the second reaction source introduced into the reaction chamber to the first preset value when forming the first semiconductor layer 2 is 0.05s~0.2s; the time range used to close the access valve of the second reaction source is 0.05s~0.2s. Exemplarily, the time used to reduce the gas flow rate of the second reaction source introduced into the reaction chamber to the first preset value when forming the first semiconductor layer 2 is 0.1s; the time used to close the access valve of the second reaction source is 0.1s. By precisely controlling the time of each step of gradually closing the second reaction source and completing the closing of the second reaction source as quickly as possible, it is ensured that the second reaction source in the reaction chamber is cleared as quickly as possible, while also improving process efficiency.
[0069] In some embodiments, the gas introduced into the reaction chamber for the purge treatment includes hydrogen. Hydrogen is used as the purge gas to purge and remove the second reaction source remaining in the reaction chamber. Hydrogen has a small molecular weight and good fluidity, and can penetrate deeper into every corner of the reaction chamber, thereby removing the residue more thoroughly. As an inert gas, hydrogen will not react with other chemical substances in the reaction chamber, so the residual second reaction source can be effectively removed. For example, hydrogen will not react with the first reaction source, the second reaction source, the third reaction source, and the fourth reaction source in the embodiments of the present invention.
[0070] In some embodiments, the preset purge time ranges from 2s to 5s. Exemplarily, the preset purge time is 3s. By precisely controlling the purge time, the residue of the second reaction source can be removed as quickly as possible to avoid mixing of the second reaction source with the third reaction source. At the same time, it also avoids the purge time being too long, resulting in excessive adsorption of the second reaction source on the surface of the first semiconductor layer 2. As the second semiconductor layer 3 grows, the atoms of the third reaction source will replace the second reaction source on the surface of the first semiconductor layer 2, thereby forming a thicker mixed layer of the third reaction source and the second reaction source, forming an interface defect on the surface of the first semiconductor layer 2.
[0071] In some embodiments, step S4 further includes steps S41 to S43, and introducing the first reaction source and the third reaction source into the reaction chamber includes the following steps:
[0072] S41: opening the inlet valve of the third reaction source within a first preset time, introducing the third reaction source into the reaction chamber, and the gas flow rate of the third reaction source introduced into the reaction chamber has a second preset value;
[0073] S42: increasing the gas flow rate of the third reaction source introduced into the reaction chamber to a third preset value within the second preset time, wherein the third preset value is at least twice the second preset value;
[0074] S43: Introduce a first reaction source into the reaction chamber.
[0075] By gradually introducing the third reaction source and precisely controlling the gas flow rate of the third reaction source during the introduction process, the uniform distribution and adsorption of the third reaction source on the surface of the first semiconductor 2 can be ensured, the introduction of impurities can be reduced, and a sudden excess of the third reaction source can be avoided, which may cause uneven adsorption of the third reaction source on the surface of the first semiconductor 2, and further cause unnecessary side reactions or impurity formation on the surface of the first semiconductor 2, affecting the performance of the first semiconductor 2.
[0076] In some embodiments, the first preset time range is 0.05s to 0.2s; the fourth preset time range is 0.05s to 0.2s. Exemplarily, the second preset time is 0.1s; the fourth preset time is 0.1s. By precisely controlling the time of each step of gradually introducing the third reaction source and completing the introduction of the third reaction source as quickly as possible, unnecessary side reactions in the reaction chamber can be avoided while also improving process efficiency.
[0077] In some embodiments, when forming the first semiconductor layer 2, the reaction chamber is at a first reaction temperature; when forming the second semiconductor layer 3, the reaction chamber is at a second reaction temperature, and the first reaction temperature is lower than the second reaction temperature, and while gradually introducing the third reaction source for forming the second semiconductor layer 3 into the reaction chamber, the temperature in the reaction chamber is also gradually raised from the first reaction temperature to the second reaction temperature. That is, the formation of the first semiconductor layer 2 and the second semiconductor layer 3 both have their own optimal growth temperatures, and the optimal growth temperature of the first semiconductor layer 2 is lower than the optimal growth temperature of the second semiconductor layer 3. Then, the low-temperature growth of the first semiconductor layer 2 can improve the material quality, further enhance the corrosion resistance of the first semiconductor layer 2 in subsequent processes, thereby reducing the formation of interface defects and improving the reliability of semiconductor devices.
[0078] In addition, when the first reaction source is introduced into the reaction chamber during the formation of the second semiconductor layer 3, the temperature in the reaction chamber gradually increases from the first reaction temperature to the second reaction temperature. The temperature increase process of the reaction temperature is further optimized to further ensure the reliability of the semiconductor device.
[0079] See also Figure 3, is a SEM image of the first semiconductor layer 2 (specifically, a SEM image when the first semiconductor layer 2 is an etching stop layer). The first semiconductor layer 2 prepared by the method for preparing the epitaxial structure in the embodiment of the present invention has significantly reduced surface defects compared to the first semiconductor layer located in the lower layer formed in the prior art, that is, the method for preparing the epitaxial structure in the embodiment of the present invention can significantly improve the interface defects generated by the second reaction source from the first semiconductor layer 2 formed by the second reaction source to the second semiconductor layer 3 formed by the third reaction source, and the third reaction source from the surface of the first semiconductor layer 2, thereby improving the life of the semiconductor device.
[0080] It should be noted that the above-mentioned purging treatment and reaction source control scheme performed during the growth of the first semiconductor layer 2 and the second semiconductor layer 3 are applicable to different situations where the first semiconductor layer 2 includes an etch stop layer, and the second semiconductor layer 3 includes a collector layer; the first semiconductor layer 2 includes an emitter layer, and the second semiconductor layer 3 includes an emitter electrode layer. However, regarding the setting values of time, temperature and gas flow rate that appear in the process, in different situations where the first semiconductor layer 2 includes an etch stop layer, and the second semiconductor layer 3 includes a collector layer; the first semiconductor layer 2 includes an emitter layer, and the second semiconductor layer 3 includes an emitter electrode layer, the setting values of time, temperature and gas flow rate may remain consistent or inconsistent, and may be selected according to actual conditions. Mainly, the process of forming the conversion process between the first semiconductor layer 2 and the second semiconductor layer 3 can be optimized through the above-mentioned technical solution of the present invention to improve the performance of the semiconductor device.
[0081] It should be understood that although Figure 2 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 2 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.
[0082] Please continue reading Figure 4 The present invention also provides an epitaxial structure, and the epitaxial structure is prepared by the above-mentioned semiconductor structure preparation method, including: a substrate 1, a first semiconductor layer 2 and a second semiconductor layer 3, the first semiconductor material layer 2 is located above the substrate 1, and the second semiconductor layer 3 is located on the first semiconductor layer 3.
[0083] In this embodiment, the epitaxial structure includes the first semiconductor layer 2 including an etch stop layer, the second semiconductor layer 3 including a collector region layer, the first semiconductor layer 2 including an emitter region layer, and the second semiconductor layer 3 including an emitter electrode layer. The first semiconductor layer 2 and the second semiconductor layer 3 when the first semiconductor layer 2 includes an etch stop layer and the second semiconductor layer 3 includes a collector region layer are located below the first semiconductor layer 2 and the second semiconductor layer 3 when the first semiconductor layer 2 includes an emitter region layer and the second semiconductor layer 3 includes an emitter electrode layer.
[0084] A contact electrode layer 4 is provided between the substrate 1 and the first semiconductor layer 2 which is an etching stop layer; a base layer 5 is also provided between the second semiconductor layer 3 which is a collector layer and the first semiconductor layer 2 which is an emitter layer.
[0085] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.
[0086] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0087] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.
Claims
1. A method for preparing an epitaxial structure, characterized in that: The steps include: Providing a substrate, and placing the substrate into a reaction chamber; At least a first reaction source and a second reaction source are introduced into the reaction chamber to form a first semiconductor layer above the substrate; interrupting the flow of the first reaction source and the second reaction source into the reaction chamber; After the first reaction source and the second reaction source are interrupted, a purge process is performed in the reaction chamber for a preset purge time; At least the first reaction source and the third reaction source are introduced into the reaction chamber to form a second semiconductor layer on the first semiconductor layer. The third reaction source and the second reaction source include the same main group element.
2. The method for preparing an epitaxial structure according to claim 1, characterized in that: The saturated vapor pressure of the second reaction source is greater than the saturated vapor pressure of the third reaction source.
3. The method for preparing an epitaxial structure according to claim 1, characterized in that: Interrupting the flow of the first reaction source and the second reaction source into the reaction chamber comprises the following steps: Closing the inlet valve of the first reaction source; reducing the gas flow rate of the second reaction source introduced into the reaction chamber when forming the first semiconductor layer to a first preset value, wherein the first preset value is at least half of the gas flow rate of the second reaction source when forming the first semiconductor layer; Then close the inlet valve of the second reaction source.
4. The method for preparing an epitaxial structure according to claim 1, characterized in that: The gas used for purging the reaction chamber includes hydrogen.
5. The method for preparing an epitaxial structure according to claim 1, characterized in that: The preset purge time ranges from 2s to 5s.
6. The method for preparing an epitaxial structure according to claim 1, characterized in that: Introducing the first reaction source and the third reaction source into the reaction chamber comprises the following steps: Opening the inlet valve of the third reaction source within a first preset time, introducing the third reaction source into the reaction chamber, and the gas flow rate of the third reaction source introduced into the reaction chamber has a second preset value; Increasing the gas flow rate of the third reaction source introduced into the reaction chamber to a third preset value within a second preset time, wherein the third preset value is at least twice the second preset value; The first reaction source is introduced into the reaction chamber.
7. The method for preparing an epitaxial structure according to claim 6, characterized in that: The first preset time range is 0.05s~0.2s; the second preset time range is 0.05s~0.2s.
8. The method for preparing an epitaxial structure according to claim 1, characterized in that: When the first semiconductor layer is formed, the reaction chamber is at a first reaction temperature; when the second semiconductor layer is formed, the reaction chamber is at a second reaction temperature, and the first reaction temperature is lower than the second reaction temperature.
9. The method for preparing an epitaxial structure according to claim 1, characterized in that: The first semiconductor layer includes an etch stop layer, and the second semiconductor layer includes a collector region layer; and / or the first semiconductor layer includes an emitter region layer, and the second semiconductor layer includes an emitter electrode layer.
10. An epitaxial structure, characterized in that: The epitaxial structure is prepared by the method for preparing an epitaxial structure according to any one of claims 1 to 9.