A method for preparing silicon carbide film layer

Abstract

The present application provides a method for preparing a silicon carbide film layer, comprising the following steps: forming a plurality of micropores with nanometer-sized pores on the surface of a substrate, forming a microporous rough layer on the surface of the substrate; depositing a silicon carbide film layer on the microporous rough layer; removing the substrate to form a separate silicon carbide film layer. The present application solves the technical problem that the conventional process for preparing CVD silicon carbide coatings cannot prepare thick and high-quality silicon carbide coatings.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular, to a method for preparing a silicon carbide film layer. Background Art

[0002] CVD silicon carbide coating is a silicon carbide film prepared by chemical vapor deposition, which has many advantages and a wide range of applications. It has excellent chemical stability and high temperature resistance, and is used in high-temperature thermoelectric conversion materials, aerospace equipment, nuclear industry, chemical industry and other fields; high hardness and wear resistance, used in mechanical parts, cutting tools, bearings, turbomachinery, mechanical seals and other fields; excellent insulation and dielectric properties, can be used in insulating materials, capacitors, electronic components, semiconductor devices and other fields; excellent chemical corrosion resistance, used in highly corrosive environments such as chemical industry, electroplating industry and seawater environment; excellent thermal conductivity and heat conductivity, widely used in electronic devices, electronic heat dissipation equipment, high-temperature smelting equipment and other fields; good optical properties, can be used in optical fields such as optical films, optical lenses, solar energy equipment, lasers, etc.

[0003] The current mainstream process for silicon carbide coating (SiC coating) is to deposit it on an isostatic graphite substrate. The main reason is that isostatic graphite is resistant to high temperatures, has excellent performance parameters such as thermal stability and thermal uniformity, and its thermal expansion coefficient is close to that of silicon carbide. When isostatic graphite is used as the substrate for SiC coating deposition, the graphite itself has many particles and poor surface roughness, which has a great impact on the quality of silicon carbide after deposition. In addition, the cost of isostatic graphite is also high. Currently, it is mainly imported from abroad, and the mainstream is Japan's Toyo Tanso, Tokai Carbon, Germany's SGL, France's Mersen, and the United States' Buge, and the price is very high.

[0004] The industry has also tried to use silicon wafers as the substrate for silicon carbide coatings (SiC coatings). As a mature semiconductor substrate, silicon wafers have the advantages of high purity, no pollution, good surface roughness, and low cost. However, the thermal expansion coefficient of silicon wafers is 2.6×10 -6 / K, and polycrystalline SiC 3.5×10 -6 / K has a large difference, and the thermal stress is very large during deposition. The effect is acceptable when a silicon carbide coating (SiC coating) with a very small thickness is formed, but the silicon carbide coating is easy to peel off when a silicon carbide coating (SiC coating) with a slightly larger thickness (100 microns) is formed.

[0005] For this reason, some technologies use the surface treatment of silicon, such as the surface groove treatment in patent CN1816897B. However, this process suitable for bonding two materials will cause the silicon carbide coating (SiC coating) to grow in the grooves if a CVD silicon carbide coating (SiC coating) is to be grown. Figure 1As shown, the substrate 82 and the thin film 85 are silicon carbide coatings (SiC coatings). The silicon carbide coatings (SiC coatings) finally formed are uneven and of poor quality and cannot be applied to the substrate end of semiconductor devices.

[0006] Figure 2 This is a schematic diagram of patent CN112647055B. Patent CN112647055B uses a surface etching method to achieve the purpose of stress release. However, the surface height difference of this etching is large (>5μm) and the roughness uniformity is poor. This has a great impact on the quality of the silicon carbide coating (SiC coating) after CVD SiC growth.

[0007] The bottleneck of silicon wafer as SiC CVD deposition substrate lies in two points:

[0008] 1. The difference in thermal expansion coefficient leads to excessive thermal stress, making it difficult to form a silicon carbide coating (SiC coating) with a thickness of more than 100 microns, and it is easy to crack and peel off.

[0009] 2. The current technology uses a groove or etching method to treat the silicon surface, which makes it difficult to form a high-quality CVD silicon carbide coating (SiC coating) that can be applied to the device substrate, and the roughness is very large.

[0010] Therefore, the traditional process for preparing CVD silicon carbide coatings cannot produce thick and high-quality silicon carbide coatings, which is a technical problem that technical personnel in this field urgently need to solve.

[0011] The above information disclosed in the background section is only for enhancing understanding of the background of the present application and therefore it may contain information that does not form the prior art known to a person of ordinary skill in the art. Summary of the invention

[0012] The present application provides a method for preparing a silicon carbide film layer to solve the technical problem that the traditional process for preparing CVD silicon carbide coatings cannot prepare thick and high-quality silicon carbide coatings.

[0013] The present application provides a method for preparing a silicon carbide film layer, comprising the following steps:

[0014] A plurality of micropores with nanometer-scale pore diameters are formed on the surface of the substrate, and a microporous rough layer is formed on the surface of the substrate;

[0015] depositing a silicon carbide membrane layer on the microporous rough layer;

[0016] The substrate is removed to form a separate silicon carbide film layer.

[0017] Due to the adoption of the above technical solution, this application has the following technical effects:

[0018] The method for preparing the silicon carbide film layer of the application forms a plurality of micropores with nanometer-sized pores on the surface of the substrate, and forms a microporous rough layer on the surface of the substrate. In this way, the surface of the substrate is roughened by the nanoscale micropores, and the surface atomic structure of the substrate is disrupted by the nanoscale micropores. The surface atomic structure of the substrate is disrupted by the nanoscale micropores, which provides space for releasing the stress of the substrate, so that the stress release of the substrate does not act on the deposited silicon carbide film layer, but acts on the microporous rough layer, so that the silicon carbide film layer can be thicker and less prone to cracking and peeling.

[0019] The reason for selecting nano-scale micropores is that the pore size of the micropores is small. In the subsequent process of depositing a silicon carbide film layer on the microporous rough layer, the roughness of the silicon carbide film layer is small, so that the roughness and particle size of the final single silicon carbide film layer are small. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0021] Figure 1 It is a schematic diagram of patent CN1816897B;

[0022] Figure 2 It is a schematic diagram of patent CN112647055B;

[0023] Figure 3 A schematic diagram of completing step S1 of the method for preparing a silicon carbide film layer of the present application;

[0024] Figure 4 A schematic diagram of completing step S2 of the method for preparing a silicon carbide film layer of the present application;

[0025] Figure 5 A schematic diagram of completing step S3 of the method for preparing a silicon carbide film layer of the present application;

[0026] Figure 6 is a schematic diagram of completing step S5 of the method for preparing a silicon carbide film layer of the present application;

[0027] Figure 7 It is a schematic diagram of completing step S6 of the method for preparing a silicon carbide film layer of the present application.

[0028] Reference numerals:

[0029] Substrate 1, microporous rough layer 2, silicon carbide membrane layer 3. DETAILED DESCRIPTION

[0030] In order to make the technical solutions and advantages of the present application more clearly understood, the exemplary embodiments of the present application are further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than an exhaustive list of all the embodiments. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other without conflict.

[0031] Embodiment 1

[0032] like Figures 3 to 7 As shown, the method for preparing the silicon carbide film layer of the present application comprises the following steps:

[0033] A plurality of micropores with nanometer-scale pore diameters are formed on the surface of the substrate 1, and a microporous rough layer 2 is formed on the surface of the substrate;

[0034] Depositing a silicon carbide film layer 3 on the microporous rough layer 2;

[0035] The substrate is removed to form a separate silicon carbide film layer 3 .

[0036] The method for preparing the silicon carbide film layer of the present application is aimed at substrate materials with excessive thermal stress, including but not limited to single crystal silicon wafers.

[0037] The method for preparing the silicon carbide film layer of the present application forms a plurality of micropores with a pore size of nanometers on the surface of the substrate, and forms a microporous rough layer on the surface of the substrate. In this way, the surface of the substrate is roughened by the nanometer-scale micropores, and the nanometer-scale micropores disrupt the surface atomic structure of the substrate. The nanometer-scale micropores disrupt the surface atomic structure of the substrate, providing space for releasing the stress of the substrate, so that the stress release of the substrate does not act on the deposited polycrystalline silicon carbide film layer, but acts on the microporous rough layer, so that the silicon carbide film layer can be thicker and less prone to cracking and peeling.

[0038] The reason for choosing nano-scale micropores is that the pore size of the micropores is small. In the subsequent process of depositing a silicon carbide film layer on the microporous rough layer, the roughness of the silicon carbide film layer is small, so that the roughness and particle size of the final single silicon carbide film layer are small, resulting in a high-quality silicon carbide film layer.

[0039] In implementation, the substrate 1 is a single crystal silicon wafer;

[0040] The silicon carbide film layer 3 is a polycrystalline silicon carbide film layer 3 .

[0041] The substrate is usually a silicon wafer. Single-crystal silicon carbide cannot grow on the microporous rough layer formed on the surface of the silicon wafer. Therefore, the silicon carbide film layer can only be a polycrystalline silicon carbide film layer.

[0042] In practice, micropores with nanometer-scale pore diameters refer to pore diameters in the range of greater than or equal to 1 nanometer and less than or equal to 100 nanometers.

[0043] In practice, the step of forming a plurality of micropores with nanometer-scale pore sizes on the surface of the substrate 1 specifically includes the following steps:

[0044] The surface of the substrate 1 is subjected to micropore treatment by ion implantation to form micropores with a pore size of nanometer level.

[0045] The reason why ion implantation is used to form nano-scale micropores is that ion implantation implants atoms, and the diameter of atoms themselves is less than 0.5 nanometers. Therefore, the micropores formed by ion implantation can be guaranteed to be micropores with a pore size of nanometers. At the same time, the uniformity of the ion implantation process itself is relatively high, so that the roughness of the final single polycrystalline silicon carbide film layer is relatively low.

[0046] In practice, the thickness of the microporous rough layer 2 is in the range of greater than or equal to 0.1 micrometer.

[0047] The step of performing micropore treatment on the surface of the substrate by ion implantation to form micropores with a pore size of nanometers is specifically:

[0048] Ion implantation is performed on the surface of the silicon wafer 1, wherein the implanted atoms are germanium atoms or argon atoms;

[0049] The injection dose range is greater than or equal to 10 15 ions / cm 2 Less than or equal to 10 17 ions / cm 2 ;

[0050] The implantation energy is greater than 20keV.

[0051] The above-mentioned implantation dose can form micropores with a pore size of nanometers on the surface of the substrate. The implanted atoms are germanium atoms or argon atoms. The principle of selecting the implanted atoms is neutral atoms with a large atomic weight. The neutrality is to prevent the implanted atoms from affecting the electrical properties of the silicon carbide film layer.

[0052] As an optional manner, the thickness of the microporous rough layer 2 is in a range of greater than or equal to 0.1 micrometer.

[0053] In practice, when the uniformity of the ion implantation dose is within 0.5% within the wafer, the thickness of the silicon carbide film layer 2 is greater than or equal to 1 mm.

[0054] The uniformity of ion implantation dose within 0.5% is an important indicator in ion implantation technology. This requires that the difference in implantation dose in each area of ​​the implanted semiconductor wafer be controlled within 0.5% to ensure the uniformity of doping and the consistency of device performance.

[0055] The thickness of the silicon carbide film layer 2 is greater than or equal to 1 mm, and a silicon carbide film layer with greater thickness and higher quality is obtained.

[0056] In practice, a plurality of micropores with nanometer-scale pore sizes are formed on the surface of the substrate, and the step of forming the microporous rough layer 2 on the surface of the substrate specifically includes:

[0057] Forming a plurality of micropores with nanometer-scale pore diameters on the upper surface of the substrate;

[0058] A plurality of micropores with nanometer-level pore diameters are formed on the upper surface of the substrate 1; at this time, microporous rough layers 2 are formed on the upper and lower surfaces of the substrate respectively;

[0059] The step of depositing a polycrystalline silicon carbide film layer on the microporous rough layer 1 specifically includes:

[0060] Depositing a polycrystalline silicon carbide film layer 3 on the microporous rough layer 2 on the upper surface of the substrate;

[0061] A polycrystalline silicon carbide film layer 3 is deposited on the microporous rough layer 2 on the lower surface of the substrate.

[0062] In addition, the method for preparing the silicon carbide film layer of the present application adopts an ion implantation process and a deposition process, so that the preparation method has simple steps and is easy to operate, while also having a low cost and a high cleanliness level.

[0063] The following is an example of a silicon wafer as a substrate, and the preparation method of the silicon carbide film layer of the present application is described in the processing sequence. The steps include:

[0064] Step S1: Figure 3 As shown, a single crystal silicon wafer is prepared as a substrate 1;

[0065] Step S2: Figure 4 As shown, a plurality of micropores with a nanometer pore size are formed on the upper surface of the substrate 1 by ion implantation;

[0066] Step S3: Figure 5 As shown, a plurality of micropores with a pore size of nanometers are formed on the lower surface of the substrate 1 by ion implantation; at this time, microporous rough layers 2 are formed on the upper and lower surfaces of the substrate respectively;

[0067] Step S4: depositing a polycrystalline silicon carbide film layer 3 on the microporous rough layer 2 on the upper surface of the substrate;

[0068] Step S5: Figure 6 As shown, a polycrystalline silicon carbide film layer 3 is deposited on the microporous rough layer 2 on the lower surface of the substrate;

[0069] Step S6: Figure 7As shown, the substrate (the microporous rough layer is the surface of the substrate) is removed to form a separate polycrystalline silicon carbide film layer 3.

[0070] The preparation method of the silicon carbide film layer of the present application has been verified by experiments and simulations, and the results are feasible. The key performance is far better than that of graphite sheets and also better than the existing porous silicon technology in the industry (mainly reflected in the surface roughness after film growth, and the particle size and metal content are also improved).

[0071]

[0072] The last row in the table shows the silicon carbide film layer prepared by the method for preparing the silicon carbide film layer of the present application, and the roughness, granularity, and metal content of the silicon carbide film layer are relatively small, which is exactly what the silicon carbide film layer is pursuing.

[0073] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0074] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0075] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0076] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0077] Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0078] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A method for preparing a silicon carbide film layer, characterized in that: The steps include: A plurality of micropores with nanometer-scale pore diameters are formed on the surface of a substrate (1), and a microporous rough layer (2) is formed on the surface of the substrate; Depositing a silicon carbide film layer (3) on the microporous rough layer; The substrate is removed to form a separate silicon carbide film layer (3).

2. The method for preparing a silicon carbide film layer according to claim 1, characterized in that: The step of forming a plurality of micropores with nanometer pore sizes on the surface of the substrate specifically comprises the following steps: The surface of the substrate is treated with micropores by ion implantation to form micropores with a pore size of nanometer level.

3. The method for preparing a silicon carbide film layer according to claim 2, characterized in that: The diameter of atoms in ion implantation is on the order of 0.5 nanometers or less.

4. The method for preparing a silicon carbide film layer according to claim 3, characterized in that: The substrate is a single crystal silicon wafer; The silicon carbide film layer (3) is a polycrystalline silicon carbide film layer (3).

5. The method for preparing a silicon carbide film layer according to claim 3, characterized in that: The thickness of the microporous rough layer (2) is in the range of greater than or equal to 0.1 micrometer.

6. The method for preparing a silicon carbide film layer according to claim 4, characterized in that: The pore size of nano-scale micropores ranges from greater than or equal to 1 nanometer to less than or equal to 100 nanometers.

7. The method for preparing a silicon carbide film layer according to claim 6, characterized in that: The step of performing micropore treatment on the surface of the substrate by ion implantation to form micropores with a pore size of nanometers is specifically: Performing ion implantation on the surface of the silicon wafer, wherein the implanted atoms are germanium atoms or argon atoms; The injection dose range is greater than or equal to 10 15 ions / cm 2 Less than or equal to 10 17 ions / cm 2 ; The implantation energy is greater than 20keV.

8. The method for preparing a silicon carbide film layer according to claim 7, characterized in that: When the uniformity of the ion implantation dose reaches within 0.5% within the wafer, the thickness of the silicon carbide film layer (3) is greater than or equal to 1 mm.

9. The method for preparing a silicon carbide film layer according to claim 3, characterized in that: A plurality of micropores with nanometer-scale pore sizes are formed on the surface of a substrate (1), and the step of forming a microporous rough layer (2) on the surface of the substrate specifically comprises: Forming a plurality of micropores with nanometer-scale pore diameters on the upper surface of the substrate; A plurality of micropores with nanometer-scale pore diameters are formed on the upper surface of the substrate; at this time, microporous rough layers (2) are formed on the upper surface and the lower surface of the substrate respectively; The step of depositing a polycrystalline silicon carbide film layer on the microporous rough layer specifically comprises: Depositing a polycrystalline silicon carbide film layer (3) on the microporous rough layer on the upper surface of the substrate; A polycrystalline silicon carbide film layer (3) is deposited on the microporous rough layer on the lower surface of the substrate.

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