Integrated evaluation method suitable for multiple types of electronic paste
By designing a method of integrated layout of tic toe distribution and multi-performance integration test and analysis, the problem of lack of comprehensive, holistic and professional evaluation methods in the existing technology is solved, and the efficient, low-cost and integrated evaluation of multiple electronic pastes is achieved, which promotes product upgrades and technical iterations.
Patent Information
- Application Number
- CN202411715974.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-27
- Publication Date
- 2025-04-04
AI Technical Summary
The existing technology lacks a comprehensive, holistic and professional evaluation method to assess the quality of multiple electronic pastes, resulting in unstable quality, uneven batches, and mismatch in process, which limits the product upgrade and technical iteration of electronic pastes.
A method of integrated evaluation is designed. Through the integrated integrated layout of tic toe distribution, multiple electronic pastes are screen-printed on the substrate according to the corresponding relationship of the printing line of the row and column, and multi-performance integrated tests are carried out, including overall testing and section testing, and targeted testing is carried out for the overlap interface of different pastes.
It has realized the integrated integrated design and manufacturing of large-volume, multi-category and multi-functional electronic pastes, which has improved testing efficiency and accuracy, reduced costs, and solved the problems of incomplete evaluation methods, high test repeatability, low efficiency and high cost in the existing technology.
Smart Images
Figure CN119757646A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of electronic material testing and analysis, and in particular to a centralized evaluation method applicable to multiple types of electronic pastes. Background Art
[0002] Electronic paste is an important material for preparing LTCC circuit substrates and integrated circuit substrates. The performance stability and quality control of the paste are the main reasons for ensuring stable electronic circuit communication and smooth circuits. In recent years, domestic pastes have developed rapidly. Many domestic manufacturers have carried out a large number of research and development work on different types of electronic pastes, and have derived dozens of domestic paste categories. However, due to the wide variety of pastes, diverse functions, complex and changeable compositions, and diverse raw materials, there are many problems such as unstable quality, uneven batches, and process mismatches. At present, there is no comprehensive, holistic, and professional evaluation and assessment technology and method for electronic pastes. At the same time, there are problems such as incomplete evaluation methods, high test repeatability, low efficiency, high cost, and low field matching, which greatly limits the product upgrade and technology iteration of electronic pastes. Summary of the invention
[0003] The present invention provides a centralized evaluation method applicable to multiple electronic pastes, the purpose of which is to solve the batch evaluation problem of the above-mentioned domestic pastes and better control the material performance. The method can be applied to the integrated, high-efficiency, low-cost, centralized evaluation of multiple batches, multiple functions, and multiple types of electronic pastes.
[0004] In the first aspect, a centralized evaluation method applicable to multiple electronic pastes is provided, including:
[0005] For N electronic pastes to be tested, a tic-tac-toe distribution integrated layout is designed, the layout includes N rows of printed lines and N columns of printed lines overlapping each other, the N rows of printed lines correspond to the N electronic pastes to be tested one by one, the N columns of printed lines correspond to the N electronic pastes to be tested one by one, and N is an integer greater than 2;
[0006] According to the designed layout, N electronic pastes to be tested are screen-printed on the substrate according to corresponding row printing lines and corresponding column printing lines;
[0007] The printed substrate is subjected to a multi-performance integrated test analysis, including an overall test and a section test. The section test is to section the substrate according to N columns of printing lines and conduct targeted tests on the overlapping interfaces of two pastes among the N electronic pastes to be tested.
[0008] In the second aspect, a centralized evaluation method applicable to multiple electronic pastes is provided, including:
[0009] For N+1 electronic pastes to be tested, a tic-tac-toe distribution integrated layout is designed, the layout includes N+1 rows of printed lines and N columns of printed lines overlapping each other, the N+1 rows of printed lines correspond one-to-one to the N+1 electronic pastes to be tested, the N+1 electronic pastes to be tested include dielectric pastes, the N columns of printed lines correspond one-to-one to the remaining N pastes in the N+1 electronic pastes to be tested except the dielectric paste, and N is an integer greater than 1;
[0010] According to the designed layout, the dielectric paste is printed on the substrate corresponding to the row 0 printing line, and the remaining N pastes except the dielectric paste among the N+1 electronic pastes to be tested are screen-printed on the substrate according to the corresponding row printing lines and the corresponding column printing lines respectively;
[0011] The printed substrate is subjected to multiple performance test analysis, including overall test and section test. The section test is to section the substrate according to N columns of printing lines and conduct targeted tests on the overlapping interfaces of two pastes in N+1 electronic pastes to be tested.
[0012] The third aspect provides a centralized evaluation method applicable to multiple electronic pastes, including:
[0013] For N+1 electronic pastes to be tested, a tic-tac-toe integrated layout is designed, the layout includes N rows of printed lines and N columns of printed lines overlapping each other, the N+1 electronic pastes to be tested include dielectric pastes, the N rows of printed lines and the N columns of printed lines correspond one to one to the remaining N pastes in the N+1 electronic pastes to be tested except the dielectric paste, and N is an integer greater than 1;
[0014] Print the dielectric paste surface on the test area of the substrate, and then screen-print the remaining N pastes except the dielectric paste among the N+1 electronic pastes to be tested on the substrate according to the corresponding row printing lines and the corresponding column printing lines according to the designed layout;
[0015] The printed substrate is subjected to multiple performance test analysis, including overall test and section test. The section test is to section the substrate according to N columns of printing lines and conduct targeted tests on the overlapping interfaces of two pastes in N+1 electronic pastes to be tested.
[0016] Fourthly, a centralized evaluation method applicable to multiple electronic pastes is provided, including:
[0017] For N+1 electronic pastes to be tested, a tic-tac-toe distribution integrated layout is designed, the layout includes N+1 rows of straight lines and N columns of straight lines overlapping each other, the N+1 rows of straight lines correspond one-to-one to the N+1 electronic pastes to be tested, the N+1 electronic pastes to be tested include dielectric paste, hole-filling paste, and soldering paste, the N columns of straight lines correspond one-to-one to the remaining N pastes except the dielectric paste in the N+1 electronic pastes to be tested, wherein the N-1 row of straight lines in the N+1 rows of straight lines is correspondingly designed as the N-1 row of printed lines, and the N-1 row of printed lines corresponds one-to-one to the remaining N-2 pastes except the hole-filling paste and the soldering paste in the N+1 electronic pastes to be tested, Among the remaining 2 row straight lines, the intersection of one row straight line and the N column straight line is designed as the hole filling gold paste printing position, and the intersection of the other row straight line and the N column straight line is designed as the soldering paste printing position; the N-2 column straight lines among the N column straight lines are correspondingly designed as the N-2 column printing lines, and the N-2 column printing lines correspond one to one to the remaining N-2 pastes except the dielectric paste, the hole filling paste, and the soldering paste among the N+1 electronic pastes to be tested, and among the remaining 2 column straight lines, the intersection of one column straight line and the N+1 row straight line is designed as the hole filling gold paste printing position, and the intersection of the other column straight line and the N+1 row straight line is designed as the soldering paste printing position, and N is an integer greater than 2;
[0018] According to the designed layout, the dielectric slurry is printed on the substrate corresponding to the straight line of row 0; for the hole-filling slurry, a hole is opened in the substrate or the dielectric layer formed by the dielectric slurry at the intersection position corresponding to the hole-filling slurry, and the hole-filling slurry is printed in the opening; for the welding slurry, the welding slurry is printed on the substrate or the dielectric layer formed by the dielectric slurry according to the intersection position corresponding to the welding slurry; the remaining N-2 slurries except the dielectric slurry, the hole-filling slurry and the welding slurry among the N+1 electronic slurries to be tested are screen-printed on the substrate according to the corresponding row printing lines and the corresponding column printing lines respectively;
[0019] The printed substrate is subjected to a multi-performance integrated test analysis, including an overall test and a section test. The section test is to section the substrate along N columns of straight lines and conduct targeted tests on the overlapping interfaces of two pastes in the N+1 electronic pastes to be tested.
[0020] In the fifth aspect, a centralized evaluation method applicable to multiple electronic pastes is provided, including:
[0021] For N+1 electronic pastes to be tested, a tic-tac-toe integrated layout is designed, the layout includes N rows of straight lines and N columns of straight lines overlapping each other, the N+1 electronic pastes to be tested include dielectric paste, hole-filling paste, and soldering paste, the N rows of straight lines correspond one-to-one to the remaining N pastes in the N+1 electronic pastes to be tested except the dielectric paste, the N columns of straight lines correspond one-to-one to the remaining N pastes in the N+1 electronic pastes to be tested except the dielectric paste, wherein N-2 rows of straight lines in the N rows of straight lines are correspondingly designed as N-2 rows of printed lines, and the N-2 rows of printed lines correspond to the remaining N-2 rows of printed lines in the N+1 electronic pastes to be tested except the dielectric paste, hole-filling paste, and soldering paste. 2 pastes correspond one to one, and in the remaining 2 row straight lines, the intersection of one row straight line and N column straight lines is designed as the hole filling gold paste printing position, and the intersection of the other row straight line and N column straight lines is designed as the soldering paste printing position; N-2 column straight lines in the N column straight lines are correspondingly designed as N-2 column printing lines, and the N-2 column printing lines correspond one to one with the remaining N-2 pastes except the dielectric paste, the hole filling paste, and the soldering paste in the N+1 electronic pastes to be tested, and in the remaining 2 column straight lines, the intersection of one column straight line and the N row straight line is designed as the hole filling gold paste printing position, and the intersection of the other column straight line and the N row straight line is designed as the soldering paste printing position, and N is an integer greater than 2;
[0022] According to the designed layout, the dielectric slurry is surface-printed on the test area of the substrate; for the hole-filling slurry, a hole is opened in the dielectric layer formed by the dielectric slurry at the intersection position corresponding to the hole-filling slurry, and the hole-filling slurry is printed in the opening; for the welding slurry, the welding slurry is printed on the dielectric layer formed by the dielectric slurry according to the intersection position corresponding to the welding slurry; the remaining N-2 slurries except the dielectric slurry, the hole-filling slurry and the welding slurry among the N+1 electronic slurries to be tested are screen-printed on the substrate according to the corresponding row printing lines and the corresponding column printing lines;
[0023] The printed substrate is subjected to a multi-performance integrated test analysis, including an overall test and a section test. The section test is to section the substrate along N columns of straight lines and conduct targeted tests on the overlapping interfaces of two pastes in the N+1 electronic pastes to be tested.
[0024] In combination with the first to fifth aspects, in certain implementations of the first to fifth aspects, the electronic paste to be tested includes multiple of surface paste, inner layer paste, hole filling paste, resistor paste, solder paste, dielectric paste, conductor paste, and encapsulation paste.
[0025] In combination with the first to fifth aspects, in certain implementations of the first to fifth aspects, a multi-performance integrated test and analysis is performed on the printed substrate, including simultaneous testing and analysis of multiple slurries in terms of interface matching, warpage, microwave loss, and film forming quality.
[0026] In combination with the first to fifth aspects, in certain implementations of the first to fifth aspects, the printing order of the electronic paste to be tested is dielectric paste->hole filling paste->resistor paste->inner layer paste->surface layer paste->soldering paste.
[0027] In combination with the first to fifth aspects, in certain implementations of the first to fifth aspects, samples used for multi-performance set testing and analysis are prepared by screen printing and sintering, wherein the drying temperature after printing is 70-80°C, the drying time is 10-15 minutes, the sintering peak temperature is 840-860°C, and the peak temperature duration is 10-20 minutes.
[0028] In combination with the first aspect to the fifth aspect, in some implementations of the first aspect to the fifth aspect, the method further includes:
[0029] When the multi-performance test analysis is passed, the electronic paste that has passed the evaluation is used to prepare a circuit board with a special printed layout.
[0030] Compared with the prior art, the solution provided by the present invention includes at least the following beneficial technical effects:
[0031] This integrated evaluation method can realize the integrated design and manufacturing of large-scale, multi-category, and multi-functional electronic pastes, as well as high-efficiency and low-cost testing, evaluation and analysis of various performances. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] Figure 1 A tic-tac-toe schematic diagram of an integrated layout design involved in this evaluation method.
[0033] Figure 2 It is a special screen printing layout. DETAILED DESCRIPTION
[0034] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.
[0035] The present invention provides a centralized evaluation method applicable to multiple types of electronic pastes, and the specific steps are as follows.
[0036] Step 101, such as Figure 1 As shown, for N electronic pastes to be tested, a tic-tac-toe distribution integrated layout is designed, the layout includes N rows of printed lines and N columns of printed lines overlapping each other, the N rows of printed lines correspond one-to-one to the N electronic pastes to be tested, the N columns of printed lines correspond one-to-one to the N electronic pastes to be tested, and N is an integer greater than 2.
[0037] The N electronic pastes to be tested may include multiple of surface paste, inner layer paste, hole filling paste, resistor paste, solder paste, dielectric paste, conductor paste, and encapsulation paste. The pastes can be divided into electronic paste for LTCC and thick film electronic paste for integrated circuits, and the paste components include gold paste, silver paste, copper paste, gold platinum palladium paste, etc.
[0038] In one embodiment, the N electronic pastes to be tested may include dielectric paste, hole filling paste, resistor paste, inner layer paste, surface layer paste, and solder paste. Among them, 1 row of printed lines and 1 column of printed lines correspond to dielectric paste; 2 rows of printed lines and 2 columns of printed lines correspond to hole filling paste; 3 rows of printed lines and 3 columns of printed lines correspond to resistor paste; 4 rows of printed lines and 4 columns of printed lines correspond to inner layer paste; 5 rows of printed lines and 5 columns of printed lines correspond to surface layer paste; 1 row of printed lines and 1 column of printed lines correspond to solder paste.
[0039] Step 102 , according to the layout designed in step 101 , screen-print N electronic pastes to be tested on the substrate according to corresponding row printing lines and corresponding column printing lines.
[0040] In one embodiment, after the target electronic paste among the N electronic pastes to be tested is stirred evenly, the target electronic paste is screen-printed on the substrate according to the layout, so that the N electronic pastes to be tested are finally overlapped with each other. After printing, it is placed horizontally for no less than 10 minutes, then placed in a 75°C drying oven for 10 minutes, and then the substrate is sintered in a tunnel furnace with a sintering peak temperature of 850°C and a duration of 15 minutes, and then cooled to room temperature after sintering.
[0041] In one embodiment, the printing order of the N electronic pastes to be tested may be dielectric paste->hole filling paste->resistor paste->inner layer paste->surface layer paste->soldering paste.
[0042] Step 103, performing a multi-performance integrated test analysis on the printed substrate, including an overall test and a section test, wherein the section test is to section the substrate according to N columns of printed lines and perform targeted tests on the overlapping interfaces of two pastes among the N electronic pastes to be tested.
[0043] The warpage and microwave loss tests can be performed on the entire substrate sample containing N electronic pastes to be tested.
[0044] The produced substrate is sliced and observed to produce N metallographic samples, which may include the interface where any two of the N electronic pastes to be tested overlap each other. A microscope is used to test the interface matching at the overlapped part and the film quality at the non-overlapped part, and the pairwise matching and quality of N pastes can be observed at the same time, eliminating the repetitiveness and inefficiency of preparing samples and testing each paste separately, and integrating them into one for collective evaluation and analysis.
[0045] The present invention also provides a centralized evaluation method applicable to multiple types of electronic pastes, and the specific steps are as follows.
[0046] Step 201, for N+1 electronic pastes to be tested, design a tic-tac-toe distribution integrated layout, the layout includes N+1 rows of printed lines and N columns of printed lines overlapping each other, the N+1 rows of printed lines correspond one-to-one to the N+1 electronic pastes to be tested, the N+1 electronic pastes to be tested include dielectric pastes, the N columns of printed lines correspond one-to-one to the remaining N pastes in the N+1 electronic pastes to be tested except the dielectric pastes, and N is an integer greater than 1.
[0047] The pastes other than the dielectric paste in the N+1 electronic pastes to be tested may include multiple of the surface paste, inner layer paste, hole filling paste, resistor paste, solder paste, conductor paste, and encapsulation paste. The pastes can be divided into electronic pastes for LTCC and thick film electronic pastes for integrated circuits, and the paste components include gold paste, silver paste, copper paste, gold platinum palladium paste, etc.
[0048] In one embodiment, N+1 electronic pastes to be tested may include dielectric paste, hole filling paste, resistor paste, inner layer paste, surface layer paste, and solder paste. Wherein 0 rows of printed lines correspond to dielectric paste; 1 row of printed lines and 1 column of printed lines correspond to hole filling paste; 2 rows of printed lines and 2 columns of printed lines correspond to resistor paste; 3 rows of printed lines and 3 columns of printed lines correspond to inner layer paste; 4 rows of printed lines and 4 columns of printed lines correspond to surface layer paste; 5 rows of printed lines and 5 columns of printed lines correspond to solder paste.
[0049] Step 202, according to the layout designed in step 201, print the dielectric paste corresponding to row 0 printing line on the substrate, and screen print the remaining N pastes except the dielectric paste among the N+1 electronic pastes to be tested on the substrate according to the corresponding row printing lines and the corresponding column printing lines.
[0050] In one embodiment, after the target electronic paste among the N+1 electronic pastes to be tested is stirred evenly, the target electronic paste is screen-printed on the substrate according to the layout, so that the N+1 rows of printed lines and the N columns of printed lines are finally overlapped with each other. After printing, it is placed horizontally for no less than 10 minutes, then placed in a 75°C drying oven for 10 minutes, and then the substrate is sintered in a tunnel furnace, with a sintering peak temperature of 850°C and a duration of 15 minutes, and then cooled to room temperature after sintering.
[0051] In one embodiment, the printing order of the N+1 electronic pastes to be tested may be dielectric paste->hole filling paste->resistor paste->inner layer paste->surface layer paste->soldering paste.
[0052] Step 203, performing a multi-performance integrated test analysis on the printed substrate, including an overall test and a section test, wherein the section test is to section the substrate according to N columns of printed lines, and perform targeted tests on the overlapping interfaces of two pastes in N+1 electronic pastes to be tested.
[0053] The warpage and microwave loss tests can be performed on the substrate sample including N+1 electronic pastes to be tested.
[0054] The produced substrate is sliced and observed to produce N metallographic samples, which may include the interface where any two of the N+1 electronic pastes to be tested overlap each other. A microscope is used to test the interface matching at the overlap and the film quality at the non-overlap, and the matching and quality of the pastes can be observed simultaneously, eliminating the repetitiveness and inefficiency of preparing samples and testing each paste separately, and integrating them into one for collective evaluation and analysis.
[0055] The present invention also provides a centralized evaluation method applicable to multiple types of electronic pastes, and the specific steps are as follows.
[0056] Step 301, for N+1 electronic pastes to be tested, design a tic-tac-toe distribution integrated layout, the layout includes N rows of printed lines and N columns of printed lines overlapping each other, the N+1 electronic pastes to be tested include dielectric pastes, the N rows of printed lines and the N columns of printed lines correspond one-to-one to the remaining N pastes in the N+1 electronic pastes to be tested except the dielectric paste, and N is an integer greater than 1.
[0057] The pastes other than the dielectric paste in the N+1 electronic pastes to be tested may include multiple of the surface paste, inner layer paste, hole filling paste, resistor paste, solder paste, conductor paste, and encapsulation paste. The pastes can be divided into electronic pastes for LTCC and thick film electronic pastes for integrated circuits, and the paste components include gold paste, silver paste, copper paste, gold platinum palladium paste, etc.
[0058] In one embodiment, N+1 electronic pastes to be tested may include dielectric paste, hole filling paste, resistor paste, inner layer paste, surface layer paste, and solder paste. Among them, 1 row of printed lines and 1 column of printed lines correspond to hole filling paste; 2 rows of printed lines and 2 columns of printed lines correspond to resistor paste; 3 rows of printed lines and 3 columns of printed lines correspond to inner layer paste; 4 rows of printed lines and 4 columns of printed lines correspond to surface layer paste; 5 rows of printed lines and 5 columns of printed lines correspond to solder paste.
[0059] Step 302, print the dielectric paste surface on the test area of the substrate, and then screen-print the remaining N pastes except the dielectric paste among the N+1 electronic pastes to be tested on the substrate according to the corresponding row printing lines and the corresponding column printing lines according to the layout designed in step 301.
[0060] In one embodiment, after the target electronic paste among the N+1 electronic pastes to be tested is stirred evenly, the target electronic paste is printed on the substrate according to the requirements of step 302, so that the N rows of printed lines and the N columns of printed lines are overlapped with each other. After printing, it is placed horizontally for no less than 10 minutes, then placed in a 75°C drying oven for 10 minutes, and then the substrate is sintered in a tunnel furnace with a sintering peak temperature of 850°C and a duration of 15 minutes, and then cooled to room temperature after sintering.
[0061] In one embodiment, the printing order of the N+1 electronic pastes to be tested may be dielectric paste->hole filling paste->resistor paste->inner layer paste->surface layer paste->soldering paste.
[0062] Step 303, performing a multi-performance integrated test analysis on the printed substrate, including an overall test and a section test, wherein the section test is to section the substrate according to N columns of printed lines, and perform targeted tests on the overlapping interfaces of two pastes in N+1 electronic pastes to be tested.
[0063] The warpage and microwave loss tests can be performed on the substrate sample including N+1 electronic pastes to be tested.
[0064] The produced substrate is sliced and observed to produce N metallographic samples, which may include the interface where any two of the N+1 electronic pastes to be tested overlap each other. A microscope is used to test the interface matching at the overlap and the film quality at the non-overlap, and the matching and quality of the pastes can be observed simultaneously, eliminating the repetitiveness and inefficiency of preparing samples and testing each paste separately, and integrating them into one for collective evaluation and analysis.
[0065] The present invention also provides a centralized evaluation method applicable to multiple types of electronic pastes, and the specific steps are as follows.
[0066] Step 401, for N+1 electronic pastes to be tested, design a tic-tac-toe distribution integrated layout, the layout includes N+1 rows of straight lines and N columns of straight lines overlapping each other, the N+1 rows of straight lines correspond one-to-one to the N+1 electronic pastes to be tested, the N+1 electronic pastes to be tested include dielectric paste, hole-filling paste, and soldering paste, the N columns of straight lines correspond one-to-one to the remaining N pastes in the N+1 electronic pastes to be tested except the dielectric paste, wherein the N-1 row of straight lines in the N+1 rows of straight lines is correspondingly designed as the N-1 row of printed lines, and the N-1 row of printed lines corresponds one-to-one to the remaining N-2 pastes in the N+1 electronic pastes to be tested except the hole-filling paste and the soldering paste. Correspondingly, among the remaining 2 row straight lines, the intersection of one row straight line and the N column straight line is designed as the hole-filling gold paste printing position, and the intersection of the other row straight line and the N column straight line is designed as the soldering paste printing position; the N-2 column straight lines among the N column straight lines are correspondingly designed as N-2 column printing lines, and the N-2 column printing lines correspond one-to-one to the remaining N-2 pastes among the N+1 electronic pastes to be tested except the dielectric paste, the hole-filling paste, and the soldering paste. Among the remaining 2 column straight lines, the intersection of one column straight line and the N+1 row straight line is designed as the hole-filling gold paste printing position, and the intersection of the other column straight line and the N+1 row straight line is designed as the soldering paste printing position, and N is an integer greater than 2.
[0067] The N+1 electronic pastes to be tested may include multiple of surface paste, inner layer paste, hole filling paste, resistor paste, solder paste, dielectric paste, conductor paste, and encapsulation paste. The pastes can be divided into electronic pastes for LTCC and thick film electronic pastes for integrated circuits. The paste components include gold paste, silver paste, copper paste, gold platinum palladium paste, etc.
[0068] In one embodiment, N+1 electronic pastes to be tested may include dielectric paste, hole-filling paste, resistor paste, inner layer paste, surface layer paste, and solder paste. Wherein, 0 rows of straight lines (corresponding to row printing line 0) correspond to the setting of dielectric paste; the intersection positions on 1 row of straight lines and the intersection positions on 1 column of straight lines both correspond to the setting of hole-filling paste; 2 rows of straight lines (corresponding to row printing line 1) and 2 columns of straight lines (corresponding to column printing line 1) correspond to resistor paste; 3 rows of straight lines (corresponding to row printing line 2) and 3 columns of straight lines (corresponding to column printing line 2) correspond to inner layer paste; 4 rows of straight lines (corresponding to row printing line 3) and 4 columns of straight lines (corresponding to column printing line 3) correspond to surface layer paste; the intersection positions on 5 rows of straight lines and the intersection positions on 5 columns of straight lines both correspond to solder paste.
[0069] Step 402, according to the layout designed in step 401, print the dielectric slurry corresponding to row 0 on the substrate, for the hole-filling slurry, open a hole in the dielectric layer formed by the substrate or the dielectric slurry at the intersection position corresponding to the hole-filling slurry, and print the hole-filling slurry in the opening; for the welding slurry, print the welding slurry on the dielectric layer formed by the substrate or the dielectric slurry according to the intersection position corresponding to the welding slurry; screen-print the remaining N-2 slurries except the dielectric slurry, hole-filling slurry and welding slurry among the N+1 electronic slurries to be tested on the substrate according to the corresponding row printing lines and the corresponding column printing lines.
[0070] In one embodiment, after the target electronic paste in the N+1 electronic pastes to be tested is stirred evenly, the target electronic paste is screen-printed on the substrate according to the layout, so that all the row printing lines and all the column printing lines overlap each other, and the hole filling paste and the welding paste overlap each other. After printing, it is placed horizontally for no less than 10 minutes, then placed in a 75°C drying oven for 10 minutes, and then the substrate is sintered in a tunnel furnace, with a sintering peak temperature of 850°C and a duration of 15 minutes, and then cooled to room temperature after sintering.
[0071] In one embodiment, the printing order of the N+1 electronic pastes to be tested may be dielectric paste->hole filling paste->resistor paste->inner layer paste->surface layer paste->soldering paste.
[0072] Step 403, performing a multi-performance integrated test analysis on the printed substrate, including an overall test and a section test, wherein the section test is to section the substrate along N columns of straight lines and perform targeted tests on the overlapping interfaces of two pastes in N+1 electronic pastes to be tested.
[0073] The warpage and microwave loss tests can be performed on the substrate sample including N+1 electronic pastes to be tested.
[0074] The produced substrate is sliced and observed to produce N metallographic samples, which may include the interface where any two of the N+1 electronic pastes to be tested overlap each other. A microscope is used to test the interface matching at the overlap and the film quality at the non-overlap, and the matching and quality of the pastes can be observed simultaneously, eliminating the repetitiveness and inefficiency of preparing samples and testing each paste separately, and integrating them into one for collective evaluation and analysis.
[0075] The present invention also provides a centralized evaluation method applicable to multiple types of electronic pastes, and the specific steps are as follows.
[0076] Step 501, for N+1 electronic pastes to be tested, design a tic-tac-toe integrated layout, the layout includes N rows of straight lines and N columns of straight lines overlapping each other, the N+1 electronic pastes to be tested include dielectric paste, hole filling paste, and soldering paste, the N rows of straight lines correspond one-to-one to the remaining N pastes in the N+1 electronic pastes to be tested except the dielectric paste, the N columns of straight lines correspond one-to-one to the remaining N pastes in the N+1 electronic pastes to be tested except the dielectric paste, wherein N-2 rows of straight lines in the N rows of straight lines are correspondingly designed as N-2 rows of printed lines, and the N-2 rows of printed lines correspond to the remaining N pastes in the N+1 electronic pastes to be tested except the dielectric paste, the hole filling paste, and the soldering paste. The remaining N-2 pastes correspond one to one, and among the remaining 2 row straight lines, the intersection of one row straight line and the N column straight line is designed as the printing position of the hole-filling gold paste, and the intersection of the other row straight line and the N column straight line is designed as the printing position of the soldering paste; the N-2 column straight lines in the N column straight lines are correspondingly designed as N-2 column printing lines, and the N-2 column printing lines correspond one to one with the remaining N-2 pastes except the dielectric paste, the hole-filling paste and the soldering paste in the N+1 electronic pastes to be tested, and among the remaining 2 column straight lines, the intersection of one column straight line and the N row straight line is designed as the printing position of the hole-filling gold paste, and the intersection of the other column straight line and the N row straight line is designed as the printing position of the soldering paste, and N is an integer greater than 2.
[0077] The N+1 electronic pastes to be tested may include multiple of surface paste, inner layer paste, hole filling paste, resistor paste, solder paste, dielectric paste, conductor paste, and encapsulation paste. The pastes can be divided into electronic pastes for LTCC and thick film electronic pastes for integrated circuits. The paste components include gold paste, silver paste, copper paste, gold platinum palladium paste, etc.
[0078] In one embodiment, N+1 electronic pastes to be tested may include dielectric paste, hole-filling paste, resistor paste, inner layer paste, surface layer paste, and solder paste. The intersection positions on 1 row of straight lines and the intersection positions on 1 column of straight lines correspond to the hole-filling paste; 2 rows of straight lines (corresponding to row printed line 1) and 2 columns of straight lines (corresponding to column printed line 1) correspond to resistor paste; 3 rows of straight lines (corresponding to row printed line 2) and 3 columns of straight lines (corresponding to column printed line 2) correspond to inner layer paste; 4 rows of straight lines (corresponding to row printed line 3) and 4 columns of straight lines (corresponding to column printed line 3) correspond to surface layer paste; the intersection positions on 5 rows of straight lines and the intersection positions on 5 columns of straight lines correspond to solder paste.
[0079] Step 502, according to the layout designed in step 501, print the dielectric slurry surface on the test area of the substrate, for the hole filling slurry, open a hole in the dielectric layer formed by the dielectric slurry at the intersection position corresponding to the hole filling slurry, and print the hole filling slurry in the opening; for the welding slurry, print the welding slurry on the dielectric layer formed by the dielectric slurry according to the intersection position corresponding to the welding slurry; screen print the remaining N-2 slurries except the dielectric slurry, hole filling slurry and welding slurry among the N+1 electronic slurries to be tested on the substrate according to the corresponding row printing lines and the corresponding column printing lines.
[0080] In one embodiment, after the target electronic paste in the N+1 electronic pastes to be tested is stirred evenly, the target electronic paste is screen-printed on the substrate according to the layout, so that all the row printing lines and all the column printing lines are overlapped with each other, and the hole filling paste and the welding paste are printed in the corresponding positions. After printing, it is placed horizontally for no less than 10 minutes, then placed in a 75°C drying oven for 10 minutes, and then the substrate is sintered in a tunnel furnace, with a sintering peak temperature of 850°C and a duration of 15 minutes, and then cooled to room temperature after sintering.
[0081] In one embodiment, the printing order of the N+1 electronic pastes to be tested may be dielectric paste->hole filling paste->resistor paste->inner layer paste->surface layer paste->soldering paste.
[0082] Step 503, performing a multi-performance integrated test analysis on the printed substrate, including an overall test and a section test, wherein the section test is to section the substrate along N columns of straight lines and perform targeted tests on the overlapping interfaces of two pastes in N+1 electronic pastes to be tested.
[0083] The warpage and microwave loss tests can be performed on the substrate sample including N+1 electronic pastes to be tested.
[0084] The produced substrate is sliced and observed to produce N metallographic samples, which may include the interface where any two of the N+1 electronic pastes to be tested overlap each other. A microscope is used to test the interface matching at the overlap and the film quality at the non-overlap, and the matching and quality of the pastes can be observed simultaneously, eliminating the repetitiveness and inefficiency of preparing samples and testing each paste separately, and integrating them into one for collective evaluation and analysis.
[0085] In the above evaluation method, multiple performance tests and analyses are performed on the printed substrate, including simultaneous testing and analysis of multiple slurries in terms of interface matching, warpage, microwave loss, film forming quality, etc.
[0086] In the above evaluation method, the samples used for the multi-performance set test and analysis are prepared by screen printing and sintering, wherein the drying temperature after printing is 70-80°C, the drying time is 10-15 minutes, the sintering peak temperature is 840-860°C, and the peak temperature duration is 10-20 minutes.
[0087] The electronic paste evaluated by the above method is used to prepare circuit boards with special printing layouts, such as Figure 2 It has been verified that the electronic paste that has passed the evaluation by the above method can also meet the product requirements when preparing circuit boards with special printing layouts.
[0088] Comparative Example 1
[0089] This comparative example provides a conventional evaluation method for 6 LTCC electronic pastes, which includes the following steps:
[0090] 1) Import the single pattern printing layout into the screen printer computer;
[0091] 2) Choose one slurry and stir it evenly, screen print it on the substrate according to the layout, place it horizontally for no less than 10 minutes after printing, then put it into a 75℃ drying oven for 10 minutes, and then use a tunnel furnace to sinter the substrate, the sintering peak temperature is 850℃, the duration is 15 minutes, and cool it to room temperature after sintering;
[0092] 3) Select one slurry and stir it evenly, print it on the same substrate according to the above steps, and sinter it to obtain overlapping samples; the remaining slurries are printed in the same way, and sintered together to obtain 15 substrate samples in total;
[0093] 4) The 15 substrates were tested for warpage and microwave loss, and their cross-sections were observed. After the metallographic samples were made, the interface matching of the overlapped parts and the film quality of the non-overlapped parts were tested under a microscope. The 15 samples prepared need to be observed and tested separately, which is labor-intensive, highly repetitive, inefficient, and has high test costs.
[0094] Although the present invention is disclosed as above in the form of a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art may make possible changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on the scope defined by the claims of the present invention.
Claims
1. A collective evaluation method applicable to multiple electronic pastes, characterized in that: include: For N electronic pastes to be tested, a tic-tac-toe distribution integrated layout is designed, the layout includes N rows of printed lines and N columns of printed lines overlapping each other, the N rows of printed lines correspond to the N electronic pastes to be tested one by one, the N columns of printed lines correspond to the N electronic pastes to be tested one by one, and N is an integer greater than 2; According to the designed layout, N electronic pastes to be tested are screen-printed on the substrate according to corresponding row printing lines and corresponding column printing lines; The printed substrate is subjected to a multi-performance integrated test analysis, including an overall test and a section test. The section test is to section the substrate according to N columns of printing lines and conduct targeted tests on the overlapping interfaces of two pastes among the N electronic pastes to be tested.
2. A collective evaluation method applicable to multiple electronic pastes, characterized in that: include: For N+1 electronic pastes to be tested, a tic-tac-toe distribution integrated layout is designed, the layout includes N+1 rows of printed lines and N columns of printed lines overlapping each other, the N+1 rows of printed lines correspond one-to-one to the N+1 electronic pastes to be tested, the N+1 electronic pastes to be tested include dielectric pastes, the N columns of printed lines correspond one-to-one to the remaining N pastes in the N+1 electronic pastes to be tested except the dielectric paste, and N is an integer greater than 1; According to the designed layout, the dielectric paste is printed on the substrate corresponding to the row 0 printing line, and the remaining N pastes except the dielectric paste among the N+1 electronic pastes to be tested are screen-printed on the substrate according to the corresponding row printing lines and the corresponding column printing lines respectively; The printed substrate is subjected to multiple performance test analysis, including overall test and section test. The section test is to section the substrate according to N columns of printing lines and conduct targeted tests on the overlapping interfaces of two pastes in N+1 electronic pastes to be tested.
3. A collective evaluation method applicable to multiple electronic pastes, characterized in that: include: For N+1 electronic pastes to be tested, a tic-tac-toe integrated layout is designed, the layout includes N rows of printed lines and N columns of printed lines overlapping each other, the N+1 electronic pastes to be tested include dielectric pastes, the N rows of printed lines and the N columns of printed lines correspond one to one to the remaining N pastes in the N+1 electronic pastes to be tested except the dielectric paste, and N is an integer greater than 1; Print the dielectric paste surface on the test area of the substrate, and then screen-print the remaining N pastes except the dielectric paste among the N+1 electronic pastes to be tested on the substrate according to the corresponding row printing lines and the corresponding column printing lines according to the designed layout; The printed substrate is subjected to multiple performance test analysis, including overall test and section test. The section test is to section the substrate according to N columns of printing lines and conduct targeted tests on the overlapping interfaces of two pastes in N+1 electronic pastes to be tested.
4. A collective evaluation method applicable to multiple electronic pastes, characterized in that: include: For N+1 electronic pastes to be tested, a tic-tac-toe distribution integrated layout is designed, the layout includes N+1 rows of straight lines and N columns of straight lines overlapping each other, the N+1 rows of straight lines correspond one-to-one to the N+1 electronic pastes to be tested, the N+1 electronic pastes to be tested include dielectric paste, hole-filling paste, and soldering paste, the N columns of straight lines correspond one-to-one to the remaining N pastes except the dielectric paste in the N+1 electronic pastes to be tested, wherein the N-1 row of straight lines in the N+1 rows of straight lines is correspondingly designed as the N-1 row of printed lines, and the N-1 row of printed lines corresponds one-to-one to the remaining N-2 pastes except the hole-filling paste and the soldering paste in the N+1 electronic pastes to be tested, Among the remaining 2 row straight lines, the intersection of one row straight line and the N column straight line is designed as the hole filling gold paste printing position, and the intersection of the other row straight line and the N column straight line is designed as the soldering paste printing position; the N-2 column straight lines among the N column straight lines are correspondingly designed as the N-2 column printing lines, and the N-2 column printing lines correspond one to one to the remaining N-2 pastes except the dielectric paste, the hole filling paste, and the soldering paste among the N+1 electronic pastes to be tested, and among the remaining 2 column straight lines, the intersection of one column straight line and the N+1 row straight line is designed as the hole filling gold paste printing position, and the intersection of the other column straight line and the N+1 row straight line is designed as the soldering paste printing position, and N is an integer greater than 2; According to the designed layout, the dielectric slurry is printed on the substrate corresponding to the straight line of row 0; for the hole-filling slurry, a hole is opened in the substrate or the dielectric layer formed by the dielectric slurry at the intersection position corresponding to the hole-filling slurry, and the hole-filling slurry is printed in the opening; for the welding slurry, the welding slurry is printed on the substrate or the dielectric layer formed by the dielectric slurry according to the intersection position corresponding to the welding slurry; the remaining N-2 slurries except the dielectric slurry, the hole-filling slurry and the welding slurry among the N+1 electronic slurries to be tested are screen-printed on the substrate according to the corresponding row printing lines and the corresponding column printing lines respectively; The printed substrate is subjected to a multi-performance integrated test analysis, including an overall test and a section test. The section test is to section the substrate along N columns of straight lines and conduct targeted tests on the overlapping interfaces of two pastes in the N+1 electronic pastes to be tested.
5. A collective evaluation method applicable to multiple electronic pastes, characterized in that: include: For N+1 electronic pastes to be tested, a tic-tac-toe integrated layout is designed, the layout includes N rows of straight lines and N columns of straight lines overlapping each other, the N+1 electronic pastes to be tested include dielectric paste, hole-filling paste, and soldering paste, the N rows of straight lines correspond one-to-one to the remaining N pastes in the N+1 electronic pastes to be tested except the dielectric paste, the N columns of straight lines correspond one-to-one to the remaining N pastes in the N+1 electronic pastes to be tested except the dielectric paste, wherein N-2 rows of straight lines in the N rows of straight lines are correspondingly designed as N-2 rows of printed lines, and the N-2 rows of printed lines correspond to the remaining N-2 rows of printed lines in the N+1 electronic pastes to be tested except the dielectric paste, hole-filling paste, and soldering paste. 2 pastes correspond one to one, and in the remaining 2 row straight lines, the intersection of one row straight line and N column straight lines is designed as the hole filling gold paste printing position, and the intersection of the other row straight line and N column straight lines is designed as the soldering paste printing position; N-2 column straight lines in the N column straight lines are correspondingly designed as N-2 column printing lines, and the N-2 column printing lines correspond one to one with the remaining N-2 pastes except the dielectric paste, the hole filling paste, and the soldering paste in the N+1 electronic pastes to be tested, and in the remaining 2 column straight lines, the intersection of one column straight line and the N row straight line is designed as the hole filling gold paste printing position, and the intersection of the other column straight line and the N row straight line is designed as the soldering paste printing position, and N is an integer greater than 2; According to the designed layout, the dielectric slurry is surface-printed on the test area of the substrate; for the hole-filling slurry, a hole is opened in the dielectric layer formed by the dielectric slurry at the intersection position corresponding to the hole-filling slurry, and the hole-filling slurry is printed in the opening; for the welding slurry, the welding slurry is printed on the dielectric layer formed by the dielectric slurry according to the intersection position corresponding to the welding slurry; the remaining N-2 slurries except the dielectric slurry, the hole-filling slurry and the welding slurry among the N+1 electronic slurries to be tested are screen-printed on the substrate according to the corresponding row printing lines and the corresponding column printing lines; The printed substrate is subjected to a multi-performance integrated test analysis, including an overall test and a section test. The section test is to section the substrate along N columns of straight lines and conduct targeted tests on the overlapping interfaces of two pastes in the N+1 electronic pastes to be tested.
6. The method according to any one of claims 1 to 5, characterized in that The electronic paste to be tested includes multiple ones of surface paste, inner layer paste, hole filling paste, resistor paste, solder paste, dielectric paste, conductor paste and encapsulation paste.
7. The method according to any one of claims 1 to 6, characterized in that The printed substrate is subjected to a multi-performance integrated test and analysis, including the simultaneous testing and analysis of multiple slurries in terms of interface matching, warpage, microwave loss, and film forming quality.
8. The method according to claim 7, characterized in that The printing order of the electronic paste to be tested is dielectric paste -> hole filling paste -> resistor paste -> inner layer paste -> surface layer paste -> soldering paste.
9. The method according to any one of claims 1 to 8, characterized in that The samples used for multi-performance set test and analysis were prepared by screen printing and sintering, wherein the drying temperature after printing was 70-80°C, the drying time was 10-15 minutes, the sintering peak temperature was 840-860°C, and the peak temperature duration was 10-20 minutes.
10. The method according to any one of claims 1 to 9, characterized in that The method further comprises: When the multi-performance test analysis is passed, the electronic paste that has passed the evaluation is used to prepare a circuit board with a special printed layout.