Method, device and equipment for testing chip pulse width, and testing machine

Abstract

The present application relates to the field of chip testing technology, and discloses a chip pulse width testing method, device, equipment, and testing machine. The testing method includes: constructing a test pattern according to the configuration information input by the user; wherein the test pattern defines the set voltage, set frequency, multiple analog quantity gears, and output pins of the chip to be tested when testing the chip to be tested; writing the test pattern into the register of the chip to be tested, collecting the number of low levels output by the output pin at each analog quantity gear; calculating the pulse width of the chip to be tested at each analog quantity gear according to the set frequency and the number of low levels output at each analog quantity gear. The present application can improve the efficiency of the pulse width test of the chip.

Description

Technical Field

[0001] The present application relates to the field of chip testing technology, for example, to a chip pulse width testing method, device, equipment, and testing machine. Background Art

[0002] Pulse width is an important indicator of signal transmission quality. In the digital circuit of the chip, pulse width determines whether the signal can be correctly identified and processed. If the pulse width is too narrow, it may cause the signal to be distorted or misidentified during transmission. Therefore, after the chip is produced, the pulse width of the chip needs to be tested.

[0003] In the related art, the pulse width of a chip is tested by inputting a signal of an analog quantity level into the chip each time, and then measuring the pulse width of the chip through an oscilloscope.

[0004] In the process of implementing the embodiments of the present disclosure, it is found that there are at least the following problems in the related art:

[0005] The pulse width test of the chip needs to measure the pulse width performance of the chip under multiple analog gears. The solution of the related art can only measure the pulse width of the chip under one analog gear at a time, which leads to low efficiency of the chip pulse width test. Therefore, how to improve the efficiency of the chip pulse width test has become a technical problem that needs to be solved urgently.

[0006] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present application, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0007] In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. The summary is not an extensive review, nor is it intended to identify key / critical components or delineate the scope of protection of these embodiments, but rather serves as a prelude to the detailed description that follows.

[0008] The embodiments of the present disclosure provide a chip pulse width testing method, device, equipment, and testing machine, which can improve the efficiency of chip pulse width testing.

[0009] In some embodiments, a test method for chip pulse width includes: constructing a test pattern based on configuration information input by a user; wherein the test pattern defines a set voltage, a set frequency, multiple analog quantity levels and an output pin of the chip to be tested when testing the chip to be tested; writing the test pattern into a register of the chip to be tested, collecting the number of low levels output by the output pin at each analog quantity level; and calculating the pulse width of the chip to be tested at each analog quantity level based on the set frequency and the number of low levels output at each analog quantity level.

[0010] Optionally, a test pattern is constructed based on the configuration information input by the user, including: parsing the configuration information input by the user to determine the set voltage, set frequency, multiple analog quantity gears and output pins of the chip to be tested when testing the chip to be tested; verifying the rationality of the set voltage, set frequency, multiple analog quantity gears and output pins according to the specification information of the chip to be tested; and if the verification passes, converting the set voltage, set frequency, multiple analog quantity gears and output pins into a test pattern.

[0011] Optionally, according to the set frequency and the number of low-level outputs at each analog quantity level, the pulse width of the chip under test at each analog quantity level is calculated according to the following expression:

[0012]

[0013] Among them, time is the pulse width of the chip under test in the current analog gear, count is the number of low levels output by the chip under test in the current analog gear, and F is the set frequency.

[0014] Optionally, after calculating the pulse width of the chip under test at each analog quantity level, the testing method further includes: displaying the pulse width of the chip under test at each analog quantity level in the form of a chart.

[0015] Optionally, after calculating the pulse width of the chip under test at each analog quantity level, the testing method further includes: comparing the pulse width of the chip under test at each analog quantity level with the expected pulse width at each analog quantity level to obtain a comparison result; and generating a performance evaluation report of the chip under test based on the comparison result.

[0016] Optionally, the testing method further includes: obtaining the pulse width of all chips to be tested in the wafer to be tested at each analog quantity level; and determining the yield rate of the chips in the wafer to be tested according to the pulse width of all chips to be tested at each analog quantity level.

[0017] Optionally, the pulse width test of all chips to be tested in the wafer to be tested is performed in parallel based on the constructed test pattern.

[0018] In some embodiments, a chip pulse width testing device includes: a construction module, configured to construct a test pattern according to configuration information input by a user; wherein the test pattern defines a set voltage, a set frequency, multiple analog quantity gears and an output pin of the chip to be tested when testing the chip to be tested; an acquisition module, configured to write the test pattern into a register of the chip to be tested, and to acquire the number of low levels output by the output pin at each analog quantity gear; and a calculation module, configured to calculate the pulse width of the chip to be tested at each analog quantity gear according to the set frequency and the number of low levels output at each analog quantity gear.

[0019] In some embodiments, a chip pulse width testing device includes a processor and a memory storing program instructions, and the processor is configured to execute the chip pulse width testing method as described above when running the program instructions.

[0020] In some embodiments, a testing machine includes: a machine body; a testing device for chip pulse width as described above, or a testing equipment for chip pulse width as described above, which is arranged on the machine body.

[0021] The chip pulse width testing method, device, equipment, and testing machine provided by the embodiments of the present disclosure can achieve the following technical effects:

[0022] In the embodiment of the present disclosure, a test pattern can be constructed according to the configuration information input by the user including the set voltage, set frequency, multiple analog quantity gears and output pins of the chip to be tested when testing the chip to be tested. By writing the test pattern into the register of the chip to be tested and collecting the number of low levels output by the output pin at each analog quantity gear, the pulse width of the chip to be tested at each analog quantity gear can be calculated to complete the test of the chip pulse width. In this way, during the test process, automatic switching of different analog quantity gears is achieved, and batch measurement of pulse widths at different analog quantity gears is achieved. Therefore, the embodiment of the present disclosure can improve the efficiency of the pulse width test of the chip.

[0023] The above general description and the following description are exemplary and explanatory only and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] One or more embodiments are exemplarily described by corresponding drawings, which do not limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements, and the drawings do not constitute a scale limitation, and wherein:

[0025] Figure 1is a schematic diagram of a test machine provided by an embodiment of the present disclosure;

[0026] Figure 2 is a schematic diagram of a chip pulse width testing method provided by an embodiment of the present disclosure;

[0027] Figure 3 is a schematic diagram of another chip pulse width testing method provided by an embodiment of the present disclosure;

[0028] Figure 4 is a schematic diagram of another chip pulse width testing method provided by an embodiment of the present disclosure;

[0029] Figure 5 is a schematic diagram showing the pulse width of the chip to be tested at each analog quantity level provided by an embodiment of the present disclosure;

[0030] Figure 6 is a schematic diagram of another chip pulse width testing method provided by an embodiment of the present disclosure;

[0031] Figure 7 is a schematic diagram of a chip pulse width testing device provided by an embodiment of the present disclosure;

[0032] Figure 8 It is a schematic diagram of a chip pulse width testing device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0033] In order to be able to understand the features and technical contents of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display.

[0034] The terms "first", "second", etc. in the specification and claims of the embodiments of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged where appropriate, so that the embodiments of the embodiments of the present disclosure described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0035] Unless otherwise stated, the term "plurality" of a feature means two or more.

[0036] In the embodiment of the present disclosure, the character " / " feature indicates that the preceding and following objects are in an "or" relationship. For example, the A / B feature indicates: A or B.

[0037] The term "and / or" is a description of the association relationship between objects, and the characteristic indicates that there can be three relationships. For example, A and / or B, the characteristic indicates: A or B, or, A and B.

[0038] The term "correspondence" may refer to an association relationship or a binding relationship. The correspondence between A and B means that there is an association relationship or a binding relationship between A and B.

[0039] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present disclosure may be combined with each other.

[0040] like Figure 1 As shown, the test machine 100 provided by the embodiment of the present disclosure includes a machine body 110 and a chip pulse width test device 700 or a chip pulse width test equipment 800 .

[0041] Specifically, the machine body 110 is provided with a wafer placement area to be tested ( Figure 1 By placing the wafer to be tested in this area, the electrical connection between the test machine and the chip to be tested in the wafer to be tested can be achieved.

[0042] Specifically, the chip pulse width testing device 700 or the chip pulse width testing equipment 800 is disposed on the machine body 110 .

[0043] Optionally, the chip pulse width test device 800 includes a processor. When performing a pulse width test on the chip, the processor can construct a test pattern according to the user input definition of the set voltage, set frequency, multiple analog quantity gears and configuration information of the output pin of the chip to be tested when testing the chip to be tested. The test pattern can be written into the register of the chip to be tested, and the number of low levels output by the output pin at each analog quantity gear is collected. The pulse width of the chip to be tested at each analog quantity gear can be calculated based on the set frequency and the number of low levels output at each analog quantity gear.

[0044] In combination with the above-mentioned test machine, the embodiment of the present disclosure provides a method for testing chip pulse width, such as Figure 2 As shown, the test method includes:

[0045] S201, the processor constructs a test pattern according to the configuration information input by the user; wherein the test pattern defines a set voltage, a set frequency, a plurality of analog quantity gears and an output pin of the chip to be tested when testing the chip to be tested.

[0046] Specifically, the test pattern defines the set voltage, set frequency, multiple analog quantity gears and output pins of the chip under test when testing the chip under test. The set voltage refers to the operating voltage of the chip during the pulse width test. The set frequency refers to the frequency of the pulse signal during the test. The analog quantity gear refers to the amplitude range of the analog signal that the chip under test can receive or output and the resolution of the signal within this range. The output pin is a GPIO (General-purpose input / output) pin designated among multiple chip pins for outputting data.

[0047] Specifically, by converting the configuration information input by the user into a test pattern, the automation and standardization of the test process can be achieved.

[0048] Specifically, according to the configuration information that defines the set voltage, set frequency, multiple analog quantity gears and output pins of the chip under test, the test requirements and the test environment to be constructed can be clarified. Therefore, the processor can construct a test pattern according to the configuration information input by the user.

[0049] Optionally, the configuration information input by the user is converted into a test pattern by C language programming.

[0050] S202, the processor writes the test pattern into the register of the chip to be tested, and collects the number of low levels output by the output pin at each analog quantity gear.

[0051] Specifically, after the test pattern is written into the register of the chip under test, the chip will respond to the pulse signals of different analog quantity levels according to the test process specified in the test pattern, and will output the corresponding low-level signal or high-level signal at the output pin. Therefore, after the test pattern is written into the register of the chip under test, the processor can collect the number of low-level signals output at each analog quantity level at the output pin.

[0052] Specifically, a software counter may be set, and at each analog quantity gear, the software counter is incremented by 1 each time a low level is output, so as to collect the number of low levels output at each analog quantity gear.

[0053] S203, the processor calculates the pulse width of the chip under test at each analog quantity level according to the set frequency and the number of low-level outputs at each analog quantity level.

[0054] Optionally, according to the set frequency and the number of low-level outputs at each analog quantity level, the pulse width of the chip under test at each analog quantity level is calculated according to the following expression:

[0055]

[0056] Among them, time is the pulse width of the chip under test in the current analog gear, count is the number of low levels output by the chip under test in the current analog gear, and F is the set frequency.

[0057] Specifically, according to the cycle calculation formula, we know that: cycle = 1 / frequency, cycle = time / number of events. According to these two calculation formulas, it can be deduced that time = number of events / frequency. When calculating the pulse width, the pulse width can be regarded as time, and the number of low potentials output can be regarded as the number of events. Therefore, the pulse width of the chip under test at each analog gear can be calculated according to the above expression.

[0058] In the embodiment of the present disclosure, a test pattern can be constructed according to the configuration information input by the user including the set voltage, set frequency, multiple analog quantity gears and output pins of the chip to be tested when testing the chip to be tested. By writing the test pattern into the register of the chip to be tested and collecting the number of low levels output by the output pin at each analog quantity gear, the pulse width of the chip to be tested at each analog quantity gear can be calculated to complete the test of the chip pulse width. In this way, during the test process, automatic switching of different analog quantity gears is achieved, and batch measurement of pulse widths at different analog quantity gears is achieved. Therefore, the embodiment of the present disclosure can improve the efficiency of the pulse width test of the chip.

[0059] The present disclosure provides another method for testing chip pulse width. Figure 3 As shown, the test method includes:

[0060] S301, the processor parses the configuration information input by the user, and determines the set voltage, set frequency, multiple analog quantity gears and output pins of the chip to be tested when testing the chip to be tested.

[0061] S302, the processor verifies the rationality of the set voltage, set frequency, multiple analog quantity gears and output pins according to the specification information of the chip to be tested.

[0062] Specifically, the operating voltage, pulse frequency, analog quantity gear and output pins supported by the chip under test can be determined according to the specification parameters of the chip under test. By comparing this information, it can be determined whether the chip under test supports working under the conditions of set voltage, set frequency and multiple analog quantity gears, and whether the chip under test includes set output pins. Therefore, the processor can verify the rationality of the set voltage, set frequency, multiple analog quantity gears and output pins according to the specification information of the chip under test.

[0063] S303: If the verification fails, the processor prompts the user to re-enter the configuration information.

[0064] Specifically, if the set voltage, set frequency, multiple analog gears and output pins fail to pass the rationality verification, it means that the configuration information entered by the user is unreasonable. In this case, if a test pattern is generated based on this information to verify the chip under test, it is very easy to cause damage to the chip under test. Therefore, in this case, the test pattern will not be generated, but the user will be prompted to re-enter the configuration information.

[0065] S304, when the verification is passed, the processor converts the set voltage, set frequency, multiple analog quantity gears and output pins into a test pattern.

[0066] S305, the processor writes the test pattern into the register of the chip to be tested, and collects the number of low levels output by the output pin at each analog quantity gear.

[0067] S306, the processor calculates the pulse width of the chip under test at each analog quantity level according to the set frequency and the number of low level outputs at each analog quantity level.

[0068] In the disclosed embodiment, before the configuration information input by the user is converted into a test pattern, the rationality of the configuration information is verified according to the specification information of the chip to be tested. Only when the rationality verification is passed, the configuration information is converted into a test pattern, and the subsequent pulse width test is performed on the chip to be tested. In this way, it is ensured that the conditions for the pulse width test of the chip to be tested are all conditions under which the chip to be tested can work, reducing the risk of damaging the chip to be tested during the test.

[0069] The present disclosure provides another method for testing chip pulse width. Figure 4 As shown, the test method includes:

[0070] S401, the processor constructs a test pattern according to the configuration information input by the user; wherein the test pattern defines a set voltage, a set frequency, a plurality of analog quantity gears and an output pin of the chip to be tested when testing the chip to be tested.

[0071] S402, the processor writes the test pattern into the register of the chip to be tested, and collects the number of low levels output by the output pin at each analog quantity gear.

[0072] S403, the processor calculates the pulse width of the chip under test at each analog quantity level according to the set frequency and the number of low-level outputs at each analog quantity level.

[0073] S404, the processor displays the pulse width of the chip under test at each analog quantity level in the form of a chart.

[0074] For example, the pulse width of the chip under test at each analog quantity level is displayed in the form of a chart. Figure 5 As shown. Figure 5 It can be seen that as the analog quantity level of the chip under test increases, its pulse width also gradually increases.

[0075] In the disclosed embodiment, after calculating the pulse width of the chip under test at each analog value level, the pulse width of the chip under test at each analog value level is displayed in the form of a chart, so that the user can intuitively understand the performance of the chip under test at different analog value levels.

[0076] The present disclosure provides another method for testing chip pulse width. Figure 6 As shown, the test method includes:

[0077] S601, the processor constructs a test pattern according to the configuration information input by the user; wherein the test pattern defines a set voltage, a set frequency, a plurality of analog quantity gears and an output pin of the chip to be tested when testing the chip to be tested.

[0078] S602, the processor writes the test pattern into the register of the chip to be tested, and collects the number of low levels output by the output pin at each analog quantity gear.

[0079] S603, the processor calculates the pulse width of the chip under test at each analog quantity level according to the set frequency and the number of low-level outputs at each analog quantity level.

[0080] S604: The processor compares the pulse width of the chip under test at each analog quantity level with the expected pulse width at each analog quantity level to obtain a comparison result.

[0081] S605: The processor generates a performance evaluation report of the chip to be tested according to the comparison result.

[0082] Specifically, by comparing the pulse width of the chip under test at each analog quantity gear with the expected pulse width at each analog quantity gear, it can be determined whether the pulse width performance of the chip under test at each analog quantity gear meets the expected requirements. Therefore, the processor can determine the performance evaluation report of the chip under test based on the comparison result of the pulse width of the chip under test at each analog quantity gear with the expected pulse width at each analog quantity gear.

[0083] In the embodiment of the present disclosure, after calculating the pulse width of the chip under test at each analog quantity level, the pulse width of the chip under test at each analog quantity level is compared with the expected pulse width at each analog quantity level, and a performance evaluation report of the chip under test is generated. In this way, the performance of the chip under test at different analog quantity levels can be quantitatively evaluated, and defects of the chip under test can be discovered.

[0084] In some embodiments, the testing method further includes: obtaining the pulse width of all chips to be tested in the wafer to be tested at each analog quantity level; and determining the yield rate of the chips in the wafer to be tested based on the pulse width of all chips to be tested at each analog quantity level.

[0085] Optionally, the pulse width test of all chips to be tested in the wafer to be tested is performed in parallel based on the constructed test pattern.

[0086] Specifically, according to the pulse width of the chip under test at each analog value level, it can be determined whether the chip under test is a good product. Therefore, based on the acquired pulse width of all the chips under test in the wafer under test at each analog value level, the yield rate of the chips in the wafer under test can be determined.

[0087] Specifically, since each chip to be tested in the wafer to be tested is independent, the chip specifications in one wafer to be tested are the same, and the test machine can be electrically connected to multiple chips to be tested in the wafer to be tested at the same time. Therefore, pulse width tests can be performed on multiple chips to be tested in the wafer to be tested in parallel based on the constructed test pattern. In this way, the efficiency of pulse width testing of chips is further improved.

[0088] Combination Figure 7 As shown, the embodiment of the present disclosure provides a test device 700 for chip pulse width, including: a construction module 701, an acquisition module 702 and a calculation module 703. The construction module 701 is configured to construct a test pattern according to the configuration information input by the user; wherein the test pattern defines the set voltage, set frequency, multiple analog quantity gears and output pins of the chip to be tested when testing the chip to be tested. The acquisition module 702 is configured to write the test pattern into the register of the chip to be tested, and collect the number of low levels output by the output pin at each analog quantity gear. The calculation module 703 is configured to calculate the pulse width of the chip to be tested at each analog quantity gear according to the set frequency and the number of low levels output at each analog quantity gear.

[0089] Combination Figure 8As shown, an embodiment of the present disclosure provides a test device 800 for chip pulse width, including: a processor (processor) 801 and a memory (memory) 802. Optionally, the device may also include a communication interface (Communication Interface) 803 and a bus 804. Among them, the processor 801, the communication interface 803, and the memory 802 can communicate with each other through the bus 804. The communication interface 803 can be used for information transmission. The processor 801 can call the logic instructions in the memory 802 to execute the test method for chip pulse width of the above embodiment.

[0090] In addition, the logic instructions in the memory 802 described above may be implemented in the form of software functional units and when sold or used as independent products, may be stored in a computer-readable storage medium.

[0091] The memory 802 is a computer-readable storage medium that can be used to store software programs and computer executable programs, such as program instructions / modules corresponding to the method in the embodiment of the present disclosure. The processor 801 executes the function application and data processing by running the program instructions / modules stored in the memory 802, that is, the test method for chip pulse width in the above embodiment is implemented.

[0092] The memory 802 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and an application required for at least one function; the data storage area may store data created according to the use of the terminal device, etc. In addition, the memory 802 may include a high-speed random access memory and may also include a non-volatile memory.

[0093] An embodiment of the present disclosure provides a computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions are configured to execute the above-mentioned test method for chip pulse width.

[0094] The technical solution of the embodiment of the present disclosure can be embodied in the form of a software product, which is stored in a storage medium and includes one or more instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in the embodiment of the present disclosure. The aforementioned storage medium may be a non-transient storage medium, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a disk or an optical disk, and other media that can store program codes.

[0095] The above description and the accompanying drawings fully illustrate the embodiments of the present disclosure so that those skilled in the art can practice them. Other embodiments may include structural, logical, electrical, process and other changes. The embodiments represent only possible changes. Unless explicitly required, separate components and functions are optional, and the order of operation may vary. The parts and features of some embodiments may be included in or replace the parts and features of other embodiments. Moreover, the words used in this application are only used to describe the embodiments and are not used to limit the claims. As used in the description of the embodiments and the claims, unless the context clearly indicates, the singular forms of "a", "an" and "the" are intended to include plural forms as well. Similarly, the term "and / or" as used in this application refers to any and all possible combinations of listings containing one or more associated ones. In addition, when used in the present application, the term "comprise" and its variants "comprises" and / or comprising refer to the presence of stated features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the presence of other identical elements in the process, method or device comprising the elements. In this article, each embodiment may focus on the differences from other embodiments, and the same and similar parts between the various embodiments may refer to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method part disclosed in the embodiments, then the relevant parts can refer to the description of the method part.

[0096] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software may depend on the specific application and design constraints of the technical solution. The technicians may use different methods for each specific application to implement the described functions, but such implementations should not be considered to exceed the scope of the embodiments of the present disclosure. The technicians may clearly understand that, for the convenience and simplicity of description, the specific working processes of the systems, devices and units described above may refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here.

[0097] In the embodiments disclosed herein, the disclosed methods and products (including but not limited to devices, equipment, etc.) can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units can be only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between each other shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms. The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to implement this embodiment. In addition, each functional unit in the embodiment of the present disclosure may be integrated in a processing unit, or each unit may exist physically alone, or two or more units may be integrated in one unit.

[0098] The flowchart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to the embodiment of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of the code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. In some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, which can depend on the functions involved. In the description corresponding to the flowchart and the block diagram in the accompanying drawings, the operations or steps corresponding to different boxes can also occur in a different order from the order disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, which can depend on the functions involved. Each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified functions or actions, or may be implemented by a combination of dedicated hardware and computer instructions.

Claims

1. A method for testing chip pulse width, characterized in that: include: Construct a test pattern according to the configuration information input by the user; wherein the test pattern defines the set voltage, set frequency, multiple analog quantity gears and output pins of the chip to be tested when testing the chip to be tested; Write the test pattern into the register of the chip to be tested, and collect the number of low-level outputs of the output pin at each analog quantity level; According to the set frequency and the number of low-level outputs at each analog quantity level, the pulse width of the chip under test at each analog quantity level is calculated.

2. The testing method according to claim 1, characterized in that: Build a test pattern based on the configuration information entered by the user, including: Parse the configuration information input by the user to determine the set voltage, set frequency, multiple analog quantity gears and output pins of the chip to be tested when testing the chip to be tested; Verify the rationality of the set voltage, set frequency, multiple analog quantity gears and output pins according to the specification information of the chip to be tested; If the verification is passed, the set voltage, set frequency, multiple analog gears and output pins are converted into a test pattern.

3. The testing method according to claim 1, characterized in that: According to the set frequency and the number of low-level outputs at each analog gear, the pulse width of the chip under test at each analog gear is calculated according to the following expression: Among them, time is the pulse width of the chip under test in the current analog gear, count is the number of low levels output by the chip under test in the current analog gear, and F is the set frequency.

4. The testing method according to any one of claims 1 to 3, characterized in that: After calculating the pulse width of the chip under test at each analog quantity level, the test method further includes: The pulse width of the chip under test at each analog value level is displayed in the form of a graph.

5. The testing method according to any one of claims 1 to 3, characterized in that: After calculating the pulse width of the chip under test at each analog quantity level, the test method further includes: Compare the pulse width of the chip under test at each analog value gear with the expected pulse width at each analog value gear to obtain a comparison result; Based on the comparison results, a performance evaluation report of the chip under test is generated.

6. The testing method according to any one of claims 1 to 3, characterized in that: Also includes: Obtain the pulse width of all chips under test in the wafer under test at each analog quantity level; The yield rate of the chips in the wafer to be tested is determined based on the pulse width of all the chips to be tested at each analog quantity level.

7. The testing method according to claim 6, characterized in that: The pulse width test of all chips in the wafer is performed in parallel based on the constructed test pattern.

8. A chip pulse width testing device, characterized in that: include: A construction module is configured to construct a test pattern according to the configuration information input by the user; wherein the test pattern defines a set voltage, a set frequency, a plurality of analog quantity gears and an output pin of the chip to be tested when testing the chip to be tested; The acquisition module is configured to write the test pattern into the register of the chip to be tested and collect the number of low levels output by the output pin at each analog quantity level; The calculation module is configured to calculate the pulse width of the chip under test at each analog quantity level according to the set frequency and the number of low-level outputs at each analog quantity level.

9. A chip pulse width test device, comprising a processor and a memory storing program instructions, characterized in that: The processor is configured to execute the chip pulse width testing method according to any one of claims 1 to 7 when running the program instructions.

10. A testing machine, characterized in that: include: Machine body; The chip pulse width testing device as claimed in claim 8, or the chip pulse width testing equipment as claimed in claim 9, is arranged on the machine body.

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