Method and device for testing service life of integrated circuit

Abstract

The invention provides a life test method and device for an integrated circuit, and belongs to the technical field of test. The method comprises the following steps: intermittently applying a high acceleration voltage to a unit for life test in the integrated circuit; in the process of intermittently applying the high acceleration voltage, controlling the unit for the life test to dynamically age and recording aging process parameters; and according to the aging process parameters, obtaining a life test result of the integrated circuit. The method is used for optimizing the life test process of the integrated circuit.

Description

Technical Field

[0001] The present disclosure relates to the field of testing technology, and in particular to a method and device for testing the life of an integrated circuit. Background Art

[0002] When integrated circuits enter the deep submicron scale, reliability issues become increasingly prominent. The reliability physical mechanisms that are usually concerned include: the time-dependent breakdown characteristics of the gate dielectric TDDB (Time-Dependent Dielectric Breakdown); the bias temperature instability BTI (Bias Temperature Instability) of the front-end process transistor, hot carrier injection HCI (hot Carrier Injection); and electro-migration EM (Electro-Migration) and stress migration SM (Stress-Migration) of the back-end process. As the working time is extended, these reliability issues will lead to device performance degradation. In particular, BTI and HCI will cause the circuit operating voltage and drive current to drift, leakage to increase, as well as delay increase, frequency reduction, etc., which will ultimately affect the life of the integrated circuit.

[0003] Integrated circuit reliability assessment usually applies voltage and temperature stress, and the appropriate accelerated stress size and time are selected by referring to the BTI and HCI models. The traditional approach to large-scale integrated circuit aging assessment is to load specific binary aging vectors and run them at low acceleration under certain voltage and temperature environments. Specific integrated circuit aging equipment and customized aging test hardware are required, and a targeted test environment needs to be built, which will incur higher testing costs. In addition, since it is a low-acceleration test, it usually needs to run for 1000 hours or longer to meet the requirements of the benchmark scenario. Summary of the invention

[0004] The present disclosure provides a life test method and device for an integrated circuit.

[0005] A first aspect of the present disclosure provides a life test method for an integrated circuit, comprising:

[0006] intermittently applying a high accelerating voltage to a unit used for life testing in the integrated circuit;

[0007] During the intermittent application of the high accelerating voltage, controlling the dynamic aging of the unit for life test and recording the aging process parameters;

[0008] The result of the integrated circuit life test is obtained according to the aging process parameters.

[0009] A second aspect of the present disclosure provides a life test device for an integrated circuit, comprising:

[0010] A unit for life testing in the integrated circuit;

[0011] A test controller is used to intermittently apply a high acceleration voltage to a unit used for life testing in the integrated circuit; in the process of intermittently applying the high acceleration voltage, control the dynamic aging of the unit used for life testing and record aging process parameters; and obtain the result of the integrated circuit life test based on the aging process parameters.

[0012] The present disclosure has the following advantages:

[0013] A high acceleration voltage is intermittently applied to the unit used for life testing in the integrated circuit. During the intermittent application of the high acceleration voltage, the unit used for life testing is controlled to dynamically age and the aging process parameters are recorded. According to the aging process parameters, the result of the integrated circuit life test is obtained, so that during the reliability test of the integrated circuit life, a high acceleration voltage stress test is performed on the integrated circuit by applying a high acceleration voltage. Compared with the low acceleration voltage stress test, the life test process is accelerated and the life test duration is shortened. In addition, the requirements of the high acceleration voltage stress test on the test environment are lower than those of the low acceleration voltage stress test, and there is no need to test in a high temperature environment. This eliminates the need to customize aging test equipment and aging test hardware, and there is no need to build a dedicated aging test environment, thereby reducing the cost of life testing. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 A schematic diagram of a life test method for an integrated circuit provided in an embodiment of the present disclosure;

[0015] Figure 2 A schematic diagram of two configuration methods for the effective running time of a test case provided in an embodiment of the present disclosure;

[0016] Figure 3a Schematic diagram of two application methods of high acceleration voltage provided in the embodiments of the present disclosure;

[0017] Figure 3b An example of a reliability modeling and life prediction process based on different parameter degradations provided in an embodiment of the present disclosure;

[0018] Figure 4 A schematic diagram of the structure of a life test device for an integrated circuit provided in an embodiment of the present disclosure;

[0019] Figure 5 A schematic diagram of a structure of a test design based on a standard unit in an IP core provided in an embodiment of the present disclosure;

[0020] Figure 6A schematic diagram of the structure of a submodule provided in an embodiment of the present disclosure;

[0021] Figure 7 A schematic diagram of a structure of a test design based on an integrated circuit built-in diagnostic circuit provided in an embodiment of the present disclosure;

[0022] Figure 8 A schematic diagram of the structure of a diagnostic link provided in an embodiment of the present disclosure;

[0023] Fig. 9 A schematic diagram showing the comparison of the results of the life test method provided in the embodiment of the present disclosure and the traditional evaluation method in a larger Vmin degradation range (1% to 20%);

[0024] Fig.10 It is a schematic diagram comparing the results of the life test method provided in the embodiment of the present disclosure and the traditional evaluation method in the low degradation range of 1% to 3%. DETAILED DESCRIPTION

[0025] The specific implementation of the present disclosure is described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation described herein is only used to illustrate and explain the present disclosure, and is not used to limit the present disclosure.

[0026] As used in this disclosure, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0027] The terms used in the present disclosure are only used to describe specific embodiments and are not intended to limit the present disclosure.As used in the present disclosure, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0028] When the terms “comprising” and / or “made of…” are used in the present disclosure, it specifies the existence of the stated features, integers, steps, operations, elements and / or components, but does not exclude the existence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0029] Unless otherwise defined, all terms (including technical and scientific terms) used in this disclosure have the same meaning as those commonly understood by those of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning unless explicitly defined in this disclosure.

[0030] The disclosed embodiments provide a life test method for an integrated circuit to perform reliability testing on the life of the integrated circuit, and can be applied to reliability testing, accelerated life evaluation, reliability prediction and other fields of integrated circuit reliability engineering.

[0031] Figure 1 The figure is a schematic flow chart of a life test method for an integrated circuit provided by an embodiment of the present disclosure, and the method mainly comprises the following steps:

[0032] Step 101: intermittently apply a high acceleration voltage to a unit in the integrated circuit for life testing.

[0033] In some embodiments, the intermittent application of a high acceleration voltage to the unit used for life testing in the integrated circuit includes: obtaining the total effective operation time corresponding to the high acceleration voltage stress test of the integrated circuit; decomposing the total effective operation time to obtain each effective operation segment time; determining the effective operation time period corresponding to each effective operation segment time period, and the intermittent period between adjacent effective operation time periods; applying a high acceleration voltage to the unit used for life testing in each effective operation time period, and stopping applying the high acceleration voltage to the unit used for life testing in the intermittent period.

[0034] By setting an interval between two time periods of applying high acceleration voltage to the integrated circuit, damage or breakdown caused by short-term heat accumulation of the integrated circuit due to long-term high acceleration voltage can be avoided, so that a complete high acceleration voltage stress test process can be completed.

[0035] The duration of the intermission period only needs to be sufficient to meet the heat dissipation requirements of the integrated circuit, and there is no limit on the specific duration.

[0036] In an exemplary embodiment, the total effective operation time corresponding to the high-acceleration stress test of the integrated circuit can be a pre-set empirical value, or a pre-calculated theoretical reference value. The total effective operation time can be determined according to the overall life assessment requirements of the integrated circuit. Specifically, the total effective operation time is usually set to several tens of hours, such as 10 hours or 20 hours.

[0037] Step 102 : During the intermittent application of the high acceleration voltage, the unit for life test is controlled to dynamically age and the ageing process parameters are recorded.

[0038] In some embodiments, during the intermittent application of the high accelerating voltage, controlling the dynamic aging of the unit for life testing and recording the aging process parameters include:

[0039] During the application of the high acceleration voltage, running the test case to control the dynamic aging of the unit for life test;

[0040] During the interval when the application of the high accelerating voltage is stopped, the aging process parameters of the unit for life test are monitored and recorded.

[0041] The test case includes the parameter configuration of the unit for user life test and the configuration of control timing during the test. For example, the test case can be a traditional wig / stil test case.

[0042] In some embodiments, the duration of each of the effective running segments is the same or increases.

[0043] The effective running segment duration of applying high acceleration voltage is the effective running duration of the test case.

[0044] The total effective running time corresponding to the high acceleration voltage stress test is the total effective running time of the test case.

[0045] It should be noted that high accelerating voltage stress is applied intermittently during the aging process, and the total effective running time of the test case is determined according to the overall life assessment requirements, and the aging time is decomposed at each intermittent reading point. Each effective running time (expressed as t_Pi) is decomposed according to the aging law and can be the same or increasing.

[0046] like Figure 2 The diagram shows two configuration methods for the effective running time of test cases. The total effective running time accumulated by the two methods is the same. Figure 2 VDD represents the normal operating voltage of the integrated circuit, and VDD_H represents the high acceleration voltage. Figure 2 In method a, the length of each effective running segment is the same, and the width of a shaded portion represents the length of an effective running segment. In this method, the width of each shaded portion is the same, and the gap between two shaded portions is the intermission period. Figure 2 In mode b, the effective operation time of each segment is different and shows an increasing trend. The width of a shaded part represents the effective operation time of a segment. The width of each shaded part in this mode is different, and it shows a gradual increasing trend from P1, P2, P3...Pn. Referring to the saturation trend of the bias temperature instability (BTI) effect, the degradation will gradually become flat over time, so the effective operation time of each segment can be increased by applying a high acceleration voltage.

[0047] In some embodiments, the effective operation segment duration is not less than the set duration. For example, no matter which effective operation segment duration is configured, the effective operation segment duration of any segment is not less than 30 seconds (s) to ensure that the effective aging is achieved by running the test case within the effective operation segment duration.

[0048] In some embodiments, the voltage value of the high acceleration voltage is not lower than the voltage value applied during the conventional high temperature operation life (HTOL) test, and is not higher than the breakdown voltage value of the transistor in the unit used for the life test. Typically, the voltage value applied during the conventional HTOL test is not lower than 1.3 times the normal operating voltage value (i.e., VDD value). For example, the voltage value of the high acceleration voltage is set to a value in the range of 1.5 times VDD to 2 times VDD.

[0049] Among them, the value of the high acceleration voltage should take into account the influence of the integrated circuit's own power consumption and heat dissipation capacity.

[0050] In some embodiments, the voltage value of the high acceleration voltage applied in each of the effective operation time periods is the same, or increases in steps.

[0051] like Figure 3a The diagram shows two ways of applying high acceleration voltage, namely constant and stepping. In the constant high acceleration voltage application mode, the voltage value of the high acceleration voltage applied in each effective operation time period is the same, which is convenient for controlling and converting the voltage acceleration time; in the stepping high acceleration voltage application mode, the voltage value of the high acceleration voltage applied in each effective operation time period increases in steps, first applying stress close to the normal value to the integrated circuit, and then increasing the stress by one level after reaching the specified time, setting no less than three levels of stress. Since the stepping pressure method provides multiple sets of voltage stress, unlike the constant pressure method, which can only obtain one set of voltage test data during the test process, the stepping pressure method can obtain more voltage group test data as a reference during the test process.

[0052] Step 103: Obtain the result of the integrated circuit life test according to the aging process parameters.

[0053] In some embodiments, the aging process parameters include respective grouped data, the grouped data including time, delay increment, and voltage applied in voltage stress;

[0054] The method also includes: obtaining an empirical model for representing the relationship between time delay and life; and fitting a life model for reflecting the relationship between time delay and life of the integrated circuit based on the empirical model and the grouping data.

[0055] In an exemplary embodiment, the empirical model for representing the relationship between time delay and life span is expressed as shown in formula (1):

[0056] DegPDmin = Bt n V m (1)

[0057] Among them, DegPDmin represents the delay increment, t represents time, V represents the high acceleration voltage, namely VDD_H, B is the experimental constant, m is the voltage coefficient, and n is the time constant.

[0058] By fitting the empirical model with the aging process parameters, the aging-related parameters of the integrated circuit and the life model reflecting the relationship between the delay and life of the integrated circuit are obtained. If the integrated circuit with the same process and the same device family needs to be tested for life in the future, the life model can be directly used for extrapolation to predict the life performance of the integrated circuit.

[0059] In some embodiments, the aging process parameters include respective grouped data, the grouped data including time, voltage increment, and voltage applied during voltage stress;

[0060] The method also includes: obtaining a physical model for representing the relationship between voltage and life; and fitting a life model for reflecting the relationship between the voltage increment of the integrated power and the life according to the physical model and the grouped data.

[0061] In an exemplary embodiment, the physical model used to represent the relationship between voltage and life is expressed as shown in formula (2):

[0062] VxD min = C exp(βV) exp(γt α ) (2)

[0063] Among them, DegV min represents the voltage increment, t represents the time, V represents the high acceleration voltage, namely VDD_H, C and γ are experimental constants, β is the voltage coefficient, and α is the time constant.

[0064] By fitting the physical model with the aging process parameters, the aging-related parameters of the integrated circuit and the lifespan model reflecting the relationship between the voltage increment of the integrated power are obtained. If the integrated circuit with the same process and the same device family needs to be tested for life in the future, the lifespan performance of the integrated circuit can be predicted by directly using the lifespan model for extrapolation.

[0065] In some embodiments, the unit for life test includes an intellectual property IP core, or includes a standard unit in the intellectual property IP core.

[0066] In an exemplary embodiment, the delay increment is obtained by monitoring the aging process of a standard cell in an IP core of an integrated circuit; and the voltage increment is obtained by monitoring the aging process of the IP core of an integrated circuit.

[0067] In the disclosed embodiment, a high acceleration voltage is intermittently applied to the unit used for life testing in the integrated circuit. During the intermittent application of the high acceleration voltage, the unit used for life testing is controlled to dynamically age and the aging process parameters are recorded. According to the aging process parameters, the result of the integrated circuit life test is obtained, so that during the reliability test of the integrated circuit life, a high acceleration voltage stress test is performed on the integrated circuit by applying a high acceleration voltage. Compared with the low acceleration voltage stress test, the life test process is accelerated and the life test duration is shortened. In addition, the requirements of the high acceleration voltage stress test on the test environment are lower than those of the low acceleration voltage stress test, and there is no need to test in a high temperature environment. This eliminates the need to customize aging test equipment and aging test hardware, and there is no need to build a dedicated aging test environment, thereby reducing the cost of life testing.

[0068] In an exemplary embodiment, Figure 3b The following is an example of a reliability modeling and life prediction process based on different parameter degradations, mainly including:

[0069] (1) Structure of accelerated life test and selection of test cases for aging;

[0070] (2) Accelerate test implementation and monitoring data collection;

[0071] For the empirical model corresponding to the time delay, perform the following (3) to (6):

[0072] (3) Fitting the empirical model based on the time-delayed aging data;

[0073] (4) Extrapolation of TTF based on specified failure criteria;

[0074] (5) AF estimation based on Fab process reference;

[0075] (6) predicting lifespan based on the obtained model;

[0076] For the physical model corresponding to voltage, perform the following (7) to (9):

[0077] (7) Establish a voltage-based physical model;

[0078] (8) Fitting the physical model based on voltage aging data;

[0079] (9) Perform lifespan prediction based on the obtained model.

[0080] The step division of the above various methods is only for clear description. When implemented, they can be combined into one step or some steps can be split and decomposed into multiple steps. As long as they include the same logical relationship, they are all within the protection scope of this disclosure. Adding insignificant modifications to the algorithm or process or introducing insignificant designs without changing the core design of the algorithm and process are all within the protection scope of this disclosure.

[0081] The present disclosure also provides a life test device for an integrated circuit. Figure 4 The schematic diagram of the structure of the device is shown, which mainly includes:

[0082] A unit 401 for life testing in the integrated circuit;

[0083] The test controller 402 is used to intermittently apply a high acceleration voltage to the unit 401 for life testing in the integrated circuit; in the process of intermittently applying the high acceleration voltage, control the dynamic aging of the unit 401 for life testing and record the aging process parameters; and obtain the result of the integrated circuit life test based on the aging process parameters.

[0084] In some embodiments, the unit for life testing is a submodule in an intellectual property IP core of the integrated circuit.

[0085] Figure 5 The structure diagram of the test design based on the standard unit in the IP core is shown. The integrated circuit is composed of multiple IP cores, and any IP-i, including core, high-speed serial computer expansion bus standard (PCIE), deserializer (serdes), double rate synchronous dynamic random access memory (DDR), etc., to realize integrated circuit functions such as calculation, data transmission, signal transmission, and buffer storage. Each core IP core is composed of multiple sub-modules Si, and is integrated with the top-level circuit to realize the specific functions of the IP core. The sub-module supports the test point TP-i to lead out, so as to realize the parameter drift monitoring of some module circuits or full integrated circuit circuits in the integrated circuit, for example, the delay increment during the aging test is recorded through the TP-i.

[0086] Figure 6 The figure shows a schematic diagram of the structure of the submodule, wherein the submodule includes a control circuit 501, a standard cell 502 and a storage circuit 503; the standard cell 502 includes a transistor array for aging test; the control circuit 501 is used to control the standard cell to perform dynamic aging according to the control logic configured by the test controller during the process of applying a high acceleration voltage to the standard cell 502, and save the aging process parameters to the storage circuit 503.

[0087] The storage circuit 502 can be divided into a front-stage storage circuit and a rear-stage storage circuit. The front-stage storage circuit is used to store the intermediate parameters of the dynamic aging process, and the rear-stage storage circuit is used to store the final parameters of the dynamic aging process.

[0088] In some embodiments, the submodule further includes a combination circuit 504; the combination circuit 504 is used to combine the transistor arrays in the standard unit 502 according to a specified path under the control of the control circuit, and return the aging process parameters of the combined transistor array group to the control circuit for storage.

[0089] Among them, according to the digital circuit part in the IP core, the standard cell 502 is composed of an AND gate and a multi-stage inverter. The specific number of stages is considered in combination with the frequency divider. The AND gate is controlled by configuring the enable (EN) signal, and the inverter flip is further controlled to achieve the purpose of dynamic circuit aging. Exemplarily, the standard cell 502 includes but is not limited to a logic gate, a driving unit, a timing unit, an operation unit, a synthesis unit, a buffer unit, etc. In addition, according to the analog circuit part in the IP core, the standard cell may include transistors with different threshold voltages such as a standard voltage threshold (SVT), a low voltage threshold (LVT), a high voltage threshold (HVT), and an ultra-low voltage threshold (ULVT) to improve the coverage of the aging circuit.

[0090] The standard cell can support module circuit flipping under the control of the control circuit 501 according to the configuration to perform dynamic aging of the transistor array.

[0091] By configuring the standard cells in the integrated circuit, the circuit flipping during the aging process is realized to perform dynamic aging and monitor the delay output after aging. The delay (or frequency) reference for aging monitoring is provided based on the standard cells in the integrated circuit. The monitored delay (or frequency) is an important parameter for achieving reliability and life modeling.

[0092] In some embodiments, the unit for life testing includes an intellectual property IP core in the integrated circuit and a diagnosis circuit corresponding to the IP core.

[0093] Figure 7 The figure shows a schematic diagram of the structure of the test design based on the built-in diagnostic circuit of the integrated circuit. The integrated circuit includes multiple IP cores, and the integrated circuit also includes a variety of diagnostic circuit designs, including but not limited to boundary scan (BSCAN), scan (SCAN), loopback (LPBK), etc., such as input / output (IO) boundary scan, link scan, loopback, etc. Each IP core or multiple IP cores support chain connection test through links, and chain_IN and chain_OUT correspond to the test link input and output respectively.

[0094] The sub-modules in the IP core support the test point TP-i lead-out to achieve voltage monitoring. The sub-modules covered by the corresponding test points can be selected according to the needs of life assessment, thereby supporting parameter drift monitoring of some sub-module circuits or full integrated circuit circuits.

[0095] Figure 8 The structure diagram of the diagnostic link is shown. A plurality of the diagnostic circuits are connected in series to form a diagnostic link, and the diagnostic link is used to connect the corresponding plurality of IP cores in series; the test controller is used to input control logic from the input end of the diagnostic link to perform a series life test on the plurality of IP cores connected in series by the diagnostic link through the control logic; the diagnostic circuit is used to control the dynamic aging of the IP core according to the control logic and record the aging process parameters in the process of applying a high acceleration voltage to the IP core.

[0096] The built-in diagnostic circuits of the integrated circuit can support high-coverage testing of the logic part, including but not limited to the register design of the built-in combinational logic.

[0097] Exemplarily, the diagnostic circuit includes a trigger and a combinational logic, provides a test vector at the input (Diag input), and shifts the internal data to the output (Diag output) through the trigger under the control of an enable (EN) signal for diagnosis. The diagnostic circuit can match a variety of low-power test vectors such as leakage test (IDDQ) and low-speed scan test (stuck-at) to achieve dynamic aging acceleration of integrated circuits. Compared with traditional aging test vectors, low-power test vectors have lower power consumption and can support the application of high voltage stress.

[0098] Run low-power test vectors on the diagnostic circuit built into the integrated circuit to switch the circuit state during the aging process for dynamic aging and monitor the voltage output after aging. Based on the diagnostic circuit inside the integrated circuit, a voltage reference for aging monitoring is provided. The monitored voltage change is an important parameter for reliability and life modeling.

[0099] In summary, for standard units or built-in diagnostic circuits in integrated circuits, the existing wig / stil test cases are applied, and FT test equipment and hardware are flexibly reused, which greatly saves the hardware cost of reliability testing and shortens the test time. It can effectively improve the efficiency of integrated circuit reliability evaluation or prediction, and provide an effective way for reliability evaluation and life prediction of large-scale integrated circuits.

[0100] The functions or modules included in the device provided in the embodiments of the present disclosure can be used to execute the method described in the method embodiments. The specific implementation and technical effects thereof can be referred to the description of the method embodiments above, and will not be described again here for the sake of brevity.

[0101] It should be noted that the modules involved in this embodiment include logic and analog modules. In practical applications, a logic unit can be a physical unit, a part of a physical unit, or a combination of multiple physical units. In addition, in order to highlight the innovative part of the present disclosure, the present embodiment does not introduce units that are not closely related to solving the technical problems proposed by the present disclosure, but this does not mean that there are no other units in the present embodiment.

[0102] In one exemplary embodiment, the process of performing life testing on an integrated circuit is as follows:

[0103] (1) Selecting standard cells of the integrated circuit process sensor module, realizing circuit flipping during the aging process through cell configuration, and monitoring the delay output after aging; in addition, based on the integrated circuit diagnostic circuit, realizing circuit state switching during the aging process by running the IDDQ test vector, and monitoring the voltage output after aging;

[0104] (2) Apply intermittent, high-acceleration voltage stress (1.5-2VDD) during the overall aging process, monitor parameter outputs when loading use cases into registers during low-voltage intermittent periods, and apply constant mode to control high voltage stress;

[0105] (3) According to the parameter degradation monitored by the standard cell or diagnostic circuit, the reliability models of life and delay, and life and voltage are established respectively, and prediction is performed based on the models;

[0106] (4) Compare the prediction results of the two test circuit corresponding methods with the traditional chip reliability HTOL prediction results.

[0107] The comparison shows that the prediction results based on standard unit and diagnostic circuit test design have a good match with the life prediction of HTOL, such as Fig. 9 As shown in Figure 2, both models have good agreement with the HTOL data in a larger Vmin degradation range (1% to 20%). Especially in the low degradation range of 1% to 3% Vmin, the two models have a high degree of match with the traditional aging prediction results, such as Fig.10 As shown, it is demonstrated that the life test device and method provided in the embodiments of the present disclosure are effective in conducting reliability test results and actual reliability evaluation.

[0108] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0109] Those skilled in the art will understand that although some embodiments described herein include certain features included in other embodiments but not other features, the combination of features from different embodiments is meant to be within the scope of the present embodiment and to form different embodiments.

[0110] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present disclosure, but the present disclosure is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and substance of the present disclosure, and these modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A life test method for an integrated circuit, characterized in that: include: intermittently applying a high accelerating voltage to a unit used for life testing in the integrated circuit; During the intermittent application of the high accelerating voltage, controlling the dynamic aging of the unit for life test and recording the aging process parameters; The result of the integrated circuit life test is obtained according to the aging process parameters.

2. The method according to claim 1, characterized in that The intermittently applying a high acceleration voltage to a unit in the integrated circuit for life testing comprises: Obtaining a total effective running time corresponding to a high acceleration voltage stress test of the integrated circuit; Decomposing the total effective operation duration to obtain each effective operation segment duration; Determine the effective operation time period corresponding to each effective operation segment duration, and the intermission period between adjacent effective operation time periods; A high acceleration voltage is applied to the unit for life test in each of the effective operation time periods, and the application of the high acceleration voltage to the unit for life test is stopped in the intermittent period.

3. The method according to claim 2, characterized in that The duration of each effective operation segment is the same or increases.

4. The method according to claim 2, characterized in that: The duration of each effective operation segment is not less than the set duration.

5. The method according to claim 2, characterized in that: The voltage value of the high acceleration voltage is not lower than the voltage value applied during the conventional high temperature working life test, and is not higher than the breakdown voltage value of the transistor in the unit used for the life test.

6. The method according to claim 3, characterized in that The voltage value of the high acceleration voltage applied in each of the effective operation time periods is the same, or increases in steps.

7. The method according to claim 1, characterized in that In the process of intermittently applying the high accelerating voltage, controlling the dynamic aging of the unit for life test and recording the aging process parameters include: During the application of the high acceleration voltage, running the test case to control the dynamic aging of the unit for life test; During the interval when the application of the high accelerating voltage is stopped, the aging process parameters of the unit for life test are monitored and recorded.

8. The method according to claim 1, characterized in that: The aging process parameters include grouped data, including time, delay increment, and voltage applied in voltage stress; The method further comprises: Obtaining an empirical model for representing the relationship between time delay and life span; A life model for reflecting the relationship between the delay and life of the integrated circuit is obtained by fitting according to the empirical model and the grouping data.

9. The method according to claim 1, characterized in that: The aging process parameters include grouped data including time, voltage increment, and voltage applied in voltage stress; The method further comprises: Obtaining a physical model for representing the relationship between voltage and life; According to the physical model and the grouping data, a life model for reflecting the relationship between the voltage increment of the integrated electric quantity and the life is obtained by fitting.

10. The method according to claim 1, characterized in that The unit for life test includes an intellectual property IP core, or includes a standard unit in the intellectual property IP core.

11. A life test device for an integrated circuit, characterized in that: include: A unit for life testing in the integrated circuit; A test controller is used to intermittently apply a high acceleration voltage to a unit used for life testing in the integrated circuit; in the process of intermittently applying the high acceleration voltage, control the dynamic aging of the unit used for life testing and record aging process parameters; and obtain the result of the integrated circuit life test based on the aging process parameters.

12. The device according to claim 11, characterized in that The unit for life test is a submodule in the intellectual property IP core of the integrated circuit; The submodule includes a control circuit, a standard unit and a storage circuit; The standard cell includes a transistor array for aging testing; The control circuit is used to control the standard cell to perform dynamic aging according to the control logic configured by the test controller during the process of applying a high acceleration voltage to the standard cell, and save the aging process parameters to the storage circuit.

13. The device according to claim 12, characterized in that The submodule also includes a combination circuit; The combination circuit is used to combine the transistor arrays in the standard unit according to a specified path under the control of the control circuit, and return the aging process parameters of the combined transistor array group to the control circuit for storage.

14. The device according to claim 11, characterized in that The unit for life test includes an intellectual property IP core in the integrated circuit and a diagnostic circuit corresponding to the IP core; A plurality of the diagnostic circuits are connected in series to form a diagnostic link, and the diagnostic link is used to connect a corresponding plurality of the IP cores in series; The test controller is used to input control logic from the input end of the diagnostic link to perform a serial connection life test on the multiple IP cores serially connected to the diagnostic link through the control logic; The diagnostic circuit is used to control the dynamic aging of the IP core and record the aging process parameters according to the control logic during the process of applying a high acceleration voltage to the IP core.

Images