Method and system for testing abnormal power-off of chip, device and medium

Abstract

The application discloses a kind of to chip abnormal power-down test method and its system, equipment, medium;It is related to chip test technical field.Abnormal power-down test system includes: test fixture, stabilized power supply, timing on-off relay, stepping relay and host computer;Method includes: when the shutdown charging function of test fixture is closed, in the process that test control module responds to read-write test instruction to carry out read-write test to the chip to be measured, host computer responds to random power-down control instruction, controls the working state of timing on-off relay and stepping relay, continuously carries out multiple power-down control, and makes multiple power-down faults;Power-down control instruction is as follows one: timing power-down single mode instruction, step-down single mode instruction, combined power-down mode instruction;Test control module automatically returns read-write test result after each power-down fault occurs to host computer to realize abnormal power-down test to the chip to be measured.Can improve the reliability and accuracy of abnormal power-down test.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip testing, and in particular to a chip abnormal power-off test method, system, device and medium. BACKGROUND

[0002] In the test of embedded chips, power-off test is a very important test item. Generally, power-off test is divided into normal power-off test and abnormal power-off test. In the read-write process of embedded chips (such as memory chips), normal power-off test or abnormal power-off test can be carried out to test the stability and reliability of embedded chips. Among them, the normal power-off test is that the host sends a command to inform the embedded chip that it will be powered off, and the embedded chip is notified to save the corresponding data and stop subsequent data operation, and then the power-off test is carried out; the abnormal power-off test is to suddenly disconnect the power supply of the device when the embedded chip is still working, and then the power-off test is carried out.

[0003] In the related art, manual switching of the power supply is required during the abnormal power-off test to simulate the power-off fault scene, and the manual work efficiency is low, which limits the number and type of manual simulation of power-off faults. Therefore, the abnormal power-off test realized by manually switching on and off the power supply to simulate the power-off fault cannot cover some low-probability abnormal power-off events in actual application scenarios, and the reliability and accuracy of the abnormal power-off test result are not high. SUMMARY

[0004] The present application aims to at least solve one of the technical problems existing in the prior art. To this end, the present application provides a chip abnormal power-off test method, system, device and medium, which can randomly create multiple abnormal power-off faults and realize automatic abnormal power-off test, thereby improving the reliability and accuracy of the abnormal power-off test.

[0005] In a first aspect, an embodiment of the present application provides a chip abnormal power-off test method applied to an abnormal power-off test system, the system comprising a test fixture, a stabilized power supply, a timing on-off relay, a stepping relay and an upper computer; wherein the test fixture comprises a test control module, a fixture power supply module electrically connected to the test control module, a USB interface, a serial port, a chip to be tested; the output end of the stabilized power supply is connected to the positive electrode of the fixture power supply module through the timing on-off relay; the upper computer is connected to the USB interface through the stepping relay and connected to the test control module through the serial port;

[0006] The method comprises:

[0007] In the case that the shutdown charging function of the test fixture is turned off, the test control module responds to the read-write test instruction sent by the upper computer through the serial port to perform read-write test on the chip to be tested;

[0008] In the read-write test process, the host computer controls the working state of the timing on-off relay and the stepping relay in response to a random power-off control instruction, and continuously performs multiple power-off controls to cause multiple power-off failures; wherein the power-off control instruction is one of the following: a timing power-off single mode instruction, a stepping power-off single mode instruction, and a combined power-off mode instruction.

[0009] The test control module automatically records the read-write test result after each power-off failure, and automatically returns the read-write test result to the host computer through the serial port, so as to realize the abnormal power-off test of the chip to be tested.

[0010] In a second aspect, the embodiments of the present application provide an abnormal power-off test system, comprising:

[0011] A test fixture, a stabilized power supply, a timing on-off relay, a stepping relay, and a host computer; wherein the test fixture comprises a test control module, a fixture power supply module electrically connected to the test control module, a USB interface, a serial port, and a chip to be tested; the output end of the stabilized power supply is connected to the positive electrode of the fixture power supply module through the timing on-off relay; the host computer is connected to the USB interface through the stepping relay and connected to the test control module through the serial port; and the abnormal power-off test system is used to execute the abnormal power-off test method of the chip as described in any one of the embodiments of the first aspect.

[0012] In a third aspect, the embodiments of the present application provide an electronic device, comprising at least one processor and a memory connected to the at least one processor in communication; the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the abnormal power-off test method of the chip as described in any one of the embodiments of the first aspect.

[0013] In a fourth aspect, the embodiments of the present application provide a computer readable storage medium, which stores computer executable instructions for causing a computer to execute the abnormal power-off test method of the chip as described in any one of the embodiments of the first aspect.

[0014] The embodiment of the present application comprises: an abnormal power-off test system comprising a test fixture, a stabilized power supply, a timing on-off relay, a stepping relay and an upper computer; wherein the test fixture comprises a test control module, a fixture power module electrically connected with the test control module, a USB interface, a serial port and a chip to be tested; the output end of the stabilized power supply is connected with the positive pole of the fixture power module through the timing on-off relay; the upper computer is connected with the USB interface through the stepping relay and connected with the test control module through the serial port; in the process of abnormal power-off test of the chip to be tested through the abnormal power-off test system, firstly, the test control module performs read-write test on the chip to be tested in response to the read-write test instruction sent by the upper computer through the serial port in the case that the shutdown charging function of the test fixture is closed; then, in the read-write test process, the upper computer controls the working state of the timing on-off relay and the stepping relay in response to the random power-off control instruction, continuously performs multiple power-off control and makes multiple power-off faults; wherein the power-off control instruction is one of the following: a timing power-off single mode instruction, a stepping power-off single mode instruction and a combined power-off mode instruction; thereby random multiple abnormal power-off faults can be made in the read-write test process to simulate actual multiple abnormal power-off faults, laying a foundation for realizing automatic abnormal power-off test; finally, the test control module automatically records the read-write test result after each power-off fault occurs and automatically returns the read-write test result to the upper computer through the serial port to realize abnormal power-off test of the chip to be tested; automatic abnormal power-off test is realized, and the reliability and accuracy of abnormal power-off test are improved. That is to say, the embodiment of the present application can randomly make multiple abnormal power-off faults, realize automatic abnormal power-off test and improve the reliability and accuracy of abnormal power-off test. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 is a schematic diagram of the overall architecture of an abnormal power-off test system provided by an embodiment of the present application;

[0016] Figure 2 is a schematic diagram of the step flow of an abnormal power-off test method for a chip provided by an embodiment of the present application;

[0017] Figure 3 is a specific process diagram of power-off control in the case that the power-off control instruction is a combined power-off mode instruction provided by an embodiment of the present application;

[0018] Figure 4 is a schematic diagram of the hardware structure of an electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0019] In order to make the purpose, technical scheme and advantages of the present application more clear, the present application is further described in detail below with reference to the drawings and embodiments.

[0020] It should be noted that although the logical order is shown in the flowchart in the description of the present application, in some cases, the steps shown or described can be performed in an order different from that in the flowchart. In the description of the present application, several meanings are one or more, and multiple meanings are two or more. The description of "first", "second" is only for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features or the sequence of indicated technical features.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs. The terms used herein are only for the purpose of describing the embodiments of the present application and are not intended to limit the present application.

[0022] The terms involved in the present application are explained:

[0023] The TX port and RX port in the serial port server refer to the transmit (TX) and receive (RX) pins in serial communication. The TX port is used for transmitting data, while the RX port is used for receiving data. In serial communication, these two pins are the key part of data transmission.

[0024] The Universal Serial Bus (USB) interface is a serial bus standard and a technical specification of an input and output interface, which is widely used in personal computers and mobile devices and other information communication products.

[0025] The present application discloses a chip abnormal power-off test method, an abnormal power-off test system, an electronic device and a computer readable storage medium, and relates to the technical field of chip testing. The abnormal power-off test system comprises a test fixture, a stabilized power supply, a timing on-off relay, a stepping relay and an upper computer. The method comprises the following steps: when the shutdown charging function of the test fixture is turned off, the upper computer controls the working states of the timing on-off relay and the stepping relay in response to random power-off control instructions during the reading and writing test of the to-be-tested chip by the test control module in response to reading and writing test instructions, and multiple power-off controls are continuously performed to cause multiple power-off faults; the power-off control instruction is one of the following: a timing power-off single mode instruction, a stepping power-off single mode instruction and a combined power-off mode instruction; and the test control module automatically returns the reading and writing test result after each power-off fault to the upper computer, so as to realize the abnormal power-off test of the to-be-tested chip. The reliability and accuracy of the abnormal power-off test can be improved.

[0026] The embodiments of the present application will be further described below with reference to the accompanying drawings.

[0027] AsFigure 1 As shown, the abnormal power-off test system comprises a test fixture, a stabilized power supply, a timing on-off relay, a stepping relay and a host computer. The test fixture comprises a test control module, a fixture power module electrically connected to the test control module, a USB interface, a serial port, and a chip to be tested. The output end of the stabilized power supply is connected to the positive pole of the fixture power module through the timing on-off relay. The host computer is connected to the USB interface through the stepping relay and connected to the test control module through the serial port. It can be understood that the negative pole of the fixture power module is grounded.

[0028] The stabilized power supply is configured to provide power for the test fixture through the positive pole of the fixture power module. Specifically, in an embodiment, the stabilized power supply can be a 4.2V stabilized power supply.

[0029] The timing on-off relay is configured to control the circuit between the output end of the stabilized power supply and the positive pole of the fixture power module to be disconnected or conductive.

[0030] The stepping relay is configured to control the circuit between the host computer and the USB interface of the test fixture to be disconnected or conductive. Specifically, the stepping relay is a 5V relay. The stepping relay and the USB interface of the test fixture are connected through a USB charging data line. It should be noted that the host computer is connected to the USB interface of the test fixture through the stepping relay, so the host computer provides power for the stepping relay.

[0031] It can be understood that in the abnormal power-off test system, when the stepping relay is powered on and the timing on-off relay electrically connected to the stabilized power supply is powered on, the test fixture will be powered on and enter the start-up running phase of the test fixture.

[0032] The test fixture is configured to load the chip to be tested. The test control module of the test fixture is configured to, in the case that the test fixture shutdown charging function is closed, perform read-write test on the chip to be tested in response to the read-write test instruction sent by the host computer through the serial port, automatically record the read-write test result after each power-off failure occurs, and automatically return the read-write test result to the host computer through the serial port, so as to realize abnormal power-off test of the chip to be tested, and realize automatic abnormal power-off test. Specifically, the test fixture can be all Android system products of mobile phones, tablets and the like with built-in batteries, and has been debugged in advance. In the mobile phone and tablet abnormal power-off test system, test fixtures with different CPU platforms can be used, and currently popular CPU platforms such as MTK, Qualcomm and Spreadtrum platform can be used; so that the abnormal power-off test system of the present application has high compatibility. Therefore, the type of CPU platform used by the test fixture is not specifically limited. The test fixture can be all Android system products of mobile phones, tablets and the like with built-in batteries.

[0033] Specifically, the positive and negative electrodes are led out through the interface of the battery of the test fixture.

[0034] Specifically, the serial port comprises a TX port and a RX port. The test fixture receives the read-write test instruction sent by the host computer through the RX port to perform read-write test on the chip under test in the power-on state; and returns the read-write test result to the host computer through the TX port after the read-write test is completed.

[0035] Specifically, the chip under test is an EMMC storage chip or other chip that needs to be tested for abnormal power-off.

[0036] Specifically, the host computer is configured to send a read-write test instruction to the test control module of the test fixture through the serial port, so that the test fixture performs read-write test on the chip under test; and in response to a random power-off control instruction, the working state of the timing on-off relay and the stepping relay is controlled to continuously perform multiple power-off controls to generate multiple power-off faults; wherein the power-off control instruction is one of a timing power-off single mode instruction, a stepping power-off single mode instruction and a combined power-off mode instruction; thereby randomly generating multiple abnormal power-off faults in the read-write test process to simulate actual multiple abnormal power-off faults and lay a foundation for realizing automatic abnormal power-off test; and the host computer is further configured to automatically acquire the read-write test result recorded by the test control module after each power-off fault occurs through the serial port to realize abnormal power-off test on the chip under test; thereby realizing automatic abnormal power-off test and improving the reliability and accuracy of abnormal power-off test.

[0037] It should be noted that the embodiments of the present application can perform abnormal power-off test on products with batteries. In the chip test process, the chip under test such as an EMMC storage chip needs to be tested for abnormal power-off on the test fixture. Based on this, the abnormal power-off test system provided by the embodiments of the present application uses two relays to combine and match the test fixture that has been debugged, and controls the on-off state of the circuit in which the relays are located; multiple abnormal power-off faults can be randomly generated in the read-write test process to realize automatic abnormal power-off test, improve the reliability and accuracy of abnormal power-off test, and reduce the cost of the overall abnormal power-off test system and improve the compatibility.

[0038] Those skilled in the art can understand that the system structure shown in the figure does not constitute a limitation on the embodiments of the present application, and can include more or fewer components than the figure, or combine certain components, or different component arrangements.

[0039] The system embodiments described above are only schematic, and the units described as separate components can or can not be physically separate, that is, they can be located in one place or distributed on multiple network units. Part or all of the modules can be selected according to actual needs to achieve the purpose of the embodiments.

[0040] Those skilled in the art can understand that the system architecture and application scenarios described in the embodiments of the present application are for more clearly illustrating the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided by the embodiments of the present application. Those skilled in the art can know that, with the evolution of system architecture and the appearance of new application scenarios, the technical solutions provided by the embodiments of the present application are also applicable to similar technical problems.

[0041] Based on the above system structure, the following embodiments of the present application are proposed.

[0042] In a first aspect, as Figure 2 indicated, the abnormal power-off test method for the chip can be applied to the abnormal power-off test system as Figure 1 indicated, and the abnormal power-off test system includes a test fixture, a stabilized power supply, a timing on-off relay, a stepping relay and an upper computer. The test fixture includes a test control module, a fixture power module electrically connected to the test control module, a USB interface, a serial port and a chip to be tested. The output end of the stabilized power supply is connected to the positive electrode of the fixture power module through the timing on-off relay. The upper computer is connected to the USB interface through the stepping relay and connected to the test control module through the serial port. The abnormal power-off test method for the chip can include but is not limited to steps S110 to S130.

[0043] Step S110: In the case that the shutdown charging function of the test fixture is closed, the test control module responds to the read-write test instruction sent by the upper computer through the serial port to perform read-write test on the chip to be tested.

[0044] Step S120: During the read-write test, the upper computer responds to the random power-off control instruction to control the working state of the timing on-off relay and the stepping relay, continuously performs multiple power-off controls, and manufactures multiple power-off faults. The power-off control instruction is one of the following: timing power-off single mode instruction, stepping power-off single mode instruction and combined power-off mode instruction.

[0045] Step S130: The test control module automatically records the read-write test result after each power-off fault occurs, and automatically returns the read-write test result to the upper computer through the serial port, so as to realize the abnormal power-off test on the chip to be tested.

[0046] According to some embodiments of the present application, before step S110, the abnormal power-off test method of the chip further comprises: the test fixture receiving an input power-off charging off instruction when the original equipment manufacturer unlocking switch is turned on; and in response to the power-off charging off instruction, the power-off charging function is turned off. After the power-off charging function is turned off, the test fixture can only be charged in the power-on state, that is, the charging will automatically change from the power-off state to the power-on state, thereby laying a foundation for simulating abnormal power-off failure and performing abnormal power-off test.

[0047] The specific process of turning off the power-off charging function is as follows: first, enter the developer options and turn on the OEM switch (original equipment manufacturer unlocking switch); and then input a specific power-off charging off instruction by using a command line instruction to turn off the power-off charging function. For test fixtures using different CPU platforms, the debugging codes used when turning off the power-off charging function are different, and the present application does not specifically limit the debugging codes used to turn off the power-off charging function.

[0048] Further explanation of step S110, the read-write test performed by the test control module on the chip under test in response to the read-write test instruction specifically refers to: the test control module performs a write operation to write test data into the chip under test, and then the chip under test stores the test data; the test control module then performs a read operation to read the test data from the chip under test to obtain read-back data; the read-back data is compared with the test data to obtain a read-write test result, so as to judge the correctness of the read-write and thus judge the performance of the chip under test.

[0049] Further explanation of step S120, the working state of the timing on-off relay includes: a normally open state and a timing power-off state; when the timing on-off relay works in the normally open state, the circuit between the output end of the voltage stabilizing power supply and the positive electrode of the fixture power module remains conductive; when the timing on-off relay works in the timing power-off state, the circuit between the output end of the voltage stabilizing power supply and the positive electrode of the fixture power module is conductive at timing.

[0050] Further explanation of step S120, the working state of the stepping relay includes: a normally open state and a stepping power-off state; when the stepping relay works in the normally open state, the circuit between the host computer and the USB interface remains conductive; when the stepping relay works in the stepping power-off state, the circuit between the host computer and the USB interface is powered off once every stepping time interval.

[0051] Further to step S120, the random power-off control instruction refers to that in a long test period, the power-off control instruction received by the upper computer can be a timing power-off single mode instruction, or a step power-off single mode instruction, or a combined power-off mode instruction. Taking an example, assuming that the complete test period is 72 hours, and the complete test period includes test sub-periods (for example, 4 hours for one test sub-period). In the 72 hours, the power-off fault manufacturing mode is switched randomly; that is, in each test sub-period, the timing power-off single mode instruction, or the step power-off single mode instruction, or the combined power-off mode instruction is executed randomly. For example, in the first test sub-period, the timing power-off single mode instruction is executed to singlely manufacture the timing power-off fault; in the second test sub-period, the step power-off single mode instruction is executed to singlely manufacture the step power-off fault; in the third test sub-period, the combined power-off mode instruction is executed to simultaneously manufacture the step power-off fault and the timing power-off fault; in the fourth test sub-period, the step power-off single mode instruction is executed, and so on. Based on the random power-off control instruction, the power-off control is performed randomly and continuously for multiple times. It should be noted that the random power-off control instruction can be set by the upper computer.

[0052] Further to step S130, step S130 includes that after each power-off fault occurs, the test control module of the test fixture automatically records and prints all test states of the power-off test process by using a log, and reads and writes the test results, returns the log recording the read and written test results to the upper computer, and completes the abnormal power-off test on the chip under test. Then, the upper computer analyzes the test results based on the overall log, so as to evaluate the chip test results, and judge whether the chip under test is abnormal and evaluate the performance of the chip under test.

[0053] It should be noted that the abnormal power-off test on the chip under test is a dead loop in the embodiment of the present application, and when the preset overall test period is reached, the abnormal power-off test on the chip under test is stopped. It can be understood that in order to ensure the reliability of the abnormal power-off test, usually, thousands of times or even more times of power-off test (for example, 5000 times of step power-off and power-on) are required to meet the test requirements. Therefore, under the premise of meeting the test requirements, the length of the overall test period is not specifically limited in the embodiment of the present application.

[0054] In the process of testing the to-be-tested chip by the abnormal power-off test system through steps S110 to S130, first, the test control module performs read-write test on the to-be-tested chip in response to the read-write test instruction sent by the host computer through the serial port under the condition that the shutdown charging function of the test fixture is closed; then, in the process of read-write test, the host computer controls the working state of the timing on-off relay and the stepping relay in response to the random power-off control instruction, continuously performs multiple power-off control, and manufactures multiple power-off faults; wherein, the power-off control instruction is one of the following: timing power-off single mode instruction, stepping power-off single mode instruction, and combined power-off mode instruction; thereby, multiple abnormal power-off faults can be randomly manufactured in the process of read-write test to simulate actual multiple abnormal power-off faults, laying a foundation for realizing automatic abnormal power-off test; finally, the test control module automatically records the read-write test result after each power-off fault occurs, and automatically returns the read-write test result to the host computer through the serial port to realize abnormal power-off test on the to-be-tested chip; automatic abnormal power-off test is realized, and the reliability and accuracy of abnormal power-off test are improved. Therefore, the embodiment of the application can randomly manufacture multiple abnormal power-off faults, realize automatic abnormal power-off test, and improve the reliability and accuracy of abnormal power-off test.

[0055] According to some embodiments of the application, when the power-off control instruction is a timing power-off single mode instruction, step S120 is further described as follows.

[0056] Step S210: the host computer controls the stepping relay to work in the normally open state in response to the timing power-off single mode instruction.

[0057] Step S220: according to the first fixed time delay and the second fixed time delay, the timing on-off relay is controlled to work in the timing power-off state, continuously and repeatedly performs multiple timing power-off control, and manufactures multiple timing power-off faults.

[0058] It should be noted that in the single timing power-off fault manufacturing mode, the stepping relay works in the normally open state, so that the circuit between the host computer and the USB interface of the test fixture remains conductive, and power supply is provided to maintain the test fixture to be turned on. At the same time, the timing on-off relay works in the timing power-off state to manufacture multiple timing power-off faults.

[0059] Through steps S210 to S220, the single timing power-off fault manufacturing mode is realized, which is conducive to enriching the types of manufactured power-off faults, enriching the abnormal power-off test scene, and improving the reliability of abnormal power-off test.

[0060] According to some embodiments of the present application, when the power-off control instruction is a step-down power-off single mode instruction, further description of step S120 is as follows: the host computer controls the working states of the timing on-off relay and the step-down relay in response to the random power-off control instruction, and continuously performs multiple power-off controls to create multiple power-off faults, including but not limited to steps S310 to S320.

[0061] Step S310: The host computer controls the timing on-off relay to work in a normally open state and not to work in a timing power-off state in response to the step-down power-off single mode instruction.

[0062] Step S320: The host computer controls the step-down relay to work in a step-down power-off state according to a preset step value and a preset third fixed time delay, continuously performs multiple step-down power-off controls, and creates multiple step-down power-off faults.

[0063] It should be noted that in the single step-down power-off fault creation mode, the timing on-off relay works in the normally open state, so that the circuit between the output end of the voltage stabilizing power supply and the positive electrode of the jig power module of the test fixture is turned on, the test fixture is powered, and the test fixture is ensured to be turned on. At the same time, the step-down relay works in the step-down power-off state to create multiple step-down power-off faults.

[0064] Through steps S310 to S320, the single step-down power-off fault creation mode is realized, which is conducive to enriching the types of created power-off faults, enriching the abnormal power-off test scenarios, and further improving the reliability of the abnormal power-off test.

[0065] According to some embodiments of the present application, as shown in Figure 3 When the power-off control instruction is a combined power-off mode instruction, further description of step S120 is as follows: the host computer controls the working states of the timing on-off relay and the step-down relay in response to the random power-off control instruction, and continuously performs multiple power-off controls to create multiple power-off faults, including but not limited to steps S410 to S420.

[0066] Step S410: The host computer controls the timing on-off relay to work in a timing power-off state according to a preset first fixed time delay and a preset second fixed time delay in response to the combined power-off mode instruction, continuously performs multiple timing power-off controls, and creates multiple timing power-off faults.

[0067] Step S420: At the same time, the host computer controls the step-down relay to work in a step-down power-off state according to a preset step value and a preset third fixed time delay, continuously performs multiple step-down power-off controls, and creates multiple step-down power-off faults.

[0068] It can be understood that, although the embodiments of the present application simultaneously perform and step down power-off control, since the time parameters (the first fixed time delay and the second fixed time delay) used by the timing power-off control and the time parameters (the preset step value and the preset third fixed time delay) used by the step down power-off control are different, and the control mechanisms are different, each time the timing power-off failure is manufactured and each time the step down power-off failure is manufactured are not simultaneous. It can be that one timing power-off failure occurs, and after the timing power-off failure recovers, one or more step down power-off failures occur in succession; or during the occurrence of one timing power-off failure, one or more step down power-off failures occur; or the timing power-off failure and the step down power-off failure occur simultaneously; or one step down power-off failure occurs, and after the step down power-off failure recovers, one timing power-off failure occurs in succession, and the like. It can be seen that, in the combined power-off working mode, there are multiple occurrence situations between the timing power-off failure and the step down power-off failure, that is, there are multiple combined failures determined by the timing power-off failure and the step down power-off failure, thereby improving the randomness and diversity of the occurrence of the power-off failure.

[0069] Through steps S410 to S420, the combined power-off working mode of manufacturing the timing power-off failure and the step down power-off failure is realized, the randomness of the occurrence of the power-off failure is improved, the abnormal power-off test scene is further enriched, and the reliability of the abnormal power-off test is further improved.

[0070] According to some embodiments of the present application, the specific process of manufacturing the timing power-off failure in step S220 and step S410 is further described. Among them, according to the preset first fixed time delay and the second fixed time delay, the timing on-off relay is controlled to work in the timing power-off state, and multiple timing power-off controls are continuously and repeatedly performed to manufacture multiple timing power-off failures, including but not limited to steps S510 to S530.

[0071] Step S510: When the timing on-off relay is powered on, and after the power-on lasts for the first fixed time delay, the timing on-off relay is powered off to disconnect the circuit between the output end of the voltage stabilizing power supply and the positive electrode of the fixture power module, and one timing power-off failure is manufactured.

[0072] Step S520: When the timing on-off relay is powered off, and after the power-off lasts for the second fixed time delay, the timing on-off relay is powered on to restore the conduction of the circuit between the output end of the voltage stabilizing power supply and the positive electrode of the fixture power module.

[0073] Step S530: According to the first fixed time delay and the second fixed time delay, the timing on-off relay is continuously and cyclically controlled to be powered on and powered off to manufacture multiple timing power-off failures.

[0074] It can be understood that the first fixed time delay and the second fixed time delay can be the same or different. The test manager can debug the timing on-off relay and set the values of the first fixed time delay and the second fixed time delay according to the actual test requirements. Therefore, the application does not make specific limitations on the values of the first fixed time delay and the second fixed time delay.

[0075] Through steps S510 to S530, the timing on-off relay is alternately controlled to be powered on and powered off through the preset first fixed time delay and the second fixed time delay, so as to realize the timing power-off failure occurrence mechanism; and it is beneficial to simulate the timing power-off failure and enrich the abnormal power-off test scene.

[0076] Taking an example to illustrate steps S510 to S530, when the first fixed time delay is set to 2 seconds and the second fixed time delay is set to 5 seconds, the specific process of manufacturing the timing power-off failure is as follows: the timing on-off relay is powered on, and after the power-on lasts for 2 seconds, the timing on-off relay is powered off to occur the first timing power-off failure; after the power-off lasts for 5 seconds, the timing on-off relay is powered on, and after the power-on lasts for 2 seconds, the timing on-off relay is powered off to occur the second timing power-off failure; after the power-off lasts for 5 seconds, the timing on-off relay is powered on, and after the power-on lasts for 2 seconds, the timing on-off relay is powered off to occur the third timing power-off failure; and so on, the timing on-off relay is alternately controlled to be powered on and powered off to realize the occurrence of multiple timing power-off failures.

[0077] According to some embodiments of the application, the specific process of manufacturing the step-down power-off state in steps S320 and S420 is further illustrated. Wherein, according to the preset step-down value and the preset third fixed time delay, the step-down relay is controlled to work in the step-down power-off state, and multiple step-down power-off controls are continuously performed to manufacture multiple step-down power-off failures, including but not limited to steps S610 to S650.

[0078] Step S610: Add the obtained last first power-on duration time delay and the preset step-down value to obtain an updated current second power-on duration time delay.

[0079] Step S620: When the step-down relay is powered on and after the power-on lasts for the second power-on duration time delay, the step-down relay is powered off to disconnect the circuit between the host computer and the USB interface, and to manufacture a step-down power-off failure.

[0080] Step S630: When the step-down relay is powered off and after the power-off lasts for the third fixed time delay, the step-down relay is powered on to restore the conduction of the circuit between the host computer and the USB interface.

[0081] Step S640: add the current second power-on duration and the preset step value to obtain an updated third power-on duration; and control the step relay to power off to make the next step power-off fault according to the third power-on duration.

[0082] Step S650: repeatedly and continuously update the power-on duration and perform step power-off to make multiple step power-off faults.

[0083] It can be understood that the preset step value can be 0.1 second, 0.2 second, or the like. The test manager can debug the step relay and set the value of the preset step value according to actual test requirements. Therefore, the application does not specifically limit the value of the preset step value.

[0084] It can be understood that the third fixed time delay can be 5 seconds, 8 seconds, or the like. The test manager can set the value of the third fixed time delay according to actual test requirements. Therefore, the application does not specifically limit the value of the third fixed time delay.

[0085] Through steps S610 to S650, the power-off interval time is continuously updated by the preset step value, and the timing on-off relay is controlled to power on and power off according to the step power-off interval time and the preset third fixed time delay, so that the step power-off fault occurrence mechanism is realized, the step power-off fault is made, the randomness of the power-off fault occurrence is improved, and the abnormal power-off test scene is enriched.

[0086] An example is used to illustrate steps S610 to S650. When the preset step value is set to 0.1 second and the third fixed time delay is set to 5 seconds, the specific process of making the step power-off fault is as follows: the step relay is powered on, and after the power-on duration of 0.1 second, the step relay is powered off (that is, power-off), and the first step power-off fault occurs; after the power-off duration of 5 seconds, the step relay is powered on, and after the power-on duration of 0.2 seconds (the second power-on duration of 0.2 seconds is obtained by adding the first power-on duration of 0.1 second and the preset step value of 0.1 second), the step relay is powered off, and the second step power-off fault occurs; after the power-off duration of 5 seconds, the step relay is powered on, and after the power-on duration of 0.3 seconds (the second power-on duration of 0.3 seconds is obtained by adding the first power-on duration of 0.2 second and the preset step value of 0.1 second), the step relay is powered off, and the third step power-off fault occurs; and the like, the timing on-off relay is alternately controlled to power on and power off, and multiple timing power-off faults are realized.

[0087] As shown in FIG. 8, the application further provides an electronic device, which comprises: Figure 4

[0088] ​The processor 401 can be implemented by a general central processing unit, a microprocessor, an application specific integrated circuit, or one or more integrated circuits, and is configured to execute related programs to implement the technical solutions provided by the embodiments of the present application.

[0089] The memory 402 can be implemented by a read-only memory, a static storage device, a dynamic storage device, or a random access memory. The memory 402 can store an operating system and other application programs. When the technical solutions provided by the embodiments of the present application are implemented by software or firmware, the related program codes are stored in the memory 402 and are called and executed by the processor 401 to implement the chip abnormal power-off test method of the embodiments of the present application.

[0090] The input / output interface 403 is configured to implement information input and output.

[0091] The communication interface 404 is configured to implement the communication interaction between the device and other devices. The communication can be implemented by a wired manner (for example, a USB, a network cable, etc.) or a wireless manner (for example, a mobile network, WIFI, Bluetooth, etc.).

[0092] The bus 405 is configured to transmit information between various components (for example, the processor 401, the memory 402, the input / output interface 403, and the communication interface 404) of the device.

[0093] The processor 401, the memory 402, the input / output interface 403, and the communication interface 404 are connected to each other by the bus 405 to realize the communication connection between the device.

[0094] The embodiments of the present application further provide a storage medium, which is a computer readable storage medium. The storage medium stores a computer program. The computer program is executed by a processor to implement the chip abnormal power-off test method.

[0095] Memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer-executable programs. In addition, the memory can include a high-speed random access memory and can also include a non-transitory memory, such as at least one magnetic disk storage device, a flash memory device, or other non-transitory solid-state memory device. In some embodiments, the memory can optionally include a memory disposed remotely with respect to the processor, which can be connected to the processor through a network. Examples of the above network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof. The above-described device embodiments are merely illustrative, and units described as separate components can or can not be physically separated, implemented in one place, or distributed to multiple network units. Part or all of the modules can be selected according to actual needs to achieve the purpose of the present embodiment.

[0096] Those of ordinary skill in the art will understand that all or some of the steps in the above disclosed method, system can be implemented as software, firmware, hardware, and appropriate combinations thereof. Some or all of the physical components can be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software can be distributed on a computer readable medium, which can include computer storage media (or non-transitory media) and communication media (or transitory media). As is well known to those of ordinary skill in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and that can be accessed by a computer. In addition, it is well known to those of ordinary skill in the art that communication media typically includes computer readable instructions, data structures, program modules or other data in modulated data signals such as carrier waves or other transport mechanisms, and can include any information delivery medium.

[0097] The above is a specific description of the preferred embodiments of the present application, but the present application is not limited to the above embodiments. Those skilled in the art can make various equivalent modifications or replacements without departing from the spirit of the present application, and these equivalent modifications or replacements are all included in the scope defined by the present application.

Claims

1. A method of testing a chip for an abnormal power-down, characterized by, The application is applied to an abnormal power-off test system, and the system comprises a test fixture, a stabilized power supply, a timing on-off relay, a step relay and an upper computer; wherein the test fixture comprises a test control module, a fixture power module electrically connected with the test control module, a USB interface, a serial port, a chip to be tested; the output end of the stabilized power supply is connected with the positive pole of the fixture power module through the timing on-off relay; the upper computer is connected with the USB interface through the step relay and connected with the test control module through the serial port; The method comprises: In the case that the shutdown charging function of the test fixture is closed, the test control module performs read-write test on the chip to be tested in response to the read-write test instruction sent by the upper computer through the serial port; In the read-write test process, the upper computer controls the working state of the timing on-off relay and the step relay in response to random power-off control instructions, continuously performs multiple power-off controls and manufactures multiple power-off faults; wherein the power-off control instruction is one of the following: a timing power-off single mode instruction, a step power-off single mode instruction and a combined power-off mode instruction; The test control module automatically records the read-write test result after each power-off fault occurs and automatically returns the read-write test result to the upper computer through the serial port, so as to realize abnormal power-off test on the chip to be tested.

2. The method of claim 1, wherein, When the power-off control instruction is the timing power-off single mode instruction, the upper computer controls the working state of the timing on-off relay and the step relay in response to random power-off control instructions, continuously performs multiple power-off controls and manufactures multiple power-off faults, which comprises: The upper computer controls the step relay to work in a normally open state and not work in a step power-off state in response to the timing power-off single mode instruction; According to the first fixed time delay and the second fixed time delay, the timing on-off relay is controlled to work in a timing power-off state, continuously and repeatedly performs multiple timing power-off controls and manufactures multiple timing power-off faults.

3. The method of claim 1, wherein, When the power-off control instruction is the step power-off single mode instruction, the upper computer controls the working state of the timing on-off relay and the step relay in response to random power-off control instructions, continuously performs multiple power-off controls and manufactures multiple power-off faults, which comprises: The upper computer controls the timing on-off relay to work in a normally open state and not work in a timing power-off state in response to the step power-off single mode instruction; According to the preset step value and the third fixed time delay, the step relay is controlled to work in a step power-off state, continuously performs multiple step power-off controls and manufactures multiple step power-off faults.

4. The method of claim 1, wherein, When the power-off control instruction is the combined power-off mode instruction, the upper computer controls the working state of the timing on-off relay and the step relay in response to random power-off control instructions, continuously performs multiple power-off controls and manufactures multiple power-off faults, which comprises: The host computer controls the timing on-off relay to work in a timing power-off state according to preset first and second fixed time delays in response to the combined power-off mode instruction, continuously performs multiple timing power-off controls, and causes multiple timing power-off faults. Meanwhile, the host computer controls the stepping relay to work in a stepping power-off state according to a preset stepping value and a preset third fixed time delay, continuously performs multiple stepping power-off controls, and causes multiple stepping power-off faults.

5. The method of testing for abnormal power-down of a chip according to claim 2 or 4, wherein, The host computer controls the timing on-off relay to work in a timing power-off state according to preset first and second fixed time delays in response to the combined power-off mode instruction, continuously performs multiple timing power-off controls, and causes multiple timing power-off faults. When the timing on-off relay is powered on and the power-on lasts for the first fixed time delay, the timing on-off relay is powered off, the circuit between the output end of the voltage stabilizing power supply and the positive pole of the jig power module is disconnected, and a timing power-off fault is caused. When the timing on-off relay is powered off and the power-off lasts for the second fixed time delay, the timing on-off relay is powered on, the circuit between the output end of the voltage stabilizing power supply and the positive pole of the jig power module is restored to be conductive, and a timing power-off fault is caused. According to the first and second fixed time delays, the timing on-off relay is alternately powered on and powered off in a cycle, and multiple timing power-off faults are caused.

6. The method of testing for abnormal power-down of a chip according to claim 3 or 4, wherein, The host computer controls the timing on-off relay to work in a timing power-off state according to preset first and second fixed time delays in response to the combined power-off mode instruction, continuously performs multiple timing power-off controls, and causes multiple timing power-off faults. The first power-on duration obtained last time is added to the preset stepping value to obtain an updated current second power-on duration. When the timing on-off relay is powered on and the power-on lasts for the first fixed time delay, the timing on-off relay is powered off, the circuit between the output end of the voltage stabilizing power supply and the positive pole of the jig power module is disconnected, and a timing power-off fault is caused. When the timing on-off relay is powered off and the power-off lasts for the second fixed time delay, the timing on-off relay is powered on, the circuit between the output end of the voltage stabilizing power supply and the positive pole of the jig power module is restored to be conductive, and a timing power-off fault is caused. The first power-on duration obtained last time is added to the preset stepping value to obtain an updated current second power-on duration. The first power-on duration obtained last time is added to the preset stepping value to obtain an updated current second power-on duration.

7. The method of claim 1, wherein, The test control module responds to the read-write test instruction sent by the host computer through the serial port, and the method further comprises the following steps before performing read-write test on the chip to be tested: The test jig receives an input shutdown charging off instruction when the original equipment manufacturer unlocking switch is turned on. The shutdown charging function is turned off in response to the shutdown charging off instruction.

8. An abnormal power down test system, comprising: The test control module responds to the read-write test instruction sent by the host computer through the serial port, and the method further comprises the following steps before performing read-write test on the chip to be tested: The test fixture, the voltage stabilizing power supply, the timing on-off relay, the stepping relay and the upper computer; wherein the test fixture comprises a test control module, a fixture power supply module electrically connected with the test control module, a USB interface, a serial port and a chip to be tested; an output end of the voltage stabilizing power supply is connected with a positive pole of the fixture power supply module through the timing on-off relay; the upper computer is connected with the USB interface through the stepping relay and connected with the test control module through the serial port; the abnormal power-off test system is used for executing the abnormal power-off test method for the chip as claimed in any one of claims 1 to 7.

9. An electronic device, comprising: The system comprises at least one processor and a memory connected with the at least one processor in communication; the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the abnormal power-off test method for the chip as claimed in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer readable storage medium stores computer executable instructions for causing a computer to execute the abnormal power-off test method for the chip as claimed in any one of claims 1 to 7.

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