Automatic chip pressure testing method and system

Abstract

The invention discloses an automatic chip pressure testing method and system. The automatic chip pressure testing method comprises the steps that S1, a pressure testing program is divided into different compiling targets according to different function modules; s2, calling a compiling target calling test case by the pressure test script, sending the test script to a tested unit to execute configuration and test, and judging a test execution condition in real time; s3, the pressure test script generates test excitation or judges a test result through the auxiliary equipment in the test process; if the pressure test item does not need to use the test auxiliary equipment to generate test excitation or judge a test result, executing the step S4; if the pressure test time is not reached, circularly executing the step S2 and the step S3; and S4, the pressure test generates a test report by storing the test LOG. According to the invention, loss caused by interruption of a test process due to accidental interference factors in a test environment can be reduced, design defects of an abnormal field positioning chip can be rapidly reproduced, and the chip pressure test efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular to a chip stress testing environment and a chip automated stress testing method and system capable of automatically detecting and processing abnormal items during the stress testing process. Background Art

[0002] With the rapid development of the integrated circuit industry, in the testing phase of chip research and development, in addition to conventional functional tests and electrical parameter tests on specific chip functions, design defects in the chip's digital logic or timing can also be detected through targeted stress tests under specific functions to increase the test load, so as to ensure the performance and stability of the chip under high load or extreme conditions, and to detect hidden problems before the chip is mass-produced to avoid risks. Chip stress testing is an important part of chip testing, mainly used to determine the stability and reliability of the chip under extreme conditions. Stress testing is a non-functional testing technology used to determine the stability and robustness of the system. It checks all hypothetical scenarios through automatically generated simulation models. Stress testing usually involves running the chip for a long time under extreme conditions to observe whether the chip will fail or degrade in performance. This may include extreme conditions such as high temperature, high voltage, or long working hours.

[0003] However, the difficulty in stress testing is that during the long test cycle of stress testing, the test personnel implementing the process are often unable to monitor the test process in real time. Therefore, when test anomalies occur, protecting the test site and quickly reproducing the anomalies are the key to improving test efficiency. Summary of the invention

[0004] A series of simplified concepts are introduced in the Summary of the Invention, which are all simplifications of the prior art in the field, and will be further described in detail in the Detailed Description of the Invention. The Summary of the Invention of the present invention does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the scope of protection of the claimed technical solution.

[0005] The technical problem to be solved by the present invention is to provide a method that can reduce the losses caused by the interruption of the test process caused by occasional interference factors in the test environment, can quickly reproduce abnormal on-site positioning chip design defects, and improve the efficiency of chip stress testing.

[0006] In order to solve the above technical problems, the present invention provides a chip automatic stress testing method, comprising the following steps:

[0007] S1, divide the stress test program into different compilation targets according to different functional modules, and distinguish the functions of each functional module by instructions;

[0008] S2, the stress test script calls the test case by calling the compilation target to implement the scheduling management of the test case, sends the test script to the unit under test for execution configuration and testing, receives the response from the unit under test, and determines the test execution status in real time;

[0009] S3, the stress test script generates test stimuli or determines test results through auxiliary equipment during the test process;

[0010] If the stress test item does not require the aid of test auxiliary equipment to generate test stimulus or determine test results, then execute step S4;

[0011] If the pressure test time has not been reached, step S2 and step S3 are executed in a loop; if the pressure test time has been reached, step S4 is executed;

[0012] S4, the stress test generates a test report by saving the test LOG.

[0013] Preferably, the chip automated stress testing method is further improved, wherein the instruction includes: a host computer request frame and a slave terminal response frame;

[0014] The host computer request frame includes a frame header, a length field, a command ID, a command type, a data field, and a check field arranged in sequence;

[0015] The lower-end response frame includes a frame header, a length field, and a data field arranged in sequence.

[0016] Preferably, the chip automated stress testing method is further improved, and during the execution of step S2 and step S3, if unexpected behavior occurs, the exception item processing flow is entered.

[0017] Preferably, the chip automatic stress testing method is further improved, if the stress testing time is met, it is determined that the test of the current test item is finished; if the stress testing time is not met, it is determined whether an abnormality occurs;

[0018] If a test exception occurs, the number of times the exception occurs is recorded; if no exception occurs, the unit under test is reset and a test stimulus is generated;

[0019] If the number of exceptions exceeds the limit, the current test item is judged to be over; if the number of exceptions does not exceed the limit, it is judged whether the serial port is available;

[0020] If the serial port is unavailable, the unit under test is reset after the serial port is restarted and the test stimulus is generated; if the serial port is available, the exception code is read to analyze whether it is a recoverable error;

[0021] If it is a recoverable error, the serial port is restarted and the unit under test is reset and test stimulus is generated; if it is an unrecoverable error, the context instructions are extracted from the LOG, the debug interface records the chip system register value, and the control test auxiliary equipment records the external stimulus parameters and then determines that the current test item is finished.

[0022] In order to solve the above technical problems, the present invention provides a chip automatic stress testing system, which can be implemented based on the hardware and computer programming technology means of the prior art, and is used to execute any one of the above chip automatic stress testing methods, including: testing a host computer and testing a slave terminal;

[0023] The test host computer includes: a computer running the stress test software, which compiles and downloads different compilation targets to perform stress testing through stress test scripts;

[0024] The stress test software includes: stress test script, test API, test instruction set, test auxiliary device driver, debugger driver and serial port driver;

[0025] The test lower end includes: test auxiliary equipment, unit under test and peripheral circuits of the unit under test;

[0026] The test auxiliary equipment is used to generate test stimuli, determine the test results of the unit under test, monitor communication link data, and reset the hardware;

[0027] The unit under test is formed with the unit under test embedded software, and the unit under test embedded software is divided into different compilation targets according to the chip module; each compilation target realizes the reception and analysis of the test instructions of the host computer, the response execution of the test instructions, the feedback of the test instruction execution results, the upload of the unit under test software and hardware parameters and the software and hardware reset when abnormal test results occur;

[0028] The peripheral circuits of the UUT include: the hardware circuits necessary for the normal operation of the UUT functions, the hardware interface circuits for testing the host computer test signaling interaction, and the debugging interface circuits.

[0029] Preferably, the chip automated stress testing system is further improved, and the test auxiliary equipment driver and the test auxiliary equipment interactive program-controlled test equipment instructions are tested.

[0030] Preferably, the chip automated stress testing system is further improved, and the debugger driver serves as a download channel for the stress testing program of the unit under test.

[0031] Preferably, the chip automated stress testing system is further improved, and the serial port driver is used as a stress test signaling channel for the unit under test.

[0032] The working principle of the present invention is as follows:

[0033] When performing stress testing, the test host computer runs the test software, which includes stress test scripts, test APIs, test instruction sets, and necessary drivers for implementing the above function calls. The test script implements the following functions by calling the test APIs and test instruction sets:

[0034] 1) Stress test case management: mainly includes the execution sequence of test cases and the running time management of a single test case;

[0035] 2) Test case implementation: The test software uses the serial port, JLINK or other chip test interface as the test signaling channel to send instructions to schedule the embedded end test process to implement stress testing of specific chip functions;

[0036] 3) Automatic control: The instrument equipment is controlled through the control command set provided by the instrument manufacturer to realize the functions of test stimulus generation and test data collection;

[0037] 4) Test information collection: record the timestamps of the start and end of the stress test, print out information during the test, and compile a test report;

[0038] 5) Exception handling: When the embedded end returns an unexpected response, the time when the test exception occurs and the context instructions are recorded. The test software attempts to call the signaling channel to initialize the signaling channel and send instructions to try to soft reset the chip, or control the programmable digital power supply to hard reset the chip through instructions.

[0039] The UUT is usually a prototype verification stage before chip tape-out, usually an FPGA development board, and after tape-out it is an engineering sample produced in small batches. The embedded programs running on the UUT are divided into the following categories:

[0040] 1) Signaling driver: realize the reception and analysis of host computer instructions and the upload of status codes after the test process is completed;

[0041] 2) General control program: realizes the chip configuration of chip resources through the signaling channel, including register and memory read, write and erase, GPIO and other basic peripherals, and chip software reset functions;

[0042] 3) Test program: A set of test programs consisting of test sub-processes for a specific function of the chip during stress testing.

[0043] The present invention can effectively implement stress testing of specific chip functions, and can effectively monitor and identify chip anomalies and environmental anomalies during stress testing. When chip anomalies occur, abnormal items are recorded to facilitate testers to analyze and locate problems later. When environmental anomalies occur, the test process can be restored. The impact caused by the inability of testers to monitor the test process in real time is eliminated, and test anomalies can be protected and quickly reproduced, thereby improving test efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The drawings of the present invention are intended to illustrate the general characteristics of the methods, structures and / or materials used in specific exemplary embodiments of the present invention, and to supplement the description in the specification. However, the drawings of the present invention are schematic diagrams not drawn to scale, and thus may not accurately reflect the precise structure or performance characteristics of any given embodiment, and the drawings of the present invention should not be interpreted as limiting or restricting the range of values ​​or properties covered by the exemplary embodiments of the present invention. The present invention is further described in detail below in conjunction with the drawings and specific embodiments:

[0045] Figure 1 It is a schematic diagram of the process flow of the chip automatic pressure testing method of the present invention.

[0046] Figure 2 It is a schematic diagram of the frame structure of the instruction of the present invention.

[0047] Figure 3 It is a schematic diagram of the abnormal item processing process of the present invention.

[0048] Figure 4 It is a schematic diagram of the chip automatic stress testing system architecture of the present invention. DETAILED DESCRIPTION

[0049] The following is an explanation of the embodiments of the present invention by specific specific embodiments, and those skilled in the art can fully understand other advantages and technical effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through different specific embodiments, and the details in this specification can also be applied based on different viewpoints, and various modifications or changes can be made without deviating from the general design concept of the invention. It should be noted that, in the absence of conflict, the following embodiments and the features in the embodiments can be combined with each other. The following exemplary embodiments of the present invention can be implemented in a variety of different forms and should not be interpreted as being limited to the specific embodiments described herein. It should be understood that these embodiments are provided to make the disclosure of the present invention thorough and complete, and to fully convey the technical solutions of these exemplary specific embodiments to those skilled in the art. It should be understood that when an element is referred to as "connected" or "coupled" to another element, the element can be directly connected or coupled to another element, or there can be an intermediate element. The difference is that when an element is referred to as "directly connected" or "directly coupled" to another element, there is no intermediate element. In all figures, the same reference numerals always represent the same element. As used herein, the term "and / or" includes any combination and all combinations of one or more related listed items.

[0050] First embodiment;

[0051] refer to Figure 1 As shown, the present invention provides a chip automatic stress testing method, comprising the following steps:

[0052] S1, divide the stress test program into different compilation targets according to different functional modules, and distinguish the functions of each functional module by instructions; for example, UART, SPI, ADC and other functional modules are different compilation targets, which can avoid the problem of not being able to load all test codes due to the limitation of chip memory resources;

[0053] Exemplary, reference Figure 2 As shown, the instruction includes: a request frame of the upper computer and a response frame of the lower end;

[0054] The host computer request frame includes a frame header, a length field, a command ID, a command type, a data field, and a check field arranged in sequence;

[0055] The lower-end response frame includes a frame header, a length field, and a data field arranged in sequence;

[0056] S2, the stress test script calls the test case by calling the compilation target, sends the test script to the unit under test for execution configuration and testing, and receives the response from the unit under test to determine the test execution status in real time;

[0057] For example, the stress test script calls the IDE's API interface to compile the selected compilation target and download the test code through the debugger, thus implementing the scheduling management of test cases;

[0058] S3, the stress test script generates test stimuli or determines test results through auxiliary equipment during the test process;

[0059] If the stress test item does not require the aid of test auxiliary equipment to generate test stimulus or determine test results, then execute step S4;

[0060] If the pressure test time has not been reached, step S2 and step S3 are executed in a loop; if the pressure test time has been reached, step S4 is executed;

[0061] S4, the stress test generates a test report by saving the test LOG.

[0062] Although the above embodiment does not include an exception handling process, it can automatically perform stress testing without manual monitoring, thereby improving testing efficiency. However, the technical effect is not optimal.

[0063] Accordingly, the above embodiment is further improved. During the execution of step S2 and step S3, if unexpected behavior occurs, the abnormal item processing flow is entered, thereby ensuring that the stress test can be automatically corrected and executed smoothly. The logic reference Figure 3 As shown;

[0064] If the stress test time is met, it is determined that the current test item is finished; if the stress test time is not met, it is determined whether an exception occurs;

[0065] If a test exception occurs, the number of times the exception occurs is recorded; if no exception occurs, the unit under test is reset and a test stimulus is generated;

[0066] If the number of exceptions exceeds the limit, the current test item is judged to be over; if the number of exceptions does not exceed the limit, it is judged whether the serial port is available;

[0067] If the serial port is unavailable, the unit under test is reset after the serial port is restarted and the test stimulus is generated; if the serial port is available, the exception code is read to analyze whether it is a recoverable error;

[0068] If it is a recoverable error, the serial port is restarted and the unit under test is reset and test stimulus is generated; if it is an unrecoverable error, the context instructions are extracted from the LOG, the debug interface records the chip system register value, and the control test auxiliary equipment records the external stimulus parameters and then determines that the current test item is finished.

[0069] In order to avoid the risk of test interruption caused by random interference in the stress test environment, the present invention adds an attempt to restart the serial port or restart the unit under test to try to continue executing the test item until the test item is judged to have failed. When the test item is judged to have failed, the program will record the stimulus information generated by the kernel system register of the unit under test and the test auxiliary equipment for the tester to analyze and reproduce the problem. In addition, the stress test script will automatically execute the test content of the next test item, which greatly reduces the time of the stress test.

[0070] The present invention is not limited by the hardware resources of the chip itself. The method for handling stress test exceptions can not only effectively check for potential functional abnormalities of the chip, but also can avoid the problem of stress test interruption caused by test environment abnormalities to a great extent, thereby greatly improving the test efficiency.

[0071] Second embodiment;

[0072] refer to Figure 4 As shown, the present invention provides a chip automatic stress testing system, which is used to execute any one of the chip automatic stress testing methods described above, including: a test host computer and a test slave terminal;

[0073] The test host computer can be understood as a computer equipped with necessary drivers and software required for the test software to run. It compiles and downloads different compilation targets to perform stress testing through stress test scripts;

[0074] The stress test software includes: stress test script, test API, test instruction set, test auxiliary device driver, debugger driver and serial port driver;

[0075] The test lower end includes: test auxiliary equipment, unit under test and peripheral circuits of the unit under test;

[0076] The test auxiliary equipment is used to generate test stimuli, determine the test results of the unit under test, monitor communication link data, and reset the hardware;

[0077] The unit under test is formed with the unit under test embedded software, and the unit under test embedded software is divided into different compilation targets according to the chip module; each compilation target realizes the reception and analysis of the test instructions of the host computer, the response execution of the test instructions, the feedback of the test instruction execution results, the upload of the unit under test software and hardware parameters and the software and hardware reset when abnormal test results occur;

[0078] The peripheral circuits of the UUT include: the hardware circuits necessary for the normal operation of the UUT functions, the hardware interface circuits for testing the host computer test signaling interaction, and the debugging interface circuits.

[0079] For example, the programmable power supply can be used as a test auxiliary device to provide regular power supply to the target chip under test. However, during the test of power-on reset, power-off reset and undervoltage reset of the chip, the power supply generates corresponding test stimulus. In addition, when the test chip enters the low power consumption function, the test result can be judged by querying the power supply current.

[0080] Among them, the test auxiliary device driver and the test auxiliary device interactively program the test device instructions, the debugger driver serves as a download channel for the stress test program of the unit under test, and the serial port driver serves as a signaling channel for the stress test of the unit under test.

[0081] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. It will also be understood that, unless expressly defined herein, terms such as those defined in general dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and not interpreted in an ideal or overly formal sense.

[0082] The present invention has been described in detail above through specific implementation modes and embodiments, but these do not constitute limitations of the present invention. Without departing from the principles of the present invention, those skilled in the art may also make many variations and improvements, which should also be regarded as the protection scope of the present invention.

Claims

1. A chip automated stress testing method, characterized in that: The following steps are involved: S1, divide the stress test program into different compilation targets according to different functional modules, and distinguish the functions of each functional module by instructions; S2, the stress test script calls the test case by calling the compilation target, sends the test script to the unit under test for execution configuration and testing, and receives the response from the unit under test to determine the test execution status in real time; S3, the stress test script generates test stimuli or determines test results through auxiliary equipment during the test process; If the stress test item does not require the aid of test auxiliary equipment to generate test stimulus or determine test results, then execute step S4; If the pressure test time has not been reached, step S2 and step S3 are executed in a loop; if the pressure test time has been reached, step S4 is executed; S4, the stress test generates a test report by saving the test LOG.

2. The chip automated stress testing method according to claim 1, characterized in that: The instructions include: a request frame from the upper computer and a response frame from the lower computer; The host computer request frame includes a frame header, a length field, a command ID, a command type, a data field, and a check field arranged in sequence; The lower-end response frame includes a frame header, a length field, and a data field arranged in sequence.

3. The chip automated stress testing method according to claim 1, characterized in that: During the execution of step S2 and step S3, if unexpected behavior occurs, the abnormal item processing flow is entered.

4. The chip automated stress testing method according to claim 3, characterized in that: If the stress test time is met, it is determined that the current test item is finished; if the stress test time is not met, it is determined whether an exception occurs; If a test exception occurs, the number of times the exception occurs is recorded; If no exception occurs, the unit under test is reset and a test stimulus is generated; If the number of exceptions exceeds the limit, the current test item is judged to be over; if the number of exceptions does not exceed the limit, it is judged whether the serial port is available; If the serial port is unavailable, the unit under test is reset after the serial port is restarted and the test stimulus is generated; if the serial port is available, the exception code is read to analyze whether it is a recoverable error; If it is a recoverable error, reset the unit under test after restarting the serial port and generate test stimulus; If it is an unrecoverable error, the context instructions are extracted from the LOG, the debug interface records the chip system register value, and the control test auxiliary equipment records the external stimulus parameters and then determines that the current test item is finished.

5. A chip automated stress testing system, used to execute the chip automated stress testing method according to any one of claims 1 to 5, characterized in that: include: Test the host computer and test the lower end; The test host computer includes: a computer running the stress test software, which compiles and downloads different compilation targets to perform stress testing through stress test scripts; The stress test software includes: stress test script, test API, test instruction set, test auxiliary device driver, debugger driver and serial port driver; The test lower end includes: test auxiliary equipment, unit under test and peripheral circuits of the unit under test; The test auxiliary equipment is used to generate test stimuli, determine the test results of the unit under test, monitor communication link data, and reset the hardware; The unit under test is formed with the unit under test embedded software, and the unit under test embedded software is divided into different compilation targets according to the chip module; each compilation target realizes the reception and analysis of the test instructions of the host computer, the response execution of the test instructions, the feedback of the test instruction execution results, the upload of the unit under test software and hardware parameters and the software and hardware reset when abnormal test results occur; The peripheral circuits of the UUT include: the hardware circuits necessary for the normal operation of the UUT functions, the hardware interface circuits for testing the host computer test signaling interaction, and the debugging interface circuits.

6. The chip automated stress testing system according to claim 6, characterized in that: Test auxiliary equipment drivers and test auxiliary equipment interactive program-controlled test equipment instructions.

7. The chip automated stress testing system as claimed in claim 6, characterized in that: The debugger driver serves as the download channel for the stress test program of the unit under test.

8. The chip automated stress testing system as claimed in claim 6, characterized in that: The serial port driver serves as the signaling channel for the stress test of the unit under test.

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