A chip function testing method, test control module, equipment and device

Abstract

The present invention discloses a chip function test method, test control module, equipment and device. When the chip to be tested releases a power-on reset signal and ends the power-on reset state, the test control module is configured for testing through the JTAG interface of the chip to be tested, and the chip to be tested and the automated test equipment are controlled to establish a synchronous state, the chip to be tested is tested and the test result is output. This technical solution is based on adding a test control module in the chip design stage, so that the automated test equipment can directly provide the chip to be tested with an external reset and an external clock according to the automated test vector to establish a synchronous state between the two, so that the chip function test can meet the requirements of the automated test equipment synchronization test method, and can quickly realize multiple function tests on the automated test equipment, effectively improving the automation degree of the function test, the test efficiency and the stability.

Description

Technical Field

[0001] The present invention relates to the field of testing technology, and in particular to a chip function testing method, a test control module, equipment and a device. Background Art

[0002] In the process of chip design and production, Design for Test (DFT) has been widely used as a key technology to ensure product quality and eliminate chips with manufacturing defects. Design for Test improves the testability of the chip, including controllability and observability, by inserting specific testability circuits during the chip design phase. This technology runs through all stages of the chip development process. During the chip production test phase, testability circuits, automatic test equipment (ATE) and automatic test patterns (ATP) are used to test the chip to eliminate chips with manufacturing defects and ensure the quality of the chip before it leaves the factory.

[0003] During the chip production test phase, automated test equipment and automated test vectors are usually used to complete non-functional testing, while functional testing relies on system test boards and test programs. However, compared with automated test equipment, system test boards have multiple disadvantages. Their design needs to be customized in combination with chip functions. This customization process may introduce unexpected problems, which leads to low test efficiency due to the need for subsequent problem handling. In addition, the system test board has poor versatility and stability, making it difficult to adapt to the needs of AC parameter testing, DC parameter testing, and injection error testing.

[0004] Therefore, the chip function testing method in the related art has technical problems such as low testing efficiency and poor stability. Summary of the invention

[0005] The main purpose of the present invention is to propose a chip function testing method, test control module, equipment and device, aiming to at least solve the technical problems of low test efficiency and poor stability in the chip function testing method in the related art.

[0006] To achieve the above object, the technical solution of the present invention is as follows:

[0007] A first aspect of the present invention provides a chip function testing method, which is applied to an automated testing device. The chip function testing method comprises:

[0008] Control the chip under test to be in power-on reset state and external reset state at the initial stage of power-on;

[0009] When the chip under test releases the power-on reset signal and ends the power-on reset state, the test control module is configured for testing through the JTAG interface of the chip under test, and the chip under test and the automated test equipment are controlled to establish a synchronization state; wherein the test control module is pre-integrated in the chip under test;

[0010] When the external reset signal of the chip under test is released and the external reset state ends, the chip under test performs a functional test preparation operation;

[0011] According to the selected functional test items, the chip under test is controlled to perform a test and output a test result; wherein the functional test items include synchronous functional tests or asynchronous functional tests.

[0012] A second aspect of the present invention provides a test control module, the test control module is integrated in the chip to be tested, and the test control module is provided with a JTAG interface, a bus slave interface, a general register, a counter and a configuration register;

[0013] The test control module is designed in two aspects: reset and clock:

[0014] In terms of reset, the reset signal of the test control module adopts a power-on reset signal; when the chip under test is in an external reset state, the automated test equipment sets the test_mode signal output by the test control module high through the JTAG interface, so that the internal reset circuit logic of the chip under test changes and can be directly driven and controlled by the external reset pin of the chip;

[0015] In terms of clock, when the chip under test is in an external reset state, the automated test equipment sets the test_mode signal output by the test control module high through the JTAG interface, so that the internal clock circuit logic of the chip under test changes and can be directly driven and controlled by the external clock through the external clock pin. At the same time, the external clock provided by the automated test equipment can be freely propagated in the clock circuit to start the bus clock of the test control module;

[0016] The test control module is used to implement the chip function testing method as described in the first aspect.

[0017] A third aspect of the present invention provides an automated testing device, the automated testing device comprising:

[0018] The first control module is used to control the chip under test to be in a power-on reset state and an external reset state at the initial stage of power-on;

[0019] A configuration module, used for performing test-related configuration on a test control module through a JTAG interface of the chip under test when the chip under test releases a power-on reset signal and ends the power-on reset state, and controlling the chip under test and the automated test equipment to establish a synchronization state; wherein the test control module is pre-integrated in the chip under test;

[0020] A second control module, configured to release the external reset signal of the chip under test and end the external reset state, so that the chip under test performs a functional test preparation operation;

[0021] The test module is used to control the chip to be tested to perform a test and output a test result according to the selected functional test items; wherein the functional test items include synchronous functional tests or asynchronous functional tests.

[0022] According to a fourth aspect of the present invention, an electronic device is provided, comprising a memory, a processor and a bus; the bus is used to realize connection and communication between the memory and the processor; the processor is used to execute a computer program stored in the memory; when the processor executes the computer program, the steps in the chip function testing method of the first aspect are realized.

[0023] The present invention provides a chip function test method, test control module, equipment and device, which control the chip to be tested to be in a power-on reset state and an external reset state at the start of power-on. When the chip to be tested releases a power-on reset signal and ends the power-on reset state, the test control module is configured for testing through the JTAG interface of the chip to be tested, and the chip to be tested and the automated test equipment are controlled to establish a synchronization state. When the external reset signal of the chip to be tested is released and the external reset state is ended, the chip to be tested performs a functional test preparation operation, and controls the chip to be tested to perform a test and output a test result according to the selected functional test items. Compared with the related art of using a system test board for testing, the technical scheme is based on adding a test control module in the chip design stage, so that the automated test equipment can directly provide the chip to be tested with an external reset and an external clock according to the automated test vector to establish a synchronization state between the two, so that the chip function test can meet the requirements of the automated test equipment synchronization test method, avoid introducing unexpected problems when using the system test board for testing, so that multiple functional tests can be quickly implemented on the automated test equipment, and the automation degree, test efficiency and test stability of the functional test are effectively improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0025] Figure 1 A schematic diagram of the structure of the automated testing equipment provided in the embodiment of the present application;

[0026] Figure 2 A schematic diagram of a flow chart of a chip function testing method provided in an embodiment of the present application;

[0027] Figure 3 A schematic diagram of clock, reset and test_mode signals in different stages of the chip function testing method provided in an embodiment of the present application;

[0028] Figure 4 This is a schematic diagram of the internal structure of the test control module of an embodiment of the present application;

[0029] Figure 5 A schematic diagram of the structure of an output circuit in a configuration register according to an embodiment of the present application;

[0030] Figure 6 A circuit connection diagram of the FLASH mode configuration register of an embodiment of the present application;

[0031] Figure 7 A schematic diagram of a flow chart of a chip function testing method provided in an embodiment of the present application;

[0032] Figure 8 A schematic diagram of a flow chart of a chip function testing method provided in an embodiment of the present application;

[0033] Fig. 9 A schematic diagram of the internal structure of a chip to be tested in the related art;

[0034] Fig.10 A waveform diagram of a clock reset signal in different stages of a chip under test during a chip function test in the related art;

[0035] Fig.11 A waveform diagram of a clock reset signal in different stages of a chip under test during a chip function test in the related art;

[0036] Fig.12 This is a schematic diagram of the internal structure of the chip to be tested in the embodiment of the present application;

[0037] Fig.13A schematic diagram of module connections in the automated testing equipment provided in an embodiment of the present application;

[0038] Fig.14 This is a schematic diagram of the internal structural connection of the electronic device provided in an embodiment of the present application.

[0039] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0040] It should be understood that the specific embodiments described herein are only used to explain the present invention, and are not used to limit the present invention.

[0041] It should be noted that related terms such as "first", "second", etc. can be used to describe various components, but these terms do not limit the components. These terms are only used to distinguish one component from another component. For example, without departing from the scope of the present invention, a first component can be referred to as a second component, and the second component can also be referred to as a first component similarly. The term "and / or" refers to any one or more combinations of related items and description items.

[0042] In the chip design and production process, in order to ensure product quality and eliminate chips with manufacturing defects, a testability design method is usually adopted. This testability design method improves the testability of the chip by inserting specific testability circuits in the chip design stage. In the chip production test stage, the chip can be tested using testability circuits, automated test equipment and automated test vectors to eliminate chips with manufacturing defects and ensure the chip's factory quality.

[0043] Among them, the testable design can be divided into two categories according to whether it is related to the chip's own functions, namely non-functional testable design and functional testable design. Non-functional testable design is a test on the chip circuit structure itself, which has nothing to do with the chip's own functions. Functional testing can detect whether there are functional faults in the chip during chip production testing, such as abnormal communication interface, abnormal low power mode, and abnormal digital-to-analog conversion results. Therefore, the combination of non-functional testing and functional testing can cover the testing of all chip faults and realize a complete production test process.

[0044] During the chip production test phase, automated test equipment and automated test vectors are usually used to complete non-functional testing, while functional testing relies on system test boards and test programs. However, compared with automated test equipment, system test boards have multiple disadvantages. Their design needs to be customized in combination with chip functions, and this customization process may introduce unexpected problems. In addition, the versatility and stability of system test boards are poor, making it difficult to adapt to the needs of AC parameter testing, DC parameter testing, and injection error testing.

[0045] Therefore, the chip function testing method in the related art has technical problems such as low testing efficiency and poor stability.

[0046] To solve the above technical problems, please refer to Figure 1 , this embodiment provides an automated testing system that can execute a chip function testing method.

[0047] The automated test system includes a computer, automated test equipment, a printed circuit board, a chip fixture and a test chip. Specifically, the automated test vector has the expected input and expected output of each clock cycle during the functional test of the chip to be tested. The automated test equipment adopts a synchronous test method, that is, the automated test equipment generates the expected input signal (such as clock, reset, data) of the chip to be tested cycle by cycle according to the automated test vector, and compares the expected output and actual output of the chip to be tested, and completes the above test process in a synchronous state. Among them, the printed circuit board connects the automated test equipment and the test circuit, the chip fixture is used to fix and facilitate the replacement of the chip to be tested, and the test chip can realize the test of the complex functions (such as USB functions) of the chip to be tested. In the functional test, the automated test equipment requires that the output of each clock cycle of the chip to be tested is consistent with the expected output through the synchronous test method, and the pass or fail of the test result determines the qualification of the chip to be tested. Among them, according to whether the chip to be tested and the automated test equipment are always in a synchronous state during the functional test, the test is divided into synchronous functional test and asynchronous functional test.

[0048] See also Figure 2 and Figure 3 The chip function testing method of the embodiment of the present application includes the following steps:

[0049] Step S201 , controlling the chip under test to be in a power-on reset state and an external reset state at the initial stage of power-on.

[0050] Specifically, when it is necessary to perform functional testing on the chip under test, the tester can connect the automated testing equipment to the chip under test through a printed circuit board and power on the chip under test, thereby triggering the generation of a power-on reset signal and causing the chip under test to enter a power-on reset state, to ensure that the circuit of the chip under test is in a certain state. At the same time, the control unit of the automated testing equipment generates an external reset signal and transmits it to the external reset pin of the chip under test. Since the two reset signals are generated independently, the chip under test can receive both a valid power-on reset signal and an external reset signal at the start of power-on, ensuring that the chip under test maintains consistency and synchronization in the two reset states. In other words, the automated testing equipment can control the chip under test to be in both a power-on reset state and an external reset state at the start of power-on, which is a Figure 3 The power-on reset phase in the test lays the foundation for subsequent test control module configuration and functional testing.

[0051] Step S202, when the chip under test releases the power-on reset signal and ends the power-on reset state, the test control module is configured for testing through the JTAG interface of the chip under test, and the chip under test and the automated test equipment are controlled to establish a synchronization state.

[0052] Specifically, the automated test equipment can monitor the power-on reset state of the chip under test in real time, and when the power-on reset signal is released, it is confirmed that the power-on reset state of the chip under test has ended. This stage ensures that the internal logic of the chip under test has been initialized, that is, all registers, counters, and state machines have been reset to the default state. Optionally, the automated test equipment can also wait for a sufficiently long time until the chip under test automatically releases the power-on reset signal and ends the power-on reset state.

[0053] At this time, the automated test equipment can configure the test control module inside the chip under test through the JTAG interface. Figure 3 In the test control module configuration phase. In this embodiment, the design based on the JTAG interface complies with the IEEE 1149.x standard, and the automated test equipment can establish a communication connection with the test control module through the JTAG interface standard operation method, and can initiate access operations to all register resources inside the test control module.

[0054] It should be noted that the test control module is a special function module pre-integrated inside the chip to be tested, and is usually embedded into the circuit structure of the chip based on a specific design during the design phase of the chip to be tested. Its main function is to provide control capabilities for the functional test and debugging process of the chip to be tested, with the purpose of establishing the synchronization state of the chip to be tested and the automated test equipment in the functional test of the chip to be tested, the transmission of test information (such as the selection of test items, the configuration of test parameters and the output of test results, etc.), and supporting tasks such as waiting time debugging in asynchronous functional testing. The test control module usually interacts with the automated test equipment through an external interface (such as a JTAG interface), accepts the control of the automated test equipment and performs corresponding operations. More specifically, by setting the test_mode signal output by the test control module high, the reset circuit logic and the clock circuit logic of the chip to be tested are controlled to change and can be directly driven and controlled by the automated test equipment to establish the synchronization state of the automated test equipment and the chip to be tested, and support the functional test of the chip to be tested, and can control the chip to be tested to enter different states to test and verify the target function. For example, by configuring different test parameters, functional testing and verification can be performed on the synchronous and asynchronous logic, clock domain interaction, data throughput, etc. of the chip under test.

[0055] Among them, a synchronization state between the chip under test and the automated test equipment is established, that is, the automated test equipment provides external reset, external clock and input to the chip under test according to the automated test vector, so that the chip under test, the automated test equipment and the automated test vector are completely kept in a synchronized state.

[0056] In addition, the reset signal of the test control module in the chip under test adopts a power-on reset signal (POR, Power on Reset), and other circuits of the chip under test, in addition to also requiring the use of a power-on reset signal, should be able to be controlled by an external reset pin and be in an external reset state.

[0057] Step S203, when the external reset signal of the chip under test is released and the external reset state ends, the chip under test performs a functional test preparation operation.

[0058] Specifically, when the external reset signal of the chip under test is released and the external reset state ends, the external reset state of the chip under test ends.

[0059] When the external reset state of the chip under test ends, the chip under test performs functional test preparation operations including startup, initialization and functional test item selection processes. Figure 3 The startup, initialization and functional test item selection phases are as follows:

[0060] First, the startup process: after the external reset is released, the internal system reset circuit of the chip under test first releases the reset of the startup module, and the startup module automatically starts to perform the following two tasks: 1. Load configuration data from FLASH to initialize some optional parameters of the chip, such as chip trim values ​​(such as on-chip clock source frequency trim), chip configuration options (such as on-chip LDO output voltage level, whether certain chip functions are enabled); 2. Load the test program from FLASH to the SRAM inside the chip under test. This is because the access speed of FLASH is lower than the access speed of the SRAM inside the chip under test. If the processor runs the test program directly from FLASH, its performance will be significantly reduced due to the FLASH access speed.

[0061] Secondly, the initialization process: After the startup module is completed, the internal system reset circuit of the chip under test releases the processor reset, and the processor automatically starts to execute the test program. The starting part of the test program includes the initialization work required for the program to run, such as initializing the starting address of the test program stack, initializing memory data, and initializing processor functions (such as enabling processor multi-level cache, enabling bit-band functions, etc.).

[0062] Finally, the functional test item selection process: when the test program is initialized, the functional test item selection can begin, such as reading the test information stored in the general register of the test control module, and performing the functional test item selection according to the test item selection information therein.

[0063] Step S204: According to the selected functional test items, the chip to be tested is controlled to perform the test and the test results are output.

[0064] Specifically, in Figure 3 During the functional test phase and the test result output phase, when the selected functional test item is a synchronous functional test, based on the pre-realized synchronization state between the chip to be tested and the automated test equipment, the chip to be tested is directly controlled to perform the corresponding functional test and output the test result. Also, when the selected functional test item is an asynchronous functional test, the chip to be tested and the automated test equipment are controlled and placed in an asynchronous state to control the chip to be tested to perform the corresponding functional test and output the test result. There are multiple ways to output the test result, for example: judging the test result by the high and low levels of the GPIO, and / or by writing the relevant test result to the general register in the test control module, and then the automated test equipment reads the test result through the JTAG interface.

[0065] Therefore, compared with the test method of the related art that uses a system test board (belonging to the peripheral test circuit) to perform functional testing, the test method of the embodiment of the present application is based on adding a test control module (belonging to the testability design inside the chip) in the chip design stage. During the test process, the JTAG interface of the chip to be tested can directly establish the synchronization state of the chip to be tested and the automated test equipment, so that the functional test of the chip to be tested can meet the requirements of the automated test equipment synchronization test method, and combined with the automated test advantages of the automated test equipment itself, such as good versatility, high maturity and good reliability, it can measure the AC parameters and DC parameters of the chip to be tested and is easy to perform injection error testing, etc., based on avoiding the unexpected problems that may be introduced by the peripheral test circuit, thereby quickly realizing multiple functional tests on the automated test equipment, effectively improving the degree of automation of functional testing, test efficiency and test stability. In addition, asynchronous functional testing can also be performed according to actual test needs.

[0066] In an optional implementation manner of the present embodiment, before controlling the chip to be tested to be in a power-on reset state and an external reset state at the initial stage of power-on, it also includes: powering on the chip to be tested to put the chip to be tested in a power-on reset state, when the chip to be tested releases a power-on reset signal and ends the power-on reset state, initializing the JTAG interface of the chip to be tested, accessing the FLASH mode configuration register of the test control module through the JTAG interface, and controlling the FLASH mode configuration register to output a flash_mode signal in a high state, and when the FLASH module of the chip to be tested is in a burning mode, burning the test program into the FLASH module via the FLASH interface of the chip to be tested.

[0067] Specifically, before performing a functional test, the automated test equipment accesses the FLASH mode configuration register of the test control module in the chip to be tested through the JTAG interface. During this process, the automated test equipment writes to the FLASH mode configuration register to set its output flash_mode signal high, thereby configuring the FLASH module to enter the burning mode. In the burning mode, the FLASH module is ready to receive test program data and can write data to the internal storage unit to prepare the required test program data in advance for subsequent functional tests. Among them, "high" or "high state" usually means that the signal logic value is "1", that is, when the signal logic value is a preset high value, the flash_mode signal is in a high state, which means that the FLASH module is in the burning mode.

[0068] In an optional implementation manner of the present embodiment, the test control module is configured for test-related operations through the JTAG interface of the chip to be tested, specifically including: initializing the JTAG interface of the chip to be tested, accessing the test_mode test data register of the test control module, writing the setting value of the test mode to the test_mode test data register, controlling the test_mode test data register to output a test_mode signal in a high state by configuring the setting value, and performing the initialization configuration required for testing the general registers and configuration registers inside the test control module.

[0069] Specifically, after the power-on reset of the chip to be tested is completed, its JTAG interface is first initialized by the automated test equipment. That is, after the power-on reset of the chip to be tested is completed, its JTAG interface is initialized by the automated test equipment. The initialization includes the synchronization of the clock signal (such as TCK), the data input signal (TDI) and the output signal (TDO), and the reading of the JTAG interface IDCODE, ensuring that the interface is in a communicative state, so that the automated test equipment establishes communication with the chip to be tested through the JTAG interface, ensuring that subsequent register accesses can be correctly transmitted to the test control module inside the chip.

[0070] The test_mode test data register is configured with a set value to set the test_mode signal high, which controls the internal reset circuit logic and clock circuit logic of the chip under test to change and can be directly driven and controlled by external reset and external clock. The automated test equipment provides external reset, external clock and input to the chip under test according to the automated test vector, so that the chip under test, the automated test equipment and the automated test vector are completely synchronized.

[0071] Among them, the general registers and configuration registers inside the test control module are initialized. For example, the first register in the general register is initialized to 10, and the test program selects the 10th functional test item as the functional test for this time after reading. The configuration register can control the state of the chip under test to test the functional test item, for example, the low-dropout regulator (LDO) inside the chip under test can be configured to output in low-voltage mode for functional testing.

[0072] In an optional implementation of this embodiment, the chip under test performs a functional test preparation operation, specifically including: initialization configuration of chip option parameters and test program loading of the chip under test, as well as functional test preparation operations of test program initialization and functional test item selection process. Among them, the general registers in the test control module provide test information for the test program of the chip under test, including test information such as test item selection, test parameter configuration, test result output, timing setting, and interface multiplexing setting.

[0073] In an optional implementation manner of the present embodiment, according to the selected functional test items, the chip to be tested is controlled to be tested and the test results are output, specifically including: when the selected functional test item is a synchronous functional test, while the chip to be tested and the automated test equipment are in a synchronized state, the chip to be tested is controlled to be tested according to the automated test vector, and a test result including a comparative analysis between the expected output value of the automated test vector and the actual output value of the chip to be tested is output; when the selected functional test item is an asynchronous functional test, while the chip to be tested and the automated test equipment are in an asynchronous state, the chip to be tested is controlled to be tested according to the automated test vector, and a test result including a comparative analysis between the expected output value of the automated test vector and the actual output value of the chip to be tested and the waiting time required from the starting point of the asynchronous test to the output of the test result is output.

[0074] Specifically, this embodiment flexibly adapts to the testing requirements in different scenarios by supporting synchronous functional testing and asynchronous functional testing. In synchronous functional testing, the chip to be tested and the automated testing equipment are kept in a synchronized state, and the expected output value of the automated test vector is accurately compared with the actual output value of the chip, thereby ensuring the high accuracy and stability of the test results. In asynchronous functional testing, by analyzing the test results in an asynchronous state, the waiting time information from the start of the asynchronous test to the output of the test results is further provided, thereby reducing the debugging time required to determine the waiting time for the test result output in the asynchronous functional test, and improving the development efficiency of the asynchronous functional test. The automated generation of test results significantly improves the test efficiency and reduces the possibility of human intervention. At the same time, the rich comparative analysis and delay data provide a detailed reference for performance optimization, design improvement, and troubleshooting of potential problems, thereby improving the reliability and comprehensiveness of the overall testing work.

[0075] See also Figure 4 The test control module of the embodiment of the present application is pre-integrated in the chip to be tested. The test control module is provided with 2 access interfaces, 2 clock domains, 3 types of registers and related configuration signals.

[0076] In the test control module, the two access interfaces include the JTAG interface and the bus slave interface. The functional description of the JTAG interface is as follows: The JTAG interface provides the ability to access the internal registers of the test control module from the outside. Its design complies with the IEEE 1149.x standard and adopts a 5-wire interface. The interface signals specifically include: TMS (Test Mode Select) is the test mode selection input, which controls the state machine in the test access interface controller (TAP Controller, Test Access Port Controller); TCK (Test Clock) is the test clock input; TDI (Test Data Input) is the test data input; TDO (Test Data Output) is the test data output; TRST (Test Reset) is the test reset input. The JTAG interface can be interconnected with other JTAG interfaces in the chip (typically the JTAG interface of the processor) in the form of a daisy chain, and a single standard JTAG interface can be led out to the outside of the chip without adding additional pins. And, the functional description of the bus slave interface is as follows: it provides the processor with the ability to access the internal registers of the test control module, and its design complies with the AMBA bus standards, such as AXI, AHB and APB standard slave interfaces, which are easy to integrate into the internal bus of the chip.

[0077] In the test control module, the two clock domains include the TCK clock domain and the bus clock domain. In the TCK clock domain, the clock driving source of the circuit is the TCK clock input by the JTAG interface. The modules included in the clock domain include the JTAG module and the interface module. The module functions are described as follows: the JTAG module implements the test access interface controller (TAPController), instruction register (IR, Instruction Register), BYPASS and IDCODE test data register (TDR, Test Data Register) of the IEEE 1149.x standard. In addition, the test control module also includes an interface module, which transfers the access operation of the test control module register through the JTAG interface in the TCK clock domain to the bus clock domain across clock domains, and generates the control signal required for the test control module register access.

[0078] Among them, in order to realize the steps of testing related configuration of the test control module through the JTAG interface, controlling the test_mode test data register to output a test_mode signal in a high state through the configuration set value, the configuration of the instruction register and the test_mode test data register in the test control module is shown in Table 1 below.

[0079] In order to access all registers in the test control module through the JTAG interface, such as general registers, counters and configuration registers, the configuration of the instruction register in the test control module and the test control module accessing the test data register are shown in Table 2 below.

[0080] Table 1

[0081]

[0082]

[0083] In the above Table 1, the test_mode test data register (TDR) is selected by configuring the setting value of the instruction register (IR) of the test access interface controller (TAP Controller) in the JTAG module. When the test_mode test data register receives the preset setting value (32'hxxxxxxxx), the test_mode signal output by the JTAG module is set high.

[0084] Table 2

[0085]

[0086]

[0087] In the above Table 2, the test control module is selected to access the test data register (TDR) by configuring the setting value of the instruction register (IR) of the test access interface controller (TAP Controller) in the JTAG module. The test data register controls the read and write operations through the WRn bit (1'b0 for reading, 1'b1 for writing), uses ADDR[7:0] to specify the register address, BWE[3:0] to set the byte write enable, and DATA[31:0] to write or return data. In addition, the status bit is used to indicate whether the previous register access operation is completed (1'b0 for completion, 1'b1 for incomplete), so as to realize efficient read and write operation management of the register.

[0088] In the bus clock domain in the test control module, the clock drive of its internal circuit is derived from the bus clock. The clock domain includes modules such as the bus interface module, the access arbitration module and the register. The functions of the bus interface module, the access arbitration module and the register are described as follows: the bus interface module generates the control signal required for the internal register access of the test control module according to the bus access; when the register access from JTAG and the register access from the bus occur at the same time, the access arbitration module needs to arbitrate the access conflict, and a priority arbitration method is adopted, in which the register access from JTAG always has a higher priority than the register access from the bus; the registers are divided into three categories, namely general registers, counters and configuration registers.

[0089] The functions of the three types of registers in the test control module are described as follows:

[0090] Specifically, the general register contains 8 32-bit readable and writable registers, through which the automated test equipment and the test program can transfer test information, such as the selection of test items, the configuration of test parameters, and the output of test results, etc. The specific definition of each general register can be flexibly defined according to the functional test requirements.

[0091] Specifically, the counter includes a 48-bit increment counter and related control registers. When synchronous functional testing cannot be used in some chip functional tests and asynchronous functional testing must be used, the counter is used to calculate the waiting time required between the start of the asynchronous test and the output of the test result, which is convenient for debugging the time point when the automated test equipment queries the asynchronous test result. In addition, designing an independent counter in the test control module instead of using the counter that may already exist in the chip has the following advantages: the counter bit width can be freely selected. The bit width of the existing counter of the chip may be constrained by the design indicators and is usually 32 bits or less. If the asynchronous functional test time is too long, it is very likely to cause the counter to overflow. The counter of the test control module has a bit width of 48 bits, which can effectively avoid the counter overflow problem. In addition, the counting clock of the counter can be freely selected. The existing counter of the chip is limited by the system design. When performing asynchronous functional testing, its counting clock may not be provided by the automated test equipment, while the counter of the test control module has no such limitation and can be directly provided by the automated test equipment. Therefore, the actual count value of its counter can be conveniently and directly converted into the number of waiting cycles in the automated test vector.

[0092] Specifically, the configuration register includes the trim value register and the chip function configuration register, such as the on-chip clock source frequency trim register, the on-chip bandgap reference trim register, the low power mode configuration register, and the startup mode configuration register. Some configuration registers have the following connections to the output configuration signal: Figure 5 The output circuit structure is shown.

[0093] Among them, the configuration register is usually initialized with FLASH data or the pin value of the chip during the chip startup phase to put the chip in the desired working state. The register value is used as the output value of the configuration signal by default. By adding the configuration copy register and the configuration selection register, it is convenient for the subsequent configuration value testing.

[0094] For example, in the trimming value test of the chip to be tested, the simplest method is to test each trimming value of the chip to be tested. Through the above-mentioned output circuit, the trimming value traversal test can be quickly performed to obtain the best trimming value without frequently changing the trimming value in the FLASH module, and all the best trimming values ​​can be written into the FLASH module at one time after all the trimming values ​​are tested. In the startup mode test of the chip to be tested, the circuit design of the system test board can also be simplified through the above-mentioned output circuit structure, that is, simply connecting the startup mode configuration pin of the chip to be tested to the switch, and the test control chip on the system test board can change the configuration value of the startup mode inside the chip to be tested online through the JTAG interface, which helps the system test to realize automated testing of multiple startup modes.

[0095] In an optional implementation of this embodiment, the configuration register includes a special configuration register, namely, a FLASH mode configuration register, which outputs a configuration signal flash_mode, through which the FLASH pin inside the chip can be multiplexed to the outside of the chip.

[0096] See also Figure 6 , the FLASH mode configuration register realizes flexible switching of FLASH operation mode through the connection of GPIO, FLASH control module, multiplexer (MUX) and on-chip FLASH memory. When the flash_mode signal is at the default low level, FLASH is in normal mode, and the FLASH control module is responsible for initializing the reading of configuration data and the loading of test programs, as well as the read and write access of other data; when the flash_mode signal is set high, FLASH is in burning mode, and the FLASH pin switches the control path to the external pin through the multiplexer, and the automated test equipment directly controls the FLASH to realize operations such as erasing, burning and reading. This design simplifies the FLASH mode switching process, while ensuring the flexibility and safety of normal operation and testing of the chip.

[0097] See also Figure 7 In an optional implementation manner of this embodiment, the chip function testing method includes three testing program stages.

[0098] In the first test program stage, external reset release is used as the starting point for the chip to be tested and the automated test equipment in a synchronous state in this stage, and it always runs in a synchronous state in this stage. When the chip to be tested is started, the common part of the code in the test program starts to run. The code in this stage is mainly the startup code, initialization code and functional test item selection code, and the selected test information comes from the general register in the test control module. In addition, the code in this stage should be prohibited from being modified in the entire test program development after the first functional test item is developed and debugged by the automated test equipment. The reason is that the code modification in this stage will affect the execution process of all functional test items. The test program is usually developed in an incremental form. When the code of functional test item 1 is developed and debugged by the automated test equipment, if the code of this stage is modified due to the requirements of functional test item 2, the modification will also affect the developed automated test item 1, which will cause the functional test item 1 to fail to pass the test again on the automated test equipment, and thus need to be debugged again. Therefore, only the code necessary for the function implementation should be retained in this stage.

[0099] In the second test program phase, this phase is the chip function test phase. Typically, chip function test items can be divided into multiple function test items according to various function modules in the chip, and the same function module corresponds to one function test item; some function test items can be further divided into multiple sub-test items according to test needs, such as sub-test items can be tests of each function module or different sub-functions of a function module, and the same function module under different parameter configurations. The selection information and parameter configuration information of the sub-test items can all be derived from the general registers in the test control module. In addition, some function test items may need to be divided into multiple sub-test stages. For example, in the traversal test of the adjustment value of the chip to be tested, in order to find the best adjustment value, each test stage can correspond to a test of the adjustment value; the difference between sub-test items and sub-test stages is that during the test process, the sub-test items output the test results once after the test is completed, while each sub-test stage needs to output the test results. Therefore, if the length of the sub-test stage is 1, the sub-test items and sub-test stages are actually equivalent.

[0100] During the functional test process, the chip under test and the automated test equipment can be divided into synchronous functional testing and asynchronous functional testing according to whether they are always synchronized. They are described as follows:

[0101] In synchronous functional testing, the chip under test and the automated test equipment always maintain a synchronized state. This is because the reset and clock required for the functional test are all directly provided by the automated test equipment, and the input of the chip under test is controlled by the automated test vector and kept in a synchronized state. Therefore, during the test, the output of the chip under test and the expected value of the automated test vector can be synchronized and aligned at each clock cycle. The test process is usually that the automated test equipment provides input to the chip under test based on the automated test vector, and at the same time compares the expected output value of the automated test vector with the actual output value of the chip under test, and determines whether the functional test passes based on the comparison result. Among them, the test is performed at each clock cycle level.

[0102] In asynchronous functional testing, the chip to be tested and the automated testing equipment cannot always maintain synchronization. This is usually because the clocks required for functional testing are not all directly provided by the automated testing equipment. For example, the internal PLL is used for clock multiplication during the functional testing of processor performance types, and the physical layer provides an independent clock source to the controller during the USB test. Therefore, during the functional testing process, the output of the chip to be tested and the automated test vector cannot be synchronized and aligned on each clock. The asynchronous functional testing process is usually that the automated testing equipment provides the required input to the chip to be tested based on the automated test vector. After the chip to be tested completes the functional test itself (commonly used for the function and / or performance test of the chip's internal module) or completes the test with the chip to be tested (commonly used for the function and / or performance test of the chip's complex interface module), the test results are output to the automated testing equipment. Optionally, when synchronous testing cannot be used in the functional testing of some chips and asynchronous functional testing must be used, the counter inside the test control module is used to facilitate the calculation of the waiting time required between the start of the asynchronous test and the output of the test results, so as to facilitate the debugging of the time point when the automated testing equipment queries the test results.

[0103] In the third test program stage, this stage is for the automated test equipment to collect the functional test result information of the chip to be tested. The collection of synchronous functional test results is convenient, because the automated test equipment will compare the expected output of the automated test vector and the actual output of the chip to be tested cycle by cycle during the test process, and automatically record the comparison results. Whether the comparison results are all consistent can be directly recorded in the test diary as the functional test results of this time. At the same time, the test program can also write the test result information into the general register inside the test control module. For example, in the adjustment value traversal test, the best adjustment value needs to be written into the general register, and then the general register data is read out by the automated test equipment through the JTAG interface and recorded in the test diary, which is convenient for later statistical analysis.

[0104] Among them, the collection of asynchronous function test results is more troublesome. In some asynchronous function tests, the test program can output the test results first and then output the test completion mark through GPIO after the test is completed. The automated test equipment can detect the test completion mark through a loop and collect the test results after detecting the test completion mark. The above method cannot be used in some asynchronous functional tests because the loop query requires the automated test equipment to judge and jump the output completion flag. When performing such operations, the automated test equipment needs to spend extra time to process. When executing the judgment and jump, the speed at which the automated test equipment executes the automated test vector may change, which further causes the external clock cycle provided by the automated test equipment to the chip under test to change. If the asynchronous functional test involves the use of the chip's internal PLL and its reference clock source is an external clock provided by the automated test equipment, it is very likely to cause the PLL to lose lock, thereby causing the asynchronous functional test to fail. Therefore, in this type of asynchronous functional test, the method of loop querying the test completion flag cannot be used, and only the delayed waiting method can be used. That is, in actual testing, by utilizing the test control module counter function, the waiting time can be quickly adjusted so that the automated test equipment can correctly detect the test completion flag and read the output of the chip asynchronous test results. The waiting time test method is as follows: Figure 8 shown.

[0105] Among them, the test program uses startup code, initialization code, test function selection code and code library as common code, and divides functional test items into functional modules, and can be further divided into sub-test items or sub-test stages according to test requirements. At the same time, the common code should not be modified after the first functional test item is developed and debugged on the automated test equipment. The test program structure is conducive to collaborative development by multiple people, and each test item remains relatively independent during the development process, which is conducive to multiple people independently developing or integrating existing functional test items. In the process of developing functional test items, the function calls between modules in the chip to be tested can be realized through a common code library, so as to reduce the amount of code and time for test program development, and effectively improve the efficiency of test program development.

[0106] In an optional implementation of this embodiment, after controlling the chip to be tested to be tested according to the automated test vector, it also includes: at the start of the asynchronous functional test, the count value of the counter in the control test control module is initialized to 0 and the counter is activated to start counting, when the test result of the asynchronous functional test is output, the counter is controlled to stop counting and the actual calculated value of the counter is stored in the FLASH module, the actual count value in the FLASH module is read, and the actual count value is calculated to obtain the final count value, and the final count value is used as the waiting time required from the start of the asynchronous test to the output of the test result. The final count value is the actual count value multiplied by the counting clock cycle.

[0107] Specifically, this implementation method uses a counter to accurately record the actual waiting time required from the start of the asynchronous test to the output of the test result. The actual count value is stored in the FLASH module, so that the automated test equipment can read the actual count value in the FLASH after setting flash_mode high, and record it in the test log together with the final count value, which is convenient for subsequent statistical analysis. At the same time, after the asynchronous function test is completed, the automated test equipment can directly read these actual count values ​​from the FLASH by setting flash_mode high. Through the actual count value and the counting clock frequency, the waiting time (final count value) required between the start of the asynchronous test and the output of the test result can be easily obtained. According to this waiting time, the number of waiting cycles in the automated test item vector used in the asynchronous function test item needs to be adjusted.

[0108] In an optional implementation manner of this embodiment, after controlling the chip to be tested to perform a test and outputting a test result, the method further includes:

[0109] Detect whether the chip under test passes the test of the currently selected functional test item according to the test results;

[0110] If the selected chip to be tested fails the test of the currently selected functional test item, a test result indicating that the chip to be tested has failed is output;

[0111] If the chip under test passes the test of the currently selected functional test item, check whether all functional test items have completed the test;

[0112] If all functional test items have been completed and passed, the test result indicating that the chip under test has passed the test is output;

[0113] If there are unfinished functional test items, return and execute the step of controlling the chip under test to be in a power-on reset state and an external reset state at the initial stage of power-on to perform the test of the next functional test item.

[0114] Specifically, the operation flow in this embodiment realizes the accurate determination of the functionality and qualified status of the chip to be tested, and designs a reasonable test flow backtracking mechanism to ensure that all test items are covered and the output of the test results is clear and intuitive. This design is particularly suitable for chip production testing and verification testing of chip design optimization.

[0115] In order to further explain the technical problems and related principles that can be solved by the chip function testing method provided in the embodiment of the present invention, the differences between the chip of the related art and the chip to be tested in the embodiment of the present application are described as follows:

[0116] See also Fig. 9In the related art shown in , when the original design of the reset and clock aspects of the chip under test does not meet the requirements of the above-mentioned automatic test equipment synchronization test method, the test_mode signal needs to be matched with an additional circuit to meet the above-mentioned two requirements. The specific description is as follows:

[0117] Reset: The reason why the synchronous test requirements of the automated test equipment cannot be met is that the system reset cannot be completely driven and controlled directly by the automated test equipment.

[0118] Because it contains a reset extension module, when it detects that the external reset is effective and continues to extend the system reset validity time after the external reset is released. The chip under test may be designed like this for many reasons. For example, no matter how long the external reset signal is effective, the system reset validity time after the reset extension process is not less than 20ms. This design ensures that all circuits of the chip under test can be reset correctly. However, the reset extension module is usually implemented using a counter for reset delay, and its counting clock uses an internal clock source. This clock source and the automated test equipment are in an asynchronous state, which will cause the following problems (see Fig.10 ):

[0119] Without loss of generality, after the external reset is released at time T1, the system reset will theoretically be released at time T2 after a delay of 3 cycles. However, due to the inevitable deviation between the external clock and the internal clock, the system reset may not be released until time T3. This misalignment will affect all subsequent test phases. For example, the automated test equipment knows that a GPIO of the chip under test should output a high level at time T4 based on the automated test vector. However, due to the delay in the release of the system reset, the GPIO actually outputs a high level at time T5. The automated test equipment detects that the GPIO does not output a high level at time T4, which will lead to the failure of this functional test.

[0120] Clock aspect: The reason why the synchronization test requirements of the automated test equipment cannot be met is that the system clock is not directly driven and controlled by the automated test equipment.

[0121] Since the system clock uses the internal clock by default, the possible reason for this design is that the chip under test is mainly aimed at the cost-sensitive and / or miniaturized market. In some user application scenarios, it may only need to use the internal clock as the system clock to meet its application needs without using an external clock. This reduces the area of ​​the circuit board and the number of circuit components, but it cannot meet the requirements of synchronous testing of automated test equipment, such as Fig.11 As shown:

[0122] After the system reset is released, the processor starts to execute the test program. In the initialization phase of the test program, the system clock can be switched to an external clock to establish a synchronous state between the automated test equipment and the chip under test. However, between the time when the system reset is released (T2) and the time when the system clock is switched to an external clock (T3), the system clock is an internal clock. Similarly, the deviation between the external clock and the internal clock may eventually cause a GPIO of the chip under test to output a high level at T4, but the GPIO actually outputs a high level at T5. The automated test equipment detects that the GPIO does not output a high level at T4, which will cause the failure of this functional test.

[0123] In summary, it can be seen that the chip under test in the related art cannot meet the requirements in terms of reset and clock, and therefore cannot meet the requirements of the synchronous test method of the automated equipment.

[0124] See also Fig.12 In the embodiment of the present application, the original reset and clock circuit structure of the chip under test are modified by using the test_mode signal to meet the following design goals:

[0125] Reset: When the chip under test is in the external reset state, the test_mode signal is set high through the JTAG interface, so that the internal reset circuit logic of the chip under test can be changed and directly driven and controlled by the external reset through the chip's external reset pin.

[0126] Clock aspect: When the chip under test is in the external reset state, the test_mode signal is set high through the JTAG interface, so that the internal clock circuit logic of the chip under test can be changed and directly driven by the external clock through the chip's external clock pin, and the external clock can propagate freely in the clock circuit, and then the bus clock of the test control module will also be in the on state.

[0127] Here you can combine Figure 3 In the test control module configuration phase, after the test_mode signal is set high through the JTAG interface, the system reset and system clock will switch to external reset and external clock, and they will be completely synchronized. Furthermore, the external clock, external reset and input are directly provided by the automated test equipment according to the automated test vector, so the entire chip under test will be completely synchronized with the automated test equipment and the automated test vector.

[0128] Therefore, the test control module is designed to enable the functional circuit to meet the requirements of the synchronous test method of the automated test equipment during the chip design phase (using the test_mode signal), which can effectively solve the problem that the original reset and clock circuits cannot meet the requirements of the synchronous test method of the automated test equipment.

[0129] Fig.13An automated testing device provided by an embodiment of the present invention is shown, and the automated testing device includes:

[0130] The first control module 1301 is used to control the chip under test to be in a power-on reset state and an external reset state at the initial stage of power-on;

[0131] Configuration module 1302, used for performing test-related configuration on the test control module through the JTAG interface of the chip under test when the chip under test releases the power-on reset signal and ends the power-on reset state, and controlling the chip under test and the automated test equipment to establish a synchronization state; wherein the test control module is pre-integrated in the chip under test;

[0132] The second control module 1303 is used for releasing the external reset signal of the chip under test and ending the external reset state, so that the chip under test performs a functional test preparation operation;

[0133] The testing module 1304 is used to control the chip to be tested to perform a test and output a test result according to the selected functional test items; wherein the functional test items include synchronous functional tests or asynchronous functional tests.

[0134] The automated test equipment of this embodiment is based on adding a test control module (belonging to the testability design inside the chip) in the chip design stage. The automated test equipment can directly provide the external reset and external clock to the chip to be tested according to the automated test vector to establish the synchronization state between the two, so that the chip functional test can meet the requirements of the automated test equipment synchronization test method, and combined with the automated test advantages of the automated test equipment itself, such as good versatility, high maturity and good reliability, it can measure the AC parameters and DC parameters of the chip to be tested and easily perform injection error testing, etc., so as to quickly implement multiple functional tests on the automated test equipment, effectively improve the automation degree of functional testing, test efficiency and stability. In addition, asynchronous functional testing can also be performed according to actual test needs.

[0135] Fig.14 An electronic device provided by an embodiment of the present invention is shown, and the electronic device can be used to implement the chip function testing method in any of the above embodiments. The electronic device includes:

[0136] Memory 1401, processor 1402, bus 1403, and a computer program stored in memory 1401 and executable on processor 1402, memory 1401 and processor 1402 are connected via bus 1403. When processor 1402 executes the computer program, the chip function test method in the aforementioned embodiment is implemented. The number of processors may be one or more.

[0137] The memory 1401 may be a high-speed random access memory or a non-volatile memory, such as a disk memory. The memory 1401 is used to store executable program codes, and the processor 1402 is coupled to the memory 1401 .

[0138] Furthermore, an embodiment of the present application also provides a computer-readable storage medium, which may be disposed in the electronic device in each of the above embodiments, and the computer-readable storage medium may be a memory.

[0139] The computer readable storage medium stores a computer program, and when the program is executed by the processor, the chip function test method in the aforementioned embodiment is implemented. Furthermore, the computer storable medium can also be a U disk, a mobile hard disk, a read-only memory (ROM), a RAM, a magnetic disk or an optical disk, and other media that can store program codes.

[0140] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of modules is only a logical function division. There may be other division methods in actual implementation, such as multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or modules, which can be electrical, mechanical or other forms.

[0141] Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution in this embodiment.

[0142] In addition, each functional module in each embodiment of the present application may be integrated into one processing module, or each module may exist physically separately, or two or more modules may be integrated into one module.

[0143] It should be noted that, for the above-mentioned method embodiments, for the sake of simplicity of description, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the present application is not limited by the described action sequence, because according to the present application, certain steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present application.

[0144] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0145] The above are only preferred embodiments of the present invention, and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A chip function testing method, characterized in that: Applied to automated testing equipment, the chip function testing method includes: Control the chip under test to be in power-on reset state and external reset state at the initial stage of power-on; When the chip under test releases the power-on reset signal and ends the power-on reset state, the test control module is configured for testing through the JTAG interface of the chip under test, and the chip under test and the automated test equipment are controlled to establish a synchronization state; wherein the test control module is pre-integrated in the chip under test; When the external reset signal of the chip under test is released and the external reset state ends, the chip under test performs a functional test preparation operation; According to the selected functional test items, the chip under test is controlled to perform a test and output a test result; wherein the functional test items include synchronous functional tests or asynchronous functional tests.

2. The chip function testing method according to claim 1, characterized in that: Before controlling the chip under test to be in a power-on reset state and an external reset state at the initial stage of power-on, the method further includes: Powering on the chip to be tested to put the chip to be tested in a power-on reset state; When the chip under test releases a power-on reset signal and ends the power-on reset state, the JTAG interface of the chip under test is initialized, the FLASH mode configuration register of the test control module is accessed through the JTAG interface, and the FLASH mode configuration register is controlled to output a flash_mode signal in a high state; When the FLASH module of the chip to be tested is in a burning mode, the test program is burned into the FLASH module via the FLASH interface of the chip to be tested.

3. The chip function testing method according to claim 1, characterized in that: The step of performing test-related configuration on the test control module through the JTAG interface of the chip to be tested, and controlling the chip to be tested and the automated test equipment to establish a synchronization state, specifically includes: Initialize the JTAG interface of the chip to be tested and access the test_mode test data register of the test control module; The test mode setting value is written into the test_mode test data register, and the test_mode test data register is controlled to output a test_mode signal in a high state by writing the setting value, so that the reset circuit logic and clock circuit logic of the chip under test are changed and can be directly driven and controlled by an external reset and an external clock. The automated test equipment provides an external clock and an external reset according to the automated test vector, so that the chip under test, the automated test equipment and the automated test vector maintain a synchronous state. The general registers and configuration registers inside the test control module are initialized and configured as required for the test.

4. The chip function testing method according to claim 1, characterized in that: The chip to be tested performs a functional test preparation operation, specifically including: The chip to be tested performs a functional test preparation operation; wherein, the functional test preparation operation includes starting chip option parameter initialization configuration and test program loading, as well as test program initialization and functional test item selection.

5. The chip function testing method according to claim 1, characterized in that: According to the selected functional test items, controlling the chip to be tested to perform the test and outputting the test results specifically includes: When the selected functional test item is a synchronous functional test, the chip under test is controlled to be tested according to the automated test vector while the chip under test and the automated test equipment are kept in a synchronized state, and a test result including a comparative analysis between an expected output value of the automated test vector and an actual output value of the chip under test is output; When the selected functional test item is an asynchronous functional test, when the chip to be tested and the automated testing equipment are in an asynchronous state, the chip to be tested is controlled to be tested according to an automated test vector, and a test result is output including a comparative analysis between the expected output value of the automated test vector and the actual output value of the chip to be tested and the waiting time required from the start of the asynchronous test to the output of the test result.

6. The chip function testing method as claimed in claim 5, characterized in that: After controlling the chip to be tested to be tested according to the automated test vector, the method further includes: At the start point of the asynchronous functional test, controlling the count value of the counter in the test control module to be initialized to 0 and activating the counter to start counting; When the test result of the asynchronous functional test is output, the counter is controlled to stop counting and the obtained actual count value is stored in the FLASH module; The actual count value in the FLASH module is read, and the actual count value is calculated to obtain a final count value, and the final count value is used as the waiting time required from the start point of the asynchronous test to the output of the test result.

7. The chip function testing method according to claim 1, characterized in that: After controlling the chip to be tested to perform a test and outputting a test result, the method further includes: Detecting whether the chip under test passes the test of the currently selected functional test item according to the test result; If the selected chip to be tested fails the test of the currently selected functional test item, outputting a test result indicating that the chip to be tested fails the test; If the chip under test passes the test of the currently selected functional test item, detecting whether all functional test items have completed the test; If all functional test items have been completed and passed, the test result indicating that the chip under test has passed the test is output; If there are unfinished functional test items, return to and execute the step of controlling the chip to be tested to be in a power-on reset state and an external reset state at the initial stage of power-on to perform the test of the next functional test item.

8. A test control module, characterized in that: The test control module is integrated in the chip to be tested, and the test control module is provided with a JTAG interface, a bus slave interface, a general register, a counter and a configuration register; The test control module is designed in two aspects: reset and clock: In terms of reset, the reset signal of the test control module adopts a power-on reset signal; when the chip under test is in an external reset state, the automated test equipment sets the test_mode signal output by the test control module high through the JTAG interface, so that the internal reset circuit logic of the chip under test changes and can be directly driven and controlled by the external reset pin of the chip; In terms of clock, when the chip under test is in an external reset state, the automated test equipment sets the test_mode signal output by the test control module high through the JTAG interface, so that the internal clock circuit logic of the chip under test changes and can be directly driven and controlled by the external clock through the external clock pin. At the same time, the external clock provided by the automated test equipment can be freely propagated in the clock circuit to start the bus clock of the test control module; The test control module is used to implement a chip function test method according to any one of claims 1 to 7.

9. An automated testing device, characterized in that: The automated testing equipment comprises: The first control module is used to control the chip under test to be in a power-on reset state and an external reset state at the initial stage of power-on; A configuration module, used for performing test-related configuration on a test control module through a JTAG interface of the chip under test when the chip under test releases a power-on reset signal and ends the power-on reset state, and controlling the chip under test and an automated test device to establish a synchronization state; wherein the test control module is pre-integrated in the chip under test; A second control module, configured to release the external reset signal of the chip under test and end the external reset state, so that the chip under test performs a functional test preparation operation; The test module is used to control the chip to be tested to perform a test and output a test result according to the selected functional test items; wherein the functional test items include synchronous functional tests or asynchronous functional tests.

10. An electronic device, characterized in that: Includes memory, processor and bus; The bus is used to realize the connection and communication between the memory and the processor; The processor is used to execute the computer program stored in the memory; When the processor executes the computer program, the steps in the chip function testing method described in any one of claims 1 to 7 are implemented.

Images