Chip testing method and device, storage medium and electronic equipment

Abstract

The invention discloses a chip testing method and device, a storage medium and electronic equipment, and the method comprises the steps: determining the number of signal channels of a to-be-tested chip and a testing demand; determining a target channel configuration mode from preset channel configuration modes according to the number of signal channels and test requirements; test channels are configured for the chip according to the target channel configuration mode, each test channel corresponds to one signal channel group, and each signal channel group comprises at least two signal channels; selecting a target channel currently corresponding to each test channel from the corresponding signal channel group by using a multiplexing module; and testing the target channels, and returning to execute the step of selecting the target channel currently corresponding to each test channel from the corresponding signal channel group by using the multiplexing module until all signal channels are tested. According to the scheme, the testing cost of chip testing can be reduced.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of chip technology, and specifically to a chip testing method, device, storage medium and electronic device. Background Art

[0002] In the field of chip design and manufacturing, chip function and performance testing is a key link to ensure its quality and reliability. With the rapid development of chip technology, the number and complexity of signal channels integrated inside the chip have increased significantly, which has put forward higher requirements for chip testing methods.

[0003] At present, chip testing usually adopts the full-channel testing method, that is, the test equipment is directly connected to all the signal channels of the chip for testing. However, with the widespread application of high-complexity chips such as multi-core processors, SoC (system-on-chip) and AI acceleration chips, the number of signal channels and functional modules of modern chips continues to increase. Full-channel testing requires the test equipment to have interfaces equal to the number of chip signal channels, which puts high demands on the hardware resources of the test equipment and increases the test cost and complexity. Summary of the invention

[0004] The embodiments of the present application provide a chip testing method, device, storage medium and electronic device, which can improve the testing cost of chip testing.

[0005] In a first aspect, an embodiment of the present application provides a chip testing method, comprising: Determine the number of signal channels and test requirements of the chip to be tested; Determining a target channel configuration mode from preset channel configuration modes according to the number of signal channels and the test requirements; Configure a test channel for the chip according to the target channel configuration mode, each of the test channels corresponds to a signal channel group, and each of the signal channel groups includes at least two of the signal channels; Using a multiplexing module, selecting a target channel currently corresponding to each of the test channels from a corresponding signal channel group; The target channel is tested, and the step of using a multiplexing module to select the target channel currently corresponding to each test channel from the corresponding signal channel group is returned to be executed until the test of all the signal channels is completed.

[0006] In the chip testing method provided in the embodiment of the present application, configuring a test channel for the chip according to the target channel configuration mode includes: Grouping a plurality of the signal channels; A test channel is configured for each group of the signal channels according to the grouping result, and a redundant test channel and / or a parallel test channel is added according to the target channel configuration mode.

[0007] In the chip testing method provided in the embodiment of the present application, each of the signal channel groups includes 4 signal channels, and the preset channel configuration modes include a 4n+1 channel configuration mode and a 4n+4 channel configuration mode.

[0008] In the chip testing method provided in the embodiment of the present application, the multiplexing module is used to select the target channel currently corresponding to each test channel from the corresponding signal channel group, including: generating a selection control signal for a target channel according to a test plan; The multiplexing module is used to receive and analyze the selection control signal, and the target channel currently corresponding to each of the test channels is located.

[0009] In the chip testing method provided in the embodiment of the present application, after receiving and parsing the control signal using the multiplexing module to locate the target channel currently corresponding to each of the test channels, the method further includes: The internal connection path is adjusted by the multiplexing module to connect each of the test channels with the target channel in the corresponding signal channel group.

[0010] In the chip testing method provided in the embodiment of the present application, the test plan includes test parameters and test sequence for each of the signal channels.

[0011] The chip testing method provided in the embodiment of the present application also includes: Collecting test results of each of the signal channels; Analyzing the test results to evaluate the performance and reliability of the chip; When a fault is discovered, fault isolation testing is performed via redundant channels.

[0012] In a second aspect, an embodiment of the present application provides a chip testing device, including: A first determination unit, used to determine the number of signal channels and test requirements of the chip to be tested; A second determining unit, configured to determine a target channel configuration mode from preset channel configuration modes according to the number of signal channels and the test requirement; A channel configuration unit, configured to configure a test channel for the chip according to the target channel configuration mode, each of the test channels corresponds to a signal channel group, and each of the signal channel groups includes at least two of the signal channels; A target selection unit, used for selecting a target channel currently corresponding to each of the test channels from the corresponding signal channel group using a multiplexing module; The channel testing unit is used to test the target channel and return to execute the step of using the multiplexing module to select the target channel currently corresponding to each test channel from the corresponding signal channel group until the testing of all the signal channels is completed.

[0013] In a third aspect, the present application provides a storage medium storing a plurality of instructions suitable for loading by a processor to execute any of the chip testing methods described above.

[0014] In a fourth aspect, the present application provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements any of the above-mentioned chip testing methods when executing the computer program.

[0015] In summary, the chip testing method provided by the embodiment of the present application includes determining the number of signal channels and test requirements of the chip to be tested; determining the target channel configuration method from the preset channel configuration method according to the number of signal channels and the test requirements; configuring the test channel for the chip according to the target channel configuration method, each of the test channels corresponds to a signal channel group, and each of the signal channel groups includes at least two signal channels; using a multiplexing module, selecting the target channel currently corresponding to each of the test channels from the corresponding signal channel group; testing the target channel, and returning to execute the step of selecting the target channel currently corresponding to each of the test channels from the corresponding signal channel group using the multiplexing module, until all the signal channel tests are completed. This scheme can reduce the number of test channels and reduce testing costs through multiplexing technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0017] Figure 1 It is a flowchart of the chip testing method provided in the embodiment of the present application.

[0018] Figure 2 It is a flow chart of the chip testing device provided in the embodiment of the present application.

[0019] Figure 3It is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0020] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0021] It should be noted that, in this article, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element. In addition, components, features, and elements with the same name in different embodiments of the present application may have the same meaning or different meanings, and their specific meanings need to be determined by their explanation in the specific embodiment or further combined with the context of the specific embodiment.

[0022] It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0023] In the subsequent description, the suffixes such as "module", "component" or "unit" used to represent elements are only used to facilitate the description of the present application and have no specific meaning. Therefore, "module", "component" or "unit" can be used in a mixed manner.

[0024] In the description of the present application, it should be noted that the terms "upper", "lower", "left", "right", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, terms such as "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0025] At present, chip testing usually adopts the full-channel testing method, that is, the test equipment is directly connected to all the signal channels of the chip for testing. However, with the widespread application of high-complexity chips such as multi-core processors, SoC (system-on-chip) and AI acceleration chips, the number of signal channels and functional modules of modern chips continues to increase. Full-channel testing requires the test equipment to have interfaces equal to the number of chip signal channels, which puts high demands on the hardware resources of the test equipment and increases the test cost and complexity.

[0026] Based on this, the embodiments of the present application provide a chip testing method, device, storage medium and electronic device. Specifically, the chip testing device can be integrated in an electronic device, and the electronic device can be a server or a terminal. Among them, the terminal can include a mobile phone, a wearable smart device, a tablet computer, a laptop computer, and a personal computer (PC), etc.; the server can be a single server or a server cluster composed of multiple servers, and can be a physical server or a virtual server.

[0027] The technical solutions shown in the present application will be described in detail below through specific embodiments. It should be noted that the description order of the following embodiments is not intended to limit the priority order of the embodiments.

[0028] See also Figure 1 , Figure 1 : is a schematic diagram of the process of the chip testing method provided in the embodiment of the present application. The specific process of the chip testing method can be as follows: 101. Determine the number of signal channels and test requirements of the chip to be tested.

[0029] For example, the number of signal channels can be determined by looking at the technical specification document of the chip under test, which usually clearly marks the number of input / output signal channels of the chip, the signal type (such as analog signal, digital signal), channel function, etc. You can also count the number of all available signal channels based on the pin definition of the chip under test.

[0030] The test requirements may include functional test requirements, performance test requirements, reliability test requirements and redundant channel test requirements.

[0031] In some embodiments, the main indicators that need to be tested can be listed according to the expected functions of the chip. For example: throughput, stability and bit error rate test of the data channel. Frequency, duty cycle and jitter characteristics verification of the clock signal.

[0032] 102. Determine a target channel configuration mode from preset channel configuration modes according to the number of signal channels and test requirements.

[0033] The preset channel configuration modes include a 4n+1 channel configuration mode and a 4n+4 channel configuration mode.

[0034] In the 4n+1 channel configuration, each test channel corresponds to 4 signal channels, and the remaining channels are allocated to the last test channel. In the 4n+4 channel configuration, each test channel corresponds to 4 signal channels, and the extra channels can be used for redundant or parallel testing.

[0035] Among them, the 4n+1 channel configuration mode is suitable for scenarios where the number of channels is slightly higher than 4n, providing an extra channel for special testing or fault redundancy. During the test process, this extra channel can be used to monitor or test a specific channel, enhancing flexibility.

[0036] The 4n+4 channel configuration is suitable for scenarios with high-density signal channels. The extra channels are used for redundancy design and support stronger parallel capabilities. During the test process, the extra channels can be used for redundancy to ensure that the test can still be performed even if a channel fails.

[0037] For example, when the number of signal channels is M, if M mod 4=0, the 4n+4 channel configuration mode can be selected to increase redundancy; if M mod 4≠0, the 4n+1 channel configuration mode can be selected to reduce the waste of unused channels.

[0038] In some embodiments, the target channel configuration mode can be further determined in combination with the test requirements. For example, if the test requirements require more parallel capabilities, the 4n+4 channel configuration mode is preferred. If the channel switching is frequent and the test priority is clear, it is more efficient to select the 4n+1 channel configuration mode. When redundancy is required, a configuration with more redundant channels (such as 4n+4) is preferred.

[0039] 103. Configure a test channel for the chip according to the target channel configuration mode.

[0040] In the embodiment of the present application, each test channel corresponds to a signal channel group, each signal channel group includes at least two signal channels, and each signal channel group corresponds to four signal channels.

[0041] Specifically, several signal channels may be grouped; a test channel may be configured for each group of signal channels according to the grouping result, and redundant test channels and / or parallel test channels may be added according to the target channel configuration mode.

[0042] For the 4n+1 channel configuration, N 测试信道 =⌈M / 4⌉+1. For the 4n+4 channel configuration, N 测试信道 =⌈M / 4⌉+4. Here, ⌈⋅⌉ means rounding up.

[0043] 104. Using the multiplexing module, select the target channel currently corresponding to each test channel from the corresponding signal channel group.

[0044] Specifically, a selection control signal of a target channel may be generated according to a test plan; a multiplexing module may be used to receive and parse the selection control signal to locate the target channel currently corresponding to each test channel.

[0045] The test plan may include test parameters and test sequence for each signal channel. In the specific implementation process, the target channels may be selected in sequence according to the test sequence.

[0046] In some embodiments, after the target channel is determined, the internal connection path may be adjusted through a multiplexing module to connect each test channel with the target channel in the corresponding signal channel group.

[0047] 105. Test the target channel, and return to execute the step of using the multiplexing module to select the target channel currently corresponding to each test channel from the corresponding signal channel group until the test of all signal channels is completed.

[0048] After the test is completed, the test results of each signal channel can also be collected; the test results are analyzed to evaluate the performance and reliability of the chip; when a fault is found, fault isolation testing is performed through redundant channels.

[0049] After completing the test of all channels, the data can be summarized and a final test report can be generated.

[0050] In summary, the chip testing method provided by the embodiment of the present application includes determining the number of signal channels and test requirements of the chip to be tested; determining the target channel configuration mode from the preset channel configuration mode according to the number of signal channels and the test requirements; configuring the test channel for the chip according to the target channel configuration mode, each test channel corresponds to a signal channel group, and each signal channel group includes at least two signal channels; using a multiplexing module, selecting the target channel currently corresponding to each test channel from the corresponding signal channel group; testing the target channel, and returning to execute the step of selecting the target channel currently corresponding to each test channel from the corresponding signal channel group using the multiplexing module until all signal channel tests are completed. This scheme can reduce the number of test channels and reduce the test cost through multiplexing technology. In addition, the test time can be significantly shortened through target channel switching and parallel testing mechanism. Using redundant channel design and multiplexing module, the fault tolerance of the test system is improved. It can also ensure that all signal channels can be efficiently tested to ensure the comprehensiveness and accuracy of chip function and performance verification.

[0051] In order to better implement the chip testing method provided in the embodiment of the present application, the embodiment of the present application also provides a chip testing device, wherein the meanings of the terms are the same as those in the above chip testing method, and the specific implementation details can refer to the description in the method embodiment.

[0052] See also Figure 2 , Figure 2 201 is a schematic diagram of the structure of a chip testing device provided in an embodiment of the present application. The chip testing device may include a first determination unit 201, a second determination unit 202, a channel configuration unit 203, a target selection unit 204 and a channel testing unit 205. The first determining unit 201 is used to determine the number of signal channels and test requirements of the chip to be tested; A second determining unit 202 is used to determine a target channel configuration mode from preset channel configuration modes according to the number of signal channels and test requirements; A channel configuration unit 203 is used to configure a test channel for the chip according to the target channel configuration mode, each test channel corresponds to a signal channel group, and each signal channel group includes at least two signal channels; The target selection unit 204 is used to select the target channel currently corresponding to each test channel from the corresponding signal channel group by using the multiplexing module; The channel testing unit 205 is used to test the target channel and return to execute the step of using the multiplexing module to select the target channel currently corresponding to each test channel from the corresponding signal channel group until the testing of all signal channels is completed.

[0053] The specific implementation of each of the above units can refer to the above-mentioned embodiment of the chip testing method, which will not be described one by one here.

[0054] In summary, the chip testing device provided in the embodiment of the present application can determine the number of signal channels and test requirements of the chip to be tested by the first determination unit 201; the second determination unit 202 determines the target channel configuration mode from the preset channel configuration mode according to the number of signal channels and the test requirements; the channel configuration unit 203 configures the test channel for the chip according to the target channel configuration mode, each test channel corresponds to a signal channel group, and each signal channel group includes at least two signal channels; the target selection unit 204 uses the multiplexing module to select the target channel currently corresponding to each test channel from the corresponding signal channel group; the channel test unit 205 tests the target channel and returns to execute the step of selecting the target channel currently corresponding to each test channel from the corresponding signal channel group using the multiplexing module until all signal channel tests are completed. This scheme can reduce the number of test channels and reduce the test cost through multiplexing technology. In addition, the test time can be significantly shortened through target channel switching and parallel testing mechanism. The fault tolerance of the test system is improved by using redundant channel design and multiplexing modules. It can also ensure that all signal channels can be tested efficiently, ensuring the comprehensiveness and accuracy of chip function and performance verification.

[0055] The present application also provides an electronic device, in which the chip testing device of the present application can be integrated, such as Figure 3 As shown, it shows a schematic diagram of the structure of the electronic device involved in the embodiment of the present application, specifically: The electronic device may include one or more processors 301 of processing cores and one or more computer-readable storage media memories 302 and other components. Those skilled in the art will appreciate that Figure 3 The electronic device structure shown in the figure does not constitute a limitation on the electronic device, and may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently. The processor 301 is the control center of the electronic device, which uses various interfaces and lines to connect various parts of the entire electronic device, and executes various functions of the electronic device and processes data by running or executing the software program and / or the present application stored in the memory 302, and calling the data stored in the memory 302, so as to monitor the electronic device as a whole. Optionally, the processor 301 may include one or more processing cores; preferably, the processor 301 may integrate an application processor and a modem processor, wherein the application processor mainly processes the operation storage medium, user interface and application program, etc., and the modem processor mainly processes wireless communication. It is understandable that the above-mentioned modem processor may not be integrated into the processor 301.

[0056] The memory 302 can be used to store software programs and the present application. The processor 301 executes various functional applications and data processing by running the software programs and the present application stored in the memory 302. The memory 302 may mainly include a program storage area and a data storage area, wherein the program storage area may store an operating storage medium, an application required for at least one function (such as a sound playback function, an image playback function, etc.), etc.; the data storage area may store data created according to the use of the electronic device, etc. In addition, the memory 302 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other volatile solid-state storage devices. Accordingly, the memory 302 may also include a memory controller to provide the processor 301 with access to the memory 302.

[0057] Although not shown, the electronic device may further include a display unit, an input unit, a power supply, etc., which will not be described in detail herein. Specifically in this embodiment, the processor 301 in the electronic device will load the executable files corresponding to the processes of one or more application programs into the memory 302 according to the following instructions, and the processor 301 will run the application programs stored in the memory 302, thereby realizing various functions, as follows: Determine the number of signal channels and test requirements of the chip to be tested; Determine a target channel configuration mode from preset channel configuration modes according to the number of signal channels and test requirements; Configure a test channel for the chip according to the target channel configuration mode, each test channel corresponds to a signal channel group, and each signal channel group includes at least two signal channels; Using the multiplexing module, the target channel currently corresponding to each test channel is selected from the corresponding signal channel group; The target channel is tested, and the step of using the multiplexing module to select the target channel currently corresponding to each test channel from the corresponding signal channel group is returned to be executed until the testing of all signal channels is completed.

[0058] A person of ordinary skill in the art will appreciate that all or part of the steps in the various methods of the above embodiments may be completed by instructions, or by controlling related hardware through instructions. The instructions may be stored in a computer-readable storage medium and loaded and executed by a processor.

[0059] To this end, an embodiment of the present application provides a storage medium in which a plurality of instructions are stored, and the instructions can be loaded by a processor to execute the steps in any one of the generation methods provided in the embodiments of the present application. For example, the instructions can execute the following steps: Determine the number of signal channels and test requirements of the chip to be tested; Determine a target channel configuration mode from preset channel configuration modes according to the number of signal channels and test requirements; Configure a test channel for the chip according to the target channel configuration mode, each test channel corresponds to a signal channel group, and each signal channel group includes at least two signal channels; Using the multiplexing module, the target channel currently corresponding to each test channel is selected from the corresponding signal channel group; The target channel is tested, and the step of using the multiplexing module to select the target channel currently corresponding to each test channel from the corresponding signal channel group is returned to be executed until the testing of all signal channels is completed.

[0060] The specific implementation of the above operations can be found in the previous embodiments, which will not be described in detail here.

[0061] The storage medium may include: a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0062] Since the instructions stored in the storage medium can execute the steps in any method provided in the embodiments of the present application, the beneficial effects that can be achieved by any method provided in the embodiments of the present application can be achieved. Please refer to the previous embodiments for details and will not be repeated here.

[0063] The chip testing method, device, storage medium and electronic device provided by the present application are respectively introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the core idea of ​​the present application; at the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A chip testing method, characterized in that: include: Determine the number of signal channels and test requirements of the chip to be tested; Determining a target channel configuration mode from preset channel configuration modes according to the number of signal channels and the test requirements; Configure a test channel for the chip according to the target channel configuration mode, each of the test channels corresponds to a signal channel group, and each of the signal channel groups includes at least two of the signal channels; Using a multiplexing module, selecting a target channel currently corresponding to each of the test channels from a corresponding signal channel group; The target channel is tested, and the step of using a multiplexing module to select the target channel currently corresponding to each test channel from the corresponding signal channel group is returned to be executed until the test of all the signal channels is completed.

2. The chip testing method according to claim 1, characterized in that: The configuring a test channel for the chip according to the target channel configuration mode includes: Grouping a plurality of the signal channels; A test channel is configured for each group of the signal channels according to the grouping result, and a redundant test channel and / or a parallel test channel is added according to the target channel configuration mode.

3. The chip testing method according to claim 2, characterized in that: Each of the signal channel groups includes four signal channels, and the preset channel configuration modes include a 4n+1 channel configuration mode and a 4n+4 channel configuration mode.

4. The chip testing method according to claim 1, characterized in that: The method of using a multiplexing module to select a target channel currently corresponding to each of the test channels from a corresponding signal channel group includes: generating a selection control signal for a target channel according to a test plan; The multiplexing module is used to receive and analyze the selection control signal, and the target channel currently corresponding to each of the test channels is located.

5. The chip testing method according to claim 4, characterized in that: After receiving and parsing the control signal using a multiplexing module to locate the target channel currently corresponding to each of the test channels, the method further includes: The internal connection path is adjusted by the multiplexing module to connect each of the test channels with the target channel in the corresponding signal channel group.

6. The chip testing method according to claim 4, characterized in that: The test plan includes test parameters and a test sequence for each of the signal channels.

7. The chip testing method according to claim 1, characterized in that: Also includes: Collecting test results of each of the signal channels; Analyzing the test results to evaluate the performance and reliability of the chip; When a fault is discovered, fault isolation testing is performed via redundant channels.

8. A chip testing device, characterized in that: include: A first determination unit, used to determine the number of signal channels and test requirements of the chip to be tested; A second determining unit, configured to determine a target channel configuration mode from preset channel configuration modes according to the number of signal channels and the test requirement; A channel configuration unit, configured to configure a test channel for the chip according to the target channel configuration mode, each of the test channels corresponds to a signal channel group, and each of the signal channel groups includes at least two of the signal channels; A target selection unit, used for selecting a target channel currently corresponding to each of the test channels from the corresponding signal channel group using a multiplexing module; The channel testing unit is used to test the target channel and return to execute the step of using the multiplexing module to select the target channel currently corresponding to each test channel from the corresponding signal channel group until the testing of all the signal channels is completed.

9. A storage medium, characterized in that: The storage medium stores a plurality of instructions, and the instructions are suitable for being loaded by a processor to execute the chip testing method according to any one of claims 1 to 7.

10. An electronic device, characterized in that: The method comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor implements the chip testing method according to any one of claims 1 to 7 when executing the computer program.

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