General test method and device for isolation chip and readable storage medium

Abstract

The invention discloses a general test method and device for an isolation chip and a readable storage medium, and relates to the technical field of electronic device tests.The general test device comprises a test daughter board, and the test daughter board connects pins of the isolation chip to be tested to a test bottom board; the test base plate is provided with the maximum pin number and the maximum isolation channel number according to the pin distribution rule of the isolation chip, and the isolation channel direction is set to be bidirectional; the test daughter board is connected above the test bottom board, and a resource leading-out board of a CTA8280F simulation test machine is connected below the test bottom board. The test daughter board is used for connecting pins of different types of isolation chips to the test base board. Different types of isolation chips can be tested only by replacing different test daughter boards, so that the difficulty and the period of test development can be reduced.

Description

Technical Field

[0001] The present application relates to the technical field of electronic device testing, and in particular to a universal testing method, device and readable storage medium for an isolation chip. Background Art

[0002] The traditional isolation chip testing method is to write a corresponding test program on the CTA8280F simulator according to the specific isolation chip model for testing. However, due to the different types of isolation chips on the market, their packaging forms and pin numbers are different. Specifically, the isolation chips on the market currently have 2-channel, 4-channel, and 6-channel isolation. On this basis, there are also input and output configurations in different directions. For example, the 2-channel isolation chip includes the first type, both channels are left input and right output configuration mode, the second type, one channel is left input and right output configuration mode, and the other channel is right input and left output configuration mode, and the third type, both channels are right input and left output configuration mode. 4-channel and 6-channel isolation chips are similar. The packaging form is divided into SSOP, SOIC, SOICW and other packaging forms; this leads to the disadvantages of test development not being portable, difficult test development, and long cycle; In view of this, there is an urgent need for a universal test method for isolation chips, which can use a set of test systems to complete the automated testing of isolation chips with different numbers of pins and different packages, facilitate program transplantation, and reduce the difficulty and cycle of test development. Summary of the invention

[0003] In view of the shortcomings of the prior art described above, the present application proposes a universal testing method, device and readable storage medium for isolation chips, which solves the problem in the prior art that it is impossible to complete automated testing of isolation chips with different numbers of pins and different packages using one test system.

[0004] In order to achieve the above-mentioned purpose, this application specifically adopts the following technical solutions: A universal test method for an isolation chip comprises a test sub-board, wherein the test sub-board connects the pins of the isolation chip to be tested to a test baseboard; the test baseboard sets a maximum number of pins and a maximum number of isolation channels according to the pin distribution rule of the isolation chip, and the isolation channel direction is set to be bidirectional; the test baseboard is connected to the test sub-board at the top and to a resource lead-out board of a CTA8280F simulation test machine at the bottom; and a processing terminal of the CTA8280F simulation test machine tests DC parameters and AC parameters of the isolation chip to be tested.

[0005] As an optional technical solution, the test process of the DC parameters and AC parameters includes performing non-isolated side test and isolated side test of the isolation chip to be tested through resource configuration on a CTA8280F simulation test machine, wherein the non-isolated side test of the isolation chip to be tested is: DC parameter test, open the non-isolated side DC channel relay, select the channel number and connect it to the floating source to perform all DC parameter tests: close the non-isolated side DC channel relay and disconnect it from the floating source; the DC parameters include power supply current IDD, input high level voltage threshold VIH, input low level voltage threshold VIL, output high level voltage value VOH, and output low level voltage value VOL.

[0006] AC parameter test, turn on the AC channel relay on the non-isolated side, select the number of channels and connect it to the time test board, perform transmission delay and output waveform rise and fall tests, turn on the output state configuration relay on the non-isolated side channel, select the corresponding load state, and perform a transmission delay test from the enable signal to the output signal; the AC parameters include the maximum rate fMAX, transmission delay tPLH / tPHL, rising edge time tR, falling edge time tF, enable transmission time tPZH / tPZL, and disable transmission time tPHZ / tPLZ.

[0007] The isolation side test of the isolation chip to be tested is: DC parameter test, open the DC channel relay on the isolation side, select the channel number and connect it to the floating source to perform all DC parameter tests: close the DC channel relay on the isolation side and disconnect it from the floating source; the DC parameters include power supply current IDD, input high level voltage threshold VIH, input low level voltage threshold VIL, output high level voltage value VOH, and output low level voltage value VOL.

[0008] AC parameter test, turn on the AC channel relay on the isolation side, select the number of channels and connect it to the time test board, perform transmission delay and output waveform rise and fall tests, turn on the output state configuration relay of the isolation side channel, select the corresponding load state, and perform a transmission delay test from the enable signal to the output signal; the AC parameters include the maximum rate fMAX, transmission delay tPLH / tPHL, rising edge time tR, falling edge time tF, enable transmission time tPZH / tPZL, and disable transmission time tPHZ / tPLZ.

[0009] After the non-isolated side test and the isolated side test of the isolation chip to be tested are completed, all resources of the CTA8280F simulation test machine are powered off and disconnected from the pins of the isolation chip to be tested.

[0010] As an optional technical solution, when testing the transmission delay and the rise and fall of the output waveform, the input pin is the input signal and the output pin is the detection signal.

[0011] As an optional technical solution, when performing a transmission delay test from an enable signal to an output signal, the enable pin is an input signal and the output pin is a detection signal.

[0012] As an optional technical solution, the test sub-board is a first PCB substrate, including an upper surface and a lower surface relative to each other, the upper surface is provided with a test socket that can fix the isolation chip to be tested, and the lower surface is provided with a European connector plug.

[0013] As an optional technical solution, the test base plate is a second PCB substrate, the upper surface of the second PCB substrate is provided with a socket matching the European connector plug on the lower surface of the first PCB substrate, a plurality of connection holes are provided on the second PCB substrate, and a pogo pin connector is provided on the lower surface of the second PCB substrate.

[0014] As an optional technical solution, the resource lead-out board is a third PCB substrate, a plurality of connection holes are arranged on the third PCB substrate, corresponding one-to-one with the connection holes on the second PCB substrate, and the third PCB substrate is detachably connected to the second PCB substrate via a connector; The third PCB substrate includes an upper surface and a lower surface relative to each other, the upper surface includes a pogo pin connection area matching the pogo pin connector on the second PCB substrate, and the lower surface is connected to the CTA8280F simulation test machine.

[0015] An electronic device comprises: one or more processors, a memory and one or more computer programs, wherein the one or more computer programs are stored in the memory, and the one or more computer programs include instructions, and when the instructions are executed by the electronic device, the one or more processors execute the described method.

[0016] A computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method described is implemented.

[0017] The beneficial effects of this application include: The function of the test sub-board is to connect the pins of different types of isolation chips to the test baseboard. If you want to test different types of isolation chips, you only need to replace different test sub-boards, which reduces the difficulty and cycle of test development. The isolation chip test program selects the number of isolation channels and the direction of isolation channels based on the isolation chip universal test program framework. You only need to select the corresponding relay bit number in the universal test program framework to configure the test program with different numbers of isolation channels and different directions of isolation channels, which is the so-called test program for different types of isolation chips. With this universal test program framework, the development cycle can be greatly reduced, and even beginners can quickly develop the program.

[0018] Other beneficial effects or advantages of the present application will be described in detail in conjunction with the specific structure in the specific implementation manner. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative labor. In addition, it should be understood that the proportional relationship of the various components in the drawings of this specification does not represent the proportional relationship in the actual material selection and design, which is only a schematic diagram of the structure or position, where: Figure 1 This is the isolation chip testing schematic diagram in this application. DETAILED DESCRIPTION

[0020] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0021] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0022] In the description of this application, it should be noted that the terms used, such as "top" and "bottom", refer to the part of this application that is close to the top when in use as the top, and the part that is close to the bottom as the bottom; the terms used, such as "first" and "second", are only used to distinguish expressions, and do not indicate or imply that they have a difference in importance or order; the terms used, such as "inside" and "outside", refer to the inside and outside of a specific contour. The use of the above terms is only to facilitate a clear and simple description of the technical solution of this application, and cannot be understood as a limitation on this application.

[0023] Embodiment 1: like Figure 1As shown, the present invention discloses a universal testing method for an isolation chip, comprising a test sub-board, wherein the test sub-board connects the pins of the isolation chip to be tested to a test baseboard; the test baseboard sets a maximum number of pins and a maximum number of isolation channels according to the pin distribution rule of the isolation chip, and the isolation channel direction is set to be bidirectional; the test baseboard is connected to the test sub-board at the top and to the resource lead-out board of a CTA8280F analog test machine at the bottom; the processing terminal of the CTA8280F analog test machine tests the DC parameters and AC parameters of the isolation chip to be tested.

[0024] It is particularly important to explain that: although some basic content has been mentioned in the published document CN117632609B, the general test of the microprocessor chip mentioned in the published document is completely different from the general test of the isolation chip recorded in this article. The general test of the microprocessor chip is based on the maximum number of pins, because the pins of the microprocessor chip can be reused for other functions, such as ADC, DAC, timer, etc., so the maximum number of pins is needed as a restriction condition for backward compatibility general test. The function of the isolation chip is only to isolate the signals on the input and output sides, and its pins do not have the multiplexing function, so here in addition to the maximum number of pins as a restriction condition for backward compatibility general test, the maximum number of isolation channels and isolation direction are also needed as restriction conditions for backward compatibility general test. The essence is that microprocessor chips and isolation channel chips are different types of chips, and the ideas used in testing are different.

[0025] Traditional isolation chip testing is: Because the isolation chip has 2-channel, 4-channel, and 6-channel isolation, there are also input and output configurations in different directions on this basis. For example, the 2-channel isolation chip includes the first type where both channels are in left input and right output configuration mode, the second type where one channel is in left input and right output configuration mode, and the other channel is in right input and left output configuration mode, and the third type where both channels are in right input and left output configuration mode. The 4-channel and 6-channel isolation chips are similar. The packaging form is divided into SSOP, SOIC, SOICW and other packaging forms. The current test method is to write the corresponding test program on the CTA8280F simulator according to the specific isolation chip model for testing. One problem involved here is that isolation chips of different models have different packaging forms and pin numbers (number of isolation channels), which leads to the disadvantages of test development not being portable, difficult test development, and long cycles. After the improvement of this solution, universal testing of different channels and different output directions can be achieved: By setting the maximum number of pins and the maximum number of isolation channels on the test baseboard according to the pin distribution rules of the isolation chip, and setting the isolation channel direction to bidirectional, the problem that universal testing cannot be performed at the hardware level is solved; Furthermore, the test baseboard is connected to the test sub-board on the top and to the resource lead-out board of the CTA8280F analog test machine on the bottom; the processing terminal of the CTA8280F analog test machine tests the DC parameters and AC parameters of the isolation chip to be tested, which solves the problem that isolation chips of different models have different packaging forms and pin numbers, which leads to the shortcomings of test development being non-portable, difficult, and long in cycle.

[0026] It is understandable that the solution described in the present invention improves the traditional one-to-one testing device into a universal device, as follows: The CTA8280F analog test machine has the advantages of high test accuracy, fast test speed, good stability, high reliability, and strong anti-interference ability. It is suitable for various analog circuits and mixed digital-analog circuits such as linear circuits such as op amps, power amplifier circuits, motor drive circuits, power management circuits, radio circuits, etc., and meets the testing requirements of isolation chips. The test baseboard sets a maximum of 6 channels according to the pin distribution rules of the isolation chip, and the isolation channel direction is set to bidirectional, and leads to the resource lead-out board connected to the CTA8280F analog test machine for DC parameter and AC parameter testing.

[0027] The resource lead-out board on the CTA8280F simulation test machine does not have a test function. It can only lead the test resources out of the CTA8280F simulation test machine. It must be connected to the test baseboard before starting the test.

[0028] The test sub-board is multi-modal in shape, and each mode includes a test socket. Each test socket can match a group of isolation chips to be tested with the same number of isolation channels. The function of the test sub-board is to connect the isolation channels of isolation chips of different models to the test baseboard. If you want to test different types of isolation chips, you only need to replace different test sub-boards, which reduces the difficulty and cycle of test development.

[0029] It should be noted that: traditional testing does not use universal test boards. Each time a chip model is tested, a large base board needs to be drawn and many chips need to be soldered. Now the operator only needs to replace the upper test sub-board to complete the test work. It is understandable that the main categories of isolation chips are 2-channel, 4-channel, and 6-channel isolation, so the number of test sub-boards will not be too many. Several test sub-boards can be combined with a fixed bottom test board to achieve the test purpose, reducing the difficulty and cycle of test development.

[0030] As an optional technical solution, the test process of the DC parameters and AC parameters includes performing non-isolated side test and isolated side test of the isolation chip to be tested through resource configuration on a CTA8280F simulation test machine, wherein the non-isolated side test of the isolation chip to be tested is: DC parameter test, open the non-isolated side DC channel relay, select the channel number and connect it to the floating source to perform all DC parameter tests: close the non-isolated side DC channel relay and disconnect it from the floating source; the DC parameters include power supply current IDD, input high level voltage threshold VIH, input low level voltage threshold VIL, output high level voltage value VOH, and output low level voltage value VOL.

[0031] AC parameter test, turn on the AC channel relay on the non-isolated side, select the number of channels and connect it to the time test board, perform transmission delay and output waveform rise and fall tests, turn on the output state configuration relay on the non-isolated side channel, select the corresponding load state, and perform a transmission delay test from the enable signal to the output signal; the AC parameters include the maximum rate fMAX, transmission delay tPLH / tPHL, rising edge time tR, falling edge time tF, enable transmission time tPZH / tPZL, and disable transmission time tPHZ / tPLZ.

[0032] The isolation side test of the isolation chip to be tested is: DC parameter test, open the DC channel relay on the isolation side, select the channel number and connect it to the floating source to perform all DC parameter tests: close the DC channel relay on the isolation side and disconnect it from the floating source; the DC parameters include power supply current IDD, input high level voltage threshold VIH, input low level voltage threshold VIL, output high level voltage value VOH, and output low level voltage value VOL.

[0033] AC parameter test, turn on the AC channel relay on the isolation side, select the number of channels and connect it to the time test board, perform transmission delay and output waveform rise and fall tests, turn on the output state configuration relay of the isolation side channel, select the corresponding load state, and perform a transmission delay test from the enable signal to the output signal; the AC parameters include the maximum rate fMAX, transmission delay tPLH / tPHL, rising edge time tR, falling edge time tF, enable transmission time tPZH / tPZL, and disable transmission time tPHZ / tPLZ.

[0034] After the non-isolated side test and the isolated side test of the isolation chip to be tested are completed, all resources of the CTA8280F simulation test machine are powered off and disconnected from the pins of the isolation chip to be tested.

[0035] As an optional technical solution, when testing the transmission delay and output waveform rise and fall, the input pin is the input signal and the output pin is the detection signal. When testing the transmission delay from the enable signal to the output signal, the enable pin is the input signal and the output pin is the detection signal.

[0036] It should be noted that the input pin here is the input of the isolation channel of the isolation chip, the output pin here is the output of the isolation channel of the isolation chip, and the enable pin here is the enable signal control pin of the isolation chip. The chip works when the level is high, and does not work when the level is low. The timing test of all chips is like this. The chip is installed on the test sub-board.

[0037] As an optional technical solution, the test sub-board is a first PCB substrate, including a relative upper surface and a lower surface, the upper surface is provided with a test socket that can fix the isolation chip to be tested, and the lower surface is provided with a European connector plug. The test base plate is a second PCB substrate, the upper surface of the second PCB substrate is provided with a socket that matches the European connector plug on the lower surface of the first PCB substrate, the second PCB substrate is provided with a plurality of connection holes, and the lower surface of the second PCB substrate is provided with a pogo pin connector. The resource lead-out board is a third PCB substrate, the third PCB substrate is provided with a plurality of connection holes that correspond to the connection holes on the second PCB substrate one by one, and the third PCB substrate is detachably connected to the second PCB substrate through a connector; the third PCB substrate includes a relative upper surface and a lower surface, the upper surface includes a pogo pin connection area that matches the pogo pin connector on the second PCB substrate, and the lower surface is connected to the CTA8280F simulation test machine.

[0038] Further explain how the three PCB substrates are connected. From top to bottom, they are the first PCB substrate, the second PCB substrate and the third PCB substrate. The first PCB substrate and the second PCB substrate are specially designed to achieve the purpose of this solution. By designing the first PCB substrate and the second PCB substrate, it is achieved that to test different types of isolation chips, only different test sub-boards need to be replaced, thereby reducing the difficulty and cycle of test development; due to the chip characteristics on the second PCB substrate, the test baseboard described in this solution can accommodate up to 6 isolation channels; and the third PCB substrate is the resource lead-out board that comes with the CTA8280F simulation test machine. The CTA8280F simulation test machine is an existing product, and the test baseboard of this solution is designed one-to-one for the CTA8280F simulation test machine.

[0039] When specifically designing the first PCB substrate and the second PCB substrate, it is only necessary to meet the above test purpose without making any specific structural restrictions. For example, the design may be as follows: The test sub-board, i.e., the first PCB substrate, has an upper surface core including a test socket and a lower surface core including a capacitor; The test base plate, i.e., the second PCB substrate, has a core on the upper surface including resistors, capacitors, LEDs, relays, SMA sockets, TPS modules, horn sockets, European connectors, and high-speed comparator chips; the core on the lower surface includes relays, resistors, capacitors, and LDO chips; The function of the test seat is to place the isolation chip to be tested; The resistors include pull-up resistors, pull-down resistors and current-limiting resistors, wherein the pull-up resistor is a resistor connected in series between the power supply voltage and the pin, and the current pin state is 1 by default; the pull-down resistor is a resistor connected in series between the ground and the pin, and the current pin state is 0 by default; the current-limiting resistor is a resistor connected in series between the power supply voltage and the LED, which reduces the current flowing through the LED to prevent the LED from burning due to excessive current; The capacitors include filter capacitors and energy storage capacitors, where the filter capacitor: filters out the noise on the power supply voltage to keep the power supply voltage stable, and a filter capacitor needs to be connected in parallel with the power supply pin. Energy storage capacitor: when the load current of the chip suddenly increases, the power supply current will also suddenly increase. In order to prevent the power supply voltage from suddenly dropping, an energy storage capacitor needs to be connected in parallel with the power supply pin; The LED light is used to display the switch status of the relay. The relay functions as follows: controlling the connection and disconnection between the pin of the isolated chip to be tested and the CTA8280F floating source; controlling the connection and disconnection between the pin of the isolated chip to be tested and the CTA8280F time test board.

[0040] The function of the SMA socket is to connect the signal sent by the CTA8280F simulation test machine to the base plate and to the isolation chip to be tested through the daughter board; the signal sent by the isolation chip to be tested enters the base plate through the daughter board and returns to the CTA8280F simulation test machine through the SMA socket.

[0041] The functions of the TPS module are: a time waveform processing and calculation module that can calculate the time difference between the input signal and the output signal, the time of the rising edge and the falling edge of the signal, etc.; The function of the horn seat is to physically connect the test baseboard and the resources of the CTA8280F simulation test machine; The function of the European connector is to physically connect the test base board and the test sub-board; The function of the high-speed comparator chip is to make the rising and falling edges of the signal sent by the CTA8280F analog test machine steeper, so that the measured time parameters are more accurate; The function of the LDO chip is to convert the 15V voltage into a 12V voltage to power the TPS module; An electronic device comprises: one or more processors, a memory and one or more computer programs, wherein the one or more computer programs are stored in the memory, and the one or more computer programs include instructions, and when the instructions are executed by the electronic device, the one or more processors execute the method proposed in the present application.

[0042] It can be known from the above description of the implementation method that those skilled in the art can clearly understand that all or part of the steps in the above implementation method can be implemented by means of software plus a necessary general hardware platform. Based on this understanding, the above computer program product may include but is not limited to APP; A computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method proposed in the present application is implemented.

[0043] In several embodiments provided by the present invention, if any function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on such an understanding, some technical solutions of the present invention, in essence, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product as described below.

[0044] Continuing from the above, the above-mentioned device / terminal may be a computer device, and the hardware structure of the computer device may also specifically include: at least one processor, at least one communication interface, at least one memory and at least one communication bus; the processor, the communication interface and the memory may communicate with each other through the communication bus. Among them, the processor may be a central processing unit CPU, DSP, microcontroller or digital signal processor, and may also include GPU, embedded neural network processor NPU and image signal processor ISP. The processor may also include a specific integrated circuit ASIC, or one or more integrated circuits configured to implement the embodiment of the present invention, etc. In addition, the processor may have the function of operating one or more software programs, and the software programs may be stored in a storage medium such as a memory; and the aforementioned memory / storage medium may include: non-volatile memory, such as a non-removable disk, a USB flash drive, a mobile hard disk, an optical disk, etc., as well as a read-only memory ROM, a random access memory RAM, etc.

[0045] Those skilled in the art will appreciate that the various modules, units, and method steps described in the embodiments disclosed in this specification can be implemented by a combination of electronic hardware, computer software, and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0046] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A universal testing method for an isolation chip, characterized in that: It includes a test sub-board, which connects the pins of the isolation chip to be tested to the test base board; The test base plate sets the maximum number of pins and the maximum number of isolation channels according to the pin distribution rules of the isolation chip, and the isolation channel direction is set to bidirectional; The upper part of the test baseboard is connected to the test sub-board, and the lower part is connected to the resource lead-out board of the CTA8280F simulation test machine; The processing terminal of the CTA8280F simulation test machine performs DC parameter and AC parameter tests on the isolation chip to be tested.

2. A universal testing method for an isolation chip as claimed in claim 1, characterized in that: The testing process of the DC parameters and AC parameters includes performing non-isolated side testing and isolated side testing of the isolation chip to be tested through resource configuration on the CTA8280F simulation test machine, wherein: The non-isolated side test of the isolated chip to be tested is: DC parameter test: open the non-isolated DC channel relay, select the channel number and connect it to the floating source to test all DC parameters: close the non-isolated DC channel relay and disconnect it from the floating source; the DC parameters include power supply current IDD, input high level voltage threshold VIH, input low level voltage threshold VIL, output high level voltage value VOH, and output low level voltage value VOL; AC parameter test: turn on the AC channel relay on the non-isolated side, select the number of channels and connect it to the time test board, perform transmission delay and output waveform rise and fall tests, turn on the output state configuration relay on the non-isolated side channel, select the corresponding load state, and perform a transmission delay test from the enable signal to the output signal; the AC parameters include the maximum rate fMAX, transmission delay tPLH / tPHL, rising edge time tR, falling edge time tF, enable transmission time tPZH / tPZL, and disable transmission time tPHZ / tPLZ; The isolation side test of the isolation chip to be tested is: DC parameter test: open the DC channel relay on the isolation side, select the channel number and connect it to the floating source to test all DC parameters: close the DC channel relay on the isolation side and disconnect it from the floating source; the DC parameters include power supply current IDD, input high level voltage threshold VIH, input low level voltage threshold VIL, output high level voltage value VOH, and output low level voltage value VOL; AC parameter test: turn on the AC channel relay on the isolation side, select the number of channels and connect it to the time test board, perform transmission delay and output waveform rise and fall tests, turn on the output state configuration relay of the isolation side channel, select the corresponding load state, and perform a transmission delay test from the enable signal to the output signal; the AC parameters include the maximum rate fMAX, transmission delay tPLH / tPHL, rising edge time tR, falling edge time tF, enable transmission time tPZH / tPZL, and disable transmission time tPHZ / tPLZ; After the non-isolated side test and the isolated side test of the isolation chip to be tested are completed, all resources of the CTA8280F simulation test machine are powered off and disconnected from the pins of the isolation chip to be tested.

3. A universal testing method for an isolation chip as claimed in claim 1, characterized in that: When testing the transmission delay and the rise and fall of the output waveform, the input pin is the input signal and the output pin is the detection signal.

4. A universal testing method for an isolation chip as claimed in claim 1, characterized in that: When performing a transmission delay test from an enable signal to an output signal, the enable pin is the input signal and the output pin is the detection signal.

5. A universal testing method for an isolation chip as claimed in claim 1, characterized in that: The test sub-board is a first PCB substrate, comprising an upper surface and a lower surface relative to each other, wherein a test socket capable of fixing the isolation chip to be tested is arranged on the upper surface, and a European connector plug is arranged on the lower surface.

6. A universal testing method for an isolation chip as claimed in claim 1, characterized in that: The test base plate is a second PCB substrate, the upper surface of the second PCB substrate is provided with a socket matching the European connector plug on the lower surface of the first PCB substrate, a plurality of connection holes are provided on the second PCB substrate, and a pogo pin connector is provided on the lower surface of the second PCB substrate.

7. A universal testing method for an isolation chip as claimed in claim 1, characterized in that: The resource lead-out board is a third PCB substrate, a plurality of connection holes are arranged on the third PCB substrate, corresponding one-to-one with the connection holes on the second PCB substrate, and the third PCB substrate is detachably connected to the second PCB substrate via a connector; The third PCB substrate includes an upper surface and a lower surface relative to each other, the upper surface includes a pogo pin connection area matching the pogo pin connector on the second PCB substrate, and the lower surface is connected to the CTA8280F simulation test machine.

8. An electronic device, characterized in that: include: One or more processors, a memory, and one or more computer programs, wherein the one or more computer programs are stored in the memory, and the one or more computer programs include instructions, which, when executed by the electronic device, cause the one or more processors to perform the method described in any one of claims 1 to 7.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 7 is implemented.

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