OPC correction method

Abstract

The invention provides an OPC (optical proximity correction) method, which comprises the following steps of: providing a target layer graph and a mask graph which are densely and alternately arranged, and enabling each edge of the target layer graph to be located in a range represented by the mask graph and to freely move in the range; a mask design rule is not set in a model-based OPC correction process, so that the target layer pattern freely moves in a range represented by the mask pattern until an expected simulation size is reached, and a target mask pattern is selected; and performing de-chamfering processing on the target mask pattern, measuring the target mask after de-chamfering processing to evaluate whether the target mask violates the mask design rule, if the target mask violates the mask design rule, continuing de-chamfering processing, and if the target mask does not violate the mask design rule, continuing de-chamfering processing. And performing model simulation on the target mask and evaluating whether the target mask reaches the expected simulation size of the target layer graph. According to the invention, the problem that a mask design rule is easy to violate in an existing OPC correction iteration process is solved.

Description

Technical Field

[0001] The invention relates to the technical field of semiconductor manufacturing, and in particular to an OPC correction method. Background Art

[0002] In the semiconductor manufacturing process, due to the optical proximity effect, photolithography exposure will produce graphic distortion, including corner rounding, line end shortening and proximity effect between graphics. Optical proximity correction (OPC) is to correct the graphic distortion caused by optical interference and diffraction effects, so OPC has become an indispensable part of the semiconductor manufacturing process. With the reduction of semiconductor manufacturing process nodes, especially the process nodes below 14nm, the critical size of the graphics is close to the lithography limit, and the graphic structure is relatively more complex, and OPC correction faces a huge challenge.

[0003] The via layer plays a connecting role in chip manufacturing and is generally used for MOS structure interconnection and metal layer interconnection. As the process node decreases, the MOS structure unit becomes compact, and the minimum line width and spacing of the via layer process will also decrease accordingly. The staggered structure is a common structure of the via layer. Its typical feature is that the angle-to-angle spacing between the graphics is generally less than 20nm. OPC correction is essentially an iterative process, and the predicted contour is infinitely close to the target value through model simulation. During the correction process, the mask design rules (MRC) are set manually, including the minimum critical dimension (CD) of the mask analysis and the minimum spacing (space) of the mask analysis, and the setting principle of MRC is generally determined by the process node. For the staggered via structure in OPC correction, since the spacing between the graphics is very small, the OPC correction space is very limited, and generally after several iterative cycles, the MRC will be violated. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide an OPC correction method for solving the problem that mask design rules are easily violated during the prior OPC correction iteration process.

[0005] To achieve the above object and other related objects, the present invention provides an OPC correction method, the method comprising:

[0006] Providing densely staggered target layer patterns and mask patterns, wherein the target layer pattern has the same shape as the mask pattern, and each side of the target layer pattern is within the range represented by the mask pattern and can move freely within the range;

[0007] In the model-based OPC correction process, mask design rules are not set, so that the target layer pattern is freely moved within the range represented by the mask pattern until the expected simulation size is reached, and a target mask pattern is selected, wherein the target mask pattern is a pattern that violates the mask design rules;

[0008] Performing a de-horning process on the target mask pattern, and measuring the target mask after the de-horning process to evaluate whether it violates the mask design rules, if it violates the mask design rules, continuing the de-horning process, and if it does not violate the mask design rules, performing a model simulation on the target mask and evaluating whether it reaches the expected simulation size of the target layer pattern;

[0009] The mask design rules include the minimum critical dimension of mask resolution and the minimum spacing of mask resolution. If the critical dimension of the target mask pattern is smaller than the minimum critical dimension of mask resolution and its spacing is smaller than the minimum spacing of mask resolution, it is a violation of the mask design rules.

[0010] Optionally, the target layer pattern and the mask pattern are square patterns, and the target layer pattern is used to form a through hole on a wafer.

[0011] Optionally, the densely staggered target layer patterns and mask patterns are staggered in multiple rows and columns, and the target layer patterns / mask patterns in the next adjacent row are on the same angle line as the target layer patterns / mask patterns in the previous row.

[0012] Optionally, a spacing between the mask patterns in a next row and the mask patterns in an adjacent previous row is less than 20 nm.

[0013] Optionally, if the mask design rule is violated, the method of continuing the dehorning process includes:

[0014] The de-cornering size is increased in steps of 1 nm to obtain a new de-cornering size, and the target mask is processed with the new de-cornering size, wherein the de-cornering process for the target mask is to remove the four corners of the target mask, and the removed corners are isosceles triangles, and the length of the side where the vertex is located is the de-cornering size.

[0015] Optionally, the mask design rule is determined by a process node.

[0016] Optionally, for a 14 nm process node, the value of the minimum critical dimension resolved by the mask is 18 nm, and the value of the minimum spacing resolved by the mask is 12 nm.

[0017] Optionally, for a target mask pattern that meets the mask design rules, a model simulation is performed on it, and it is checked whether the simulation profile, PVband and Meef meet the requirements. If so, the final required target mask pattern and its corresponding corner removal size are obtained.

[0018] Optionally, the model-based OPC correction includes multiple iterative loop operations.

[0019] As described above, the OPC correction method of the present invention is aimed at the through-hole layer, takes the dense interlaced structure as the research object, and proposes to solve the MRC problem by de-cornering the mask pattern. In the implementation process, the target layer pattern is first subjected to conventional MBOPC correction, and the MRC parameters are not set during the correction process, so that the target layer pattern moves to the ideal position; then the mask pattern that violates the MRC is selected and repaired; the appropriate de-cornering size is selected, and the mask pattern is de-cornered, the purpose of which is to eliminate the MRC; the selection of the de-cornering size is determined by the results of the model simulation, and the gradient controls the de-cornering size from 0 to a certain value until it does not violate the MRC, and at this time the model simulation size is close to the target size, thereby solving the problem of violating the MRC during the correction process. By repairing and optimizing the de-cornering size of the mask pattern, the simulation contour of the exposure pattern is not only on-target, but also the pvband and meef under the PW (process window) conditions meet the mass production requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 Shown is a flow chart of the OPC correction method of the present invention.

[0021] Figure 2 Shown is a schematic diagram of the target layer diagram of the present invention.

[0022] Figure 3 Shown is a schematic diagram of the photomask pattern of the present invention.

[0023] Figure 4 Shown is a schematic diagram of the exfoliation size control of the present invention.

[0024] Figure 5 Shown are schematic diagrams of mask patterns corresponding to different de-cornering sizes of the present invention. DETAILED DESCRIPTION

[0025] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0026] See also Figures 1 to 5 It should be noted that the illustrations provided in this embodiment are only schematic illustrations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation, the form, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout may also be more complicated.

[0027] like Figure 1 As shown, this embodiment provides an OPC correction method, the method comprising:

[0028] Providing densely staggered target layer patterns and mask patterns, wherein the target layer pattern has the same shape as the mask pattern, and each side of the target layer pattern is within the range represented by the mask pattern and can move freely within the range;

[0029] In the model-based OPC correction process, mask design rules are not set, so that the target layer pattern is freely moved within the range represented by the mask pattern until the expected simulation size is reached, and a target mask pattern is selected, wherein the target mask pattern is a pattern that violates the mask design rules;

[0030] Performing a de-horning process on the target mask pattern, and measuring the target mask after the de-horning process to evaluate whether it violates the mask design rules, if it violates the mask design rules, continuing the de-horning process, and if it does not violate the mask design rules, performing a model simulation on the target mask and evaluating whether it reaches the expected simulation size of the target layer pattern;

[0031] The mask design rules include the minimum critical dimension of mask resolution and the minimum spacing of mask resolution. If the critical dimension of the target mask pattern is smaller than the minimum critical dimension of mask resolution and its spacing is smaller than the minimum spacing of mask resolution, it is a violation of the mask design rules.

[0032] Specifically, the target layer pattern and the mask pattern are square patterns, and the target layer pattern is used to form a through hole on a wafer.

[0033] Specifically, the densely staggered target layer patterns and mask patterns are staggered in multiple rows and columns, and the target layer patterns / mask patterns in the next adjacent row are on the same angle line as the target layer patterns / mask patterns in the previous row.

[0034] Specifically, the spacing between the mask patterns in the next row and the mask patterns in the previous row adjacent thereto is less than 20 nm.

[0035] Specifically, if the mask design rules are violated, the method for continuing the dehorning process includes: increasing the dehorning size by a step size of 1 nm to obtain a new dehorning size, and processing the target mask with the new dehorning size, wherein the dehorning process for the target mask is to remove the four corners of the target mask, and the removed corners are isosceles triangles, and the length of the side where the vertex is located is the dehorning size.

[0036] Specifically, the mask design rule is determined by the process node.

[0037] Specifically, for a 14 nm process node, the value of the minimum critical dimension resolved by the mask is 18 nm, and the value of the minimum spacing resolved by the mask is 12 nm.

[0038] Specifically, for the target mask pattern that meets the mask design rules, a model simulation is performed on it, and it is checked whether the simulation profile, PVband and Meef meet the requirements. If they do, the final required target mask pattern and its corresponding corner removal size are obtained.

[0039] In this embodiment, PVband is a process fluctuation bandwidth value, and Meef is a mask error enhancement factor.

[0040] Specifically, the model-based OPC correction includes multiple iterative loop operations.

[0041] like Figure 2 to Figure 5 As shown, in this embodiment, taking the 14nm node as an example, the minimum critical dimension of the mask resolution of the model-based OPC (MBOPC) mask design rule (MRC) is set to 18nm, the minimum spacing of the mask resolution is 12nm, and the corner-to-corner pitch is 110nm (where 67*1.414+15.4=110nm), the size of the target layer pattern is 67nm, and the staggered hole structure with a corner-to-corner spacing of 15.4nm is used as the research object. The edge of the target mask pattern is processed in three sections, and the de-cornering size is adjusted to 0nm, 5nm, 10nm, 15nm and 20nm respectively, to study the influence of different de-cornering sizes on the mask design rules. When the de-cornering size is 0nm, Figure 3As shown in the figure, the size of the target mask pattern is 70.9nm*73.6nm, and the spacing Space between the target mask patterns is 8.8nm, which is less than the set MRC space 12nm, violating the mask design rule space 12nm. When the de-cornering size is 0nm, the spacing between the target mask patterns is only 8.8nm, violating the MRC. The purpose of de-cornering the target mask pattern is to solve the MRC problem, and at the same time, the contour / pw_cd / PVband / Meef parameters must be equivalent to the target mask pattern, that is, the contour is allowed to vary by + / -1.0nm, pw_cd / PVband varies by + / -0.5nm, and Meef<=4.5. In addition, the larger the spacing between the target mask patterns, the better. When the target mask pattern removal angle size is 5nm, the spacing between the target mask patterns will increase to 15.2nm, the simulation size under normal conditions is 68.6nm, the process window exposure dose is reduced by 4%, the pw_cd is 64nm when the focus plane is moved up by 35nm, the PVband is 3.9nm, and the meef is 4.1nm. Compared with the unrepaired target mask pattern, contourcd has increased by 1.4nm and pw_cd has increased by 1.5nm. When the target mask pattern removal angle size is 7nm, the spacing between the target mask patterns will increase to 18.1nm, the simulation size under normal conditions is 67.3nm, the process window exposure dose is reduced by 4%, the pw_cd is 62.5nm when the focus plane is moved up by 35nm, the PVband is 4.0nm, and the Meef is 4.2nm. Its parameters are almost the same as those of the unrepaired target mask pattern. Therefore, 7nm is the optimal de-cornering length. When the target mask pattern removal angle size is 15nm, the spacing between the target mask patterns will increase to 30.02nm, the simulation size under normal conditions is 55.2nm, the process window exposure dose is reduced by 4%, the pw_cd is 48.5nm when the focus plane moves up 35nm, the PVband is 5.5nm, and the Meef is 5.6nm. Compared with the unrepaired target mask pattern, the simulation parameters are quite different and cannot meet the mass production requirements. Table 1 provides the simulation results under different de-cornering sizes.

[0042] Table 1:

[0043]

[0044] Figure 5 In the figure, the light blue box represents the target value after the target layer pattern is freely moved, the entire purple area represents the target mask pattern, and the red circle represents the simulation contour. Figure 3 It can be seen that when the de-cornering length is 0nm, the spacing between the target mask patterns is only 8.8nm, which violates the MRC. Figure 3 The target mask in the image is de-cornified and repaired. When the de-cornering length is 6nm and 8nm, the simulation contour reaches the target value, but when the de-cornering length is increased to 10nm and 15nm, the simulation contour deviates from the target value. Therefore, combined with the above experimental results, the de-cornering size of the target mask pattern is not the larger the better. When the de-cornering size is between 5nm and 8nm, it can meet the simulation requirements of MRC and contour at the same time.

[0045] In summary, the OPC correction method of the present invention is aimed at the through-hole layer, takes the dense interlaced structure as the research object, and proposes to solve the MRC problem by de-cornering the mask pattern. In the implementation process, the target layer pattern is first subjected to conventional MBOPC correction, and the MRC parameters are not set during the correction process, so that the target layer pattern moves to the ideal position; then the mask pattern that violates the MRC is selected and repaired; a suitable de-cornering size is selected, and the mask pattern is de-cornered, the purpose of which is to eliminate the MRC; the selection of the de-cornering size is determined by the results of the model simulation, and the gradient controls the de-cornering size from 0 to a certain value until it does not violate the MRC, and at this time the model simulation size is close to the target size, thereby solving the problem of violating the MRC during the correction process. By repairing and optimizing the de-cornering size of the mask pattern, the simulation contour of the exposure pattern is not only on-target, but also PVband and Meef under the PW (process window) conditions meet the mass production requirements. Therefore, the present invention effectively overcomes the various shortcomings in the prior art and has a high industrial utilization value.

[0046] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. An OPC correction method, characterized in that: The method comprises: Providing densely staggered target layer patterns and mask patterns, wherein the target layer pattern has the same shape as the mask pattern, and each side of the target layer pattern is within the range represented by the mask pattern and can move freely within the range; In the model-based OPC correction process, mask design rules are not set, so that the target layer pattern is freely moved within the range represented by the mask pattern until the expected simulation size is reached, and a target mask pattern is selected, wherein the target mask pattern is a pattern that violates the mask design rules; Performing a de-horning process on the target mask pattern, and measuring the target mask after the de-horning process to evaluate whether it violates the mask design rules, if it violates the mask design rules, continuing the de-horning process, and if it does not violate the mask design rules, performing a model simulation on the target mask and evaluating whether it reaches the expected simulation size of the target layer pattern; The mask design rules include the minimum critical dimension of mask resolution and the minimum spacing of mask resolution. If the critical dimension of the target mask pattern is smaller than the minimum critical dimension of mask resolution and its spacing is smaller than the minimum spacing of mask resolution, it is a violation of the mask design rules.

2. The OPC correction method according to claim 1, characterized in that: The target layer pattern and the mask pattern are square patterns, and the target layer pattern is used to form a through hole on a wafer.

3. The OPC correction method according to claim 2, characterized in that: The densely staggered target layer patterns and mask patterns are staggered in multiple rows and columns, and the target layer patterns / mask patterns in the next adjacent row are on the same angle line as the target layer patterns / mask patterns in the previous row.

4. The OPC correction method according to claim 3, characterized in that: The spacing between the mask pattern in the next row and the mask pattern in the previous row adjacent thereto is less than 20 nm.

5. The OPC correction method according to claim 1, characterized in that: If the mask design rules are violated, the method of continuing the dehorning process includes: The de-cornering size is increased in steps of 1 nm to obtain a new de-cornering size, and the target mask is processed with the new de-cornering size, wherein the de-cornering process for the target mask is to remove the four corners of the target mask, and the removed corners are isosceles triangles, and the length of the side where the vertex is located is the de-cornering size.

6. The OPC correction method according to claim 1, characterized in that: The mask design rules are determined by the process node.

7. The OPC correction method according to claim 6, characterized in that: For the 14 nm process node, the value of the minimum critical dimension resolved by the mask is 18 nm, and the value of the minimum spacing resolved by the mask is 12 nm.

8. The OPC correction method according to claim 1, characterized in that: For the target mask pattern that meets the mask design rules, a model simulation is performed on it, and it is checked whether the simulation profile, PVband and Meef meet the requirements. If they do, the final required target mask pattern and its corresponding de-cornering size are obtained.

9. The OPC correction method according to claim 1, characterized in that: The model-based OPC correction involves multiple iterative cycles.

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